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User's Manual
V850ES/KF1 , V850ES/KG1 , V850ES/KJ1
32-Bit Single-Chip Microcontrollers Hardware
TM
TM
TM
V850ES/KF1: PD703208 PD703208(A) PD703208Y PD703208Y(A) PD703209 PD703209(A) PD703209Y PD703209Y(A) PD703210 PD703210(A) PD703210Y PD703210Y(A) PD70F3210 PD70F3210(A) PD70F3210Y PD70F3210Y(A)
V850ES/KG1: PD703212 PD703212(A) PD703212Y PD703212Y(A) PD703213 PD703213(A) PD703213Y PD703213Y(A) PD703214 PD703214(A) PD703214Y PD703214Y(A) PD70F3214 PD70F3214(A) PD70F3214Y PD70F3214Y(A)
V850ES/KJ1: PD703216 PD703216(A) PD703216Y PD703216Y(A) PD703217 PD703217(A) PD703217Y PD703217Y(A) PD70F3217 PD70F3217(A) PD70F3217Y PD70F3217Y(A)
Document No. U15862EJ3V0UD00 (3rd edition) Date Published January 2003 N CP(K) 2002 Printed in Japan
[MEMO]
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User's Manual U15862EJ3V0UD
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Purchase of NEC Electronics I C components conveys a license under the Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips.
2 2
2
2
V850 Series, V850ES/KF1, V850ES/KG1, and V850ES/KJ1 are trademarks of NEC Electronics Corporation.
User's Manual U15862EJ3V0UD
3
These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited.
* The information in this document is current as of November, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11-1
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User's Manual U15862EJ3V0UD
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics America, Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
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Novena Square, Singapore Tel: 6253-8311 Fax: 6250-3583
J02.11
User's Manual U15862EJ3V0UD
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Major Revisions in This Edition (1/2)
Pages Description
Throughout * Addition of the following special quality grade products. PD703208(A), 703208Y(A), 703209(A), 703209Y(A), 703210(A), 703210Y(A), 703212(A), 703212Y(A), 703213(A), 703213Y(A), 703214(A), 703214Y(A), 703216(A), 703216Y(A), 703217(A), 703217Y(A), 70F3210(A), 70F3210Y(A), 70F3214(A), 70F3214Y(A), 70F3217(A), 70F3217Y(A) p. 33 p. 41 p. 49 p. 55 Addition of Caution in 1.2.4 Pin configuration (top view) (V850ES/KF1) Addition of Caution in 1.3.4 Pin configuration (top view) (V850ES/KG1) Addition of Caution in 1.4.4 Pin configuration (top view) (V850ES/KJ1) Addition of description in CHAPTER 2 PIN FUNCTIONS and addition of Table 2-1 Pin I/O Buffer Power Supplies Modification of description on recommended connection of P70 to P77, P78 to P715, IC, VPP, and XT1 in 2.4 Pin I/O Circuits and Recommended Connection of Unused Pins Modification of description in 3.4.8 (2) Access to special on-chip peripheral I/O registers Modification of description in 5.11 Bus Timing Addition of 5.12 Cautions Addition of description on the main clock oscillator in 6.1 Overview Addition of description in 6.2 (1) Main clock oscillator Addition of Caution 3 in 6.3 (1) Processor clock control register (PCC) Addition of description in CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 Modification of description of Caution 4 in 7.2 (2) 16-bit timer capture/compare register 0n0 (CR0n0) Modification of description of Caution 4 in 7.2 (3) 16-bit timer capture/compare register 0n1 (CR0n1) Modification of description of Caution 1 in 7.3 (3) 16-bit timer output control register 0n (TOC0n) Addition of setting procedures and modification of description in 7.4.1 Operation as interval timer (16 bits) Addition of setting procedures in 7.4.2 PPG output operation Addition of Figure 7-6 Configuration of PPG Output Addition of Figure 7-7 PPG Output Operation Timing Addition of setting procedures in 7.4.3 Pulse width measurement Addition of setting procedures and addition of Caution 2 in 7.4.4 Operation as external event counter (16-bit timer/event counters 00, 01, 04 and 05 only) Addition of setting procedures and addition of Caution in 7.4.5 Square-wave output operation (16-bit timer/event counters 04 and 05 only) Addition of setting procedures in 7.4.6 One-shot pulse output operation Addition of Caution 2 in 7.4.6 (1) One-shot pulse output with software trigger Addition of Caution 2 in 7.4.6 (2) One-shot pulse output with external trigger Addition of Caution in 7.4.7 (10) (b) When setting CR0n0, CR0n1 to compare mode Addition of description in CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Addition of description in CHAPTER 9 8-BIT TIMERS H0 AND H1 Addition of Caution 3 in 9.3 (1) (a) 8-bit timer H mode register 0 (TMHMD0) Addition of Caution 3 in 9.3 (1) (b) 8-bit timer H mode register 1 (TMHMD1) Addition of Caution 2 in Figure 9-7 Transfer Timing Addition of Caution 4 in 9.4.3 (4) Timing chart Addition of 13.4 Relationship Between Analog Input Voltage and A/D Conversion Result
pp.93, 95
p. 134 p. 285 p. 291 p. 292 p. 293 p. 296 p. 302 p. 306 p. 307 p. 311 p. 319 p. 322 p. 324 p. 325 p. 326 p. 334
p. 337
p. 340 p. 340 p. 342 p. 349 p. 350 p. 369 p. 373 p. 374 p. 386 p. 388 p. 427
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User's Manual U15862EJ3V0UD
Major Revisions in This Edition (2/2)
Pages p. 430 p. 432 p. 441 p. 458 p. 473 p. 501 Description Addition of 13.6 (3) A/D converter sampling time and A/D conversion start delay time Addition of 13.7 How to Read A/D Converter Characteristics Table Addition of description in CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) Modification of description in Figure 15-6 Continuous Transmission Starting Procedure Addition of description in CHAPTER 16 CLOCKED SERIAL INTERFACE 0 (CSI0) Modification of description in CHAPTER 17 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION Addition of description in CHAPTER 18 I2C BUS Addition of Cautions in Table 25-1 Wiring Between PD70F3210 and 70F3210Y (V850ES/KF1), and PG-FP3 Addition of Figure 25-1 Wiring Example of V850ES/KF1 Flash Writing Adapter (FA-80GC-8BT, FA-80GK-9EU) Addition of Cautions in Table 25-2 Wiring Between PD70F3214 and 70F3214Y (V850ES/KG1), and PG-FP3 Addition of Figure 25-2 Wiring Example of V850ES/KG1 Flash Writing Adapter (FA-100GC-8EU) Addition of Cautions in Table 25-3 Wiring Between PD70F3217 and 70F3217Y (V850ES/KJ1), and PG-FP3 Addition of Figure 25-3 Wiring Example of V850ES/KJ1 Flash Writing Adapter (FA-144GJ-UEN) Addition of Note 1 and description in Absolute Maximum Ratings in CHAPTER 26 ELECTRICAL SPECIFICATIONS Addition of description on storage temperature in Absolute Maximum Ratings in CHAPTER 26 ELECTRICAL SPECIFICATIONS Addition of (i) Murata Manufacturing Co., Ltd.: Ceramic resonator (TA = -40 to +85C) in CHAPTER 26 ELECTRICAL SPECIFICATIONS Change of values of supply current (flash memory version) in DC Characteristics in CHAPTER 26 ELECTRICAL SPECIFICATIONS Change of values of supply current (mask ROM version) in DC Characteristics in CHAPTER 26 ELECTRICAL SPECIFICATIONS Addition of Caution and a timing chart in Data Retention Characteristics in CHAPTER 26 ELECTRICAL SPECIFICATIONS Addition of Caution in Bus Timing (1) (a) CLKOUT asynchronous: In multiplex bus mode (2/2) in CHAPTER 26 ELECTRICAL SPECIFICATIONS Addition of Caution 2 in Bus Timing (2) (a) Read cycle (CLKOUT asynchronous): In separate bus mode (1/2) in CHAPTER 26 ELECTRICAL SPECIFICATIONS Addition of Cautions in Bus Timing (2) (a) Read cycle (CLKOUT asynchronous): In separate bus mode (2/2) in CHAPTER 26 ELECTRICAL SPECIFICATIONS Addition of Caution 2 in Bus Timing (2) (c) Write cycle (CLKOUT asynchronous): In separate bus mode (1/2) in CHAPTER 26 ELECTRICAL SPECIFICATIONS Addition of Cautions in Bus Timing (2) (c) Write cycle (CLKOUT asynchronous): In separate bus mode (2/2) in CHAPTER 26 ELECTRICAL SPECIFICATIONS Addition of description in Basic Operation in CHAPTER 26 ELECTRICAL SPECIFICATIONS Addition of description in Flash Memory Programming Characteristics in CHAPTER 26 ELECTRICAL SPECIFICATIONS Addition of CHAPTER 28 RECOMMENDED SOLDERING CONDITIONS Addition of APPENDIX B REVISION HISTORY The mark shows major revised points.
p. 544 p. 682 p. 683 p. 684 p. 685 p. 686 p. 687 p. 699
p. 700
p. 704
p. 709
p. 710
p. 711
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p. 745 p. 755
User's Manual U15862EJ3V0UD
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PREFACE
Readers
This manual is intended for users who wish to understand the functions of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 and design application systems using these products. The target products are as follows. * Standard products:
PD703208, 703208Y, 703209, 703209Y, 703210, 703210Y,
703212, 703212Y, 703213, 703213Y, 703214, 703214Y, 703216, 703216Y, 703217, 703217Y, 70F3210, 70F3210Y, 70F3214, 70F3214Y, 70F3217, 70F3217Y
* Special products:
PD703208(A),
703208Y(A),
703209(A),
703209Y(A),
703210(A), 703210Y(A), 703212(A), 703212Y(A), 703213(A), 703213Y(A), 703214(A), 703214Y(A), 703216(A), 703216Y(A), 703217(A), 703217Y(A), 70F3210(A), 70F3210Y(A), 70F3214(A), 70F3214Y(A), 70F3217(A), 70F3217Y(A) Purpose This manual is intended to give users an understanding of the hardware functions of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 shown in the Organization below. Organization This manual is divided into two parts: Hardware (this manual) and Architecture (V850ES Architecture User's Manual). Hardware * Pin functions * CPU function * On-chip peripheral functions * Flash memory programming * Electrical specifications Architecture * Data types * Register set * Instruction format and instruction set * Interrupts and exceptions * Pipeline operation
How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. Cautions 1. The application examples in this manual apply to "standard" quality grade products for general electronic systems. When using an example in this manual for an application that requires a "special" quality grade product, thoroughly evaluate the component and circuit to be actually used to see if they satisfy the special quality grade. 2. When using this manual as a manual for a special grade product, read the part numbers as follows.
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User's Manual U15862EJ3V0UD
PD703208 PD703208Y PD703209 PD703209Y PD703210 PD703210Y PD703212 PD703212Y PD703213 PD703213Y PD703214

PD703208(A) PD703208Y(A) PD703209(A) PD703209Y(A) PD703210(A) PD703210Y(A) PD703212(A) PD703212Y(A) PD703213(A) PD703213Y(A) PD703214(A)
PD703214Y PD703216 PD703216Y PD703217 PD703217Y PD70F3210 PD70F3210Y PD70F3214 PD70F3214Y PD70F3217 PD70F3217Y

PD703214Y(A) PD703216(A) PD703216Y(A) PD703217(A) PD703217Y(A) PD70F3210(A) PD70F3210Y(A) PD70F3214(A) PD70F3214Y(A) PD70F3217(A) PD70F3217Y(A)
To find the details of a register where the name is known Refer to APPENDIX A REGISTER INDEX. To understand the details of an instruction function Refer to the V850ES Architecture User's Manual. Register format The name of the bit whose number is in angle brackets (<>) in the figure of the register format of each register is defined as a reserved word in the device file. To understand the overall functions of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 Read this manual according to the CONTENTS. To know the electrical specifications of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 Refer to CHAPTER 26 ELECTRICAL SPECIFICATIONS. Conventions Data significance: Memory map address: Note: Caution: Remark: Numeric representation: Higher digits on the left and lower digits on the right Higher addresses on the top and lower addresses on the bottom Footnote for item marked with Note in the text Information requiring particular attention Supplementary information Binary Decimal Hexadecimal K (kilo): G (giga):
10 20 30
Active low representation: xxx (overscore over pin or signal name)
... xxxx or xxxxB ... xxxx ... xxxxH
Prefix indicating power of 2 (address space, memory capacity): 2 = 1,024
2 3
M (mega): 2 = 1,024 2 = 1,024
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Related Documents
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/KF1, V850ES/KG1, and V850ES/KJ1
Document Name V850ES Architecture User's Manual V850ES/KF1, V850ES/KG1, V850ES/KJ1 Hardware User's Manual Document No. U15943E This manual
Documents related to development tools (user's manuals)
Document Name IE-V850ES-G1 (In-Circuit Emulator) IE-703217-G1-EM1 (In-Circuit Emulator Option Board) CA850 Ver. 2.50 C Compiler Package Operation C Language PM plus Assembly Language ID850 Ver. 2.50 Integrated Debugger SM850 Ver. 2.50 System Simulator SM850 Ver. 2.00 or Later System Simulator RX850 Ver. 3.13 or Later Real-Time OS Operation Operation External Part User Open Interface Specifications Fundamental Installation Technical RX850 Pro Ver. 3.15 Real-Time OS Fundamental Installation Technical RD850 Ver. 3.01 Task Debugger RD850 Pro Ver. 3.01 Task Debugger AZ850 Ver. 3.0 System Performance Analyzer PG-FP3 Flash Memory Programmer PG-FP4 Flash Memory Programmer Document No. To be prepared To be prepared U16053E U16054E U16055E U16042E U16217E U15182E U14873E U13430E U13410E U13431E U13773E U13774E U13772E U13737E U13916E U14410E U13502E U15260E
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User's Manual U15862EJ3V0UD
CONTENTS
CHAPTER 1 INTRODUCTION .................................................................................................................29 1.1 V850ES/KF1, V850ES/KG1, and V850ES/KJ1 Product Lineup ...............................................29 1.2 V850ES/KF1 .................................................................................................................................31
1.2.1 1.2.2 1.2.3 1.2.4 1.2.5 Features (V850ES/KF1) .................................................................................................................31 Applications (V850ES/KF1) ............................................................................................................32 Ordering information (V850ES/KF1)...............................................................................................32 Pin configuration (top view) (V850ES/KF1) ....................................................................................33 Function block configuration (V850ES/KF1)...................................................................................35 Features (V850ES/KG1).................................................................................................................39 Applications (V850ES/KG1) ...........................................................................................................40 Ordering information (V850ES/KG1) ..............................................................................................40 Pin configuration (top view) (V850ES/KG1)....................................................................................41 Function block configuration (V850ES/KG1) ..................................................................................43 Features (V850ES/KJ1)..................................................................................................................47 Applications (V850ES/KJ1) ............................................................................................................48 Ordering information (V850ES/KJ1) ...............................................................................................48 Pin configuration (top view) (V850ES/KJ1).....................................................................................49 Function block configuration (V850ES/KJ1) ...................................................................................51
1.3
V850ES/KG1.................................................................................................................................39
1.3.1 1.3.2 1.3.3 1.3.4 1.3.5
1.4
V850ES/KJ1 .................................................................................................................................47
1.4.1 1.4.2 1.4.3 1.4.4 1.4.5
CHAPTER 2 PIN FUNCTIONS ................................................................................................................55 2.1 List of Pin Functions ..................................................................................................................55 2.2 Pin Status.....................................................................................................................................64 2.3 Description of Pin Functions .....................................................................................................66
2.3.1 2.3.2 2.3.3 V850ES/KF1...................................................................................................................................66 V850ES/KG1 ..................................................................................................................................74 V850ES/KJ1 ...................................................................................................................................83
2.4 2.5
Pin I/O Circuits and Recommended Connection of Unused Pins..........................................93 Pin I/O Circuits ............................................................................................................................96
CHAPTER 3 CPU FUNCTIONS ..............................................................................................................98 3.1 Features .......................................................................................................................................98 3.2 CPU Register Set ........................................................................................................................99
3.2.1 3.2.2 Program register set .....................................................................................................................100 System register set.......................................................................................................................101
3.3 3.4
Operation Modes.......................................................................................................................107 Address Space ..........................................................................................................................108
3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 CPU address space......................................................................................................................108 Image ...........................................................................................................................................109 Wraparound of CPU address space .............................................................................................110 Memory map.................................................................................................................................111 Areas ............................................................................................................................................113 Peripheral I/O registers.................................................................................................................119 Special registers ...........................................................................................................................131 Cautions .......................................................................................................................................134
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CHAPTER 4 PORT FUNCTIONS ..........................................................................................................137 4.1 Features .................................................................................................................................... 137
4.1.1 4.1.2 4.1.3 V850ES/KF1 ................................................................................................................................ 137 V850ES/KG1 ............................................................................................................................... 137 V850ES/KJ1 ................................................................................................................................ 137 V850ES/KF1 ................................................................................................................................ 138 V850ES/KG1 ............................................................................................................................... 139 V850ES/KJ1 ................................................................................................................................ 140 Port 0 ........................................................................................................................................... 142 Port 1 ........................................................................................................................................... 149 Port 3 ........................................................................................................................................... 153 Port 4 ........................................................................................................................................... 165 Port 5 ........................................................................................................................................... 172 Port 6 ........................................................................................................................................... 182 Port 7 ........................................................................................................................................... 194 Port 8 ........................................................................................................................................... 198 Port 9 ........................................................................................................................................... 204
4.2
Basic Port Configuration......................................................................................................... 138
4.2.1 4.2.2 4.2.3
4.3
Port Configuration.................................................................................................................... 141
4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 4.3.9
4.3.10 Port CD ........................................................................................................................................ 223 4.3.11 Port CM........................................................................................................................................ 227 4.3.12 Port CS ........................................................................................................................................ 234 4.3.13 Port CT ........................................................................................................................................ 240 4.3.14 Port DH ........................................................................................................................................ 246 4.3.15 Port DL ........................................................................................................................................ 251
4.4
Port Function Operation.......................................................................................................... 262
4.4.1 4.4.2 4.4.3 Write operation to I/O port ........................................................................................................... 262 Read operation from I/O port ....................................................................................................... 262 Arithmetic operation with I/O ports............................................................................................... 262
CHAPTER 5 BUS CONTROL FUNCTION ...........................................................................................263 5.1 Features .................................................................................................................................... 263 5.2 Bus Control Pins ...................................................................................................................... 263
5.2.1 5.2.2 Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed................... 265 Pin status in each operation mode............................................................................................... 265 Chip select control function.......................................................................................................... 269
5.3 5.4 5.5
Memory Block Function .......................................................................................................... 266
5.3.1
External Bus Interface Mode Control Function..................................................................... 269 Bus Access ............................................................................................................................... 270
5.5.1 5.5.2 5.5.3 Number of clocks for access........................................................................................................ 270 Bus size setting function .............................................................................................................. 270 Access by bus size ...................................................................................................................... 271 Programmable wait function ........................................................................................................ 277 External wait function................................................................................................................... 278 Relationship between programmable wait and external wait ....................................................... 279 Programmable address wait function........................................................................................... 280
5.6
Wait Function............................................................................................................................ 277
5.6.1 5.6.2 5.6.3 5.6.4
5.7 12
Idle State Insertion Function................................................................................................... 281
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5.8
Bus Hold Function ....................................................................................................................282
5.8.1 5.8.2 5.8.3 Functional outline .........................................................................................................................282 Bus hold procedure ......................................................................................................................283 Operation in power save mode.....................................................................................................283
5.9 5.10
Bus Priority................................................................................................................................284 Boundary Operation Conditions .............................................................................................284
5.10.1 Program space .............................................................................................................................284 5.10.2 Data space ...................................................................................................................................284
5.11 5.12
Bus Timing.................................................................................................................................285 Cautions.....................................................................................................................................291
CHAPTER 6 CLOCK GENERATION FUNCTION ...............................................................................292 6.1 Overview ....................................................................................................................................292 6.2 Configuration.............................................................................................................................293 6.3 Control Registers ......................................................................................................................295 6.4 Operation ...................................................................................................................................299
6.4.1 6.4.2 6.4.3 Operation of each clock................................................................................................................299 Clock output function ....................................................................................................................299 External clock input function.........................................................................................................299 Overview ......................................................................................................................................300 Control register .............................................................................................................................300 Usage ...........................................................................................................................................301
6.5
PLL Function .............................................................................................................................300
6.5.1 6.5.2 6.5.3
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 ............................................................302 7.1 Functions ...................................................................................................................................302 7.2 Configuration.............................................................................................................................303 7.3 Control Registers ......................................................................................................................308 7.4 Operation ...................................................................................................................................319
7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 Operation as interval timer (16 bits)..............................................................................................319 PPG output operation ...................................................................................................................322 Pulse width measurement ............................................................................................................326 Operation as external event counter.............................................................................................334 Square-wave output operation .....................................................................................................337 One-shot pulse output operation ..................................................................................................340 Cautions .......................................................................................................................................345
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 ...........................................................350 8.1 Functions ...................................................................................................................................350 8.2 Configuration.............................................................................................................................351 8.3 Control Registers ......................................................................................................................353 8.4 Operation ...................................................................................................................................356
8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.4.7 Operation as interval timer (8 bits)................................................................................................356 Operation as external event counter (8 bits).................................................................................358 Square-wave output operation (8-bit resolution)...........................................................................359 8-bit PWM output operation..........................................................................................................361 Operation as interval timer (16 bits)..............................................................................................364 Operation as external event counter (16 bits)...............................................................................366 Square-wave output operation (16-bit resolution).........................................................................367
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8.4.8
Cautions ...................................................................................................................................... 368
CHAPTER 9 8-BIT TIMERS H0 AND H1............................................................................................369 9.1 Functions .................................................................................................................................. 369 9.2 Configuration............................................................................................................................ 369 9.3 Control Registers ..................................................................................................................... 372 9.4 Operation .................................................................................................................................. 376
9.4.1 9.4.2 9.4.3 Operation as interval timer........................................................................................................... 376 PWM pulse generator mode operation ........................................................................................ 379 Carrier generator mode operation................................................................................................ 385
CHAPTER 10 REAL-TIME OUTPUT FUNCTION (RTO) ....................................................................392 10.1 Function .................................................................................................................................... 392 10.2 Configuration............................................................................................................................ 393 10.3 RTO Control Registers............................................................................................................. 394 10.4 Operation .................................................................................................................................. 396 10.5 Usage......................................................................................................................................... 397 10.6 Cautions .................................................................................................................................... 397 10.7 Security Function ..................................................................................................................... 398 CHAPTER 11 WATCH TIMER FUNCTIONS........................................................................................400 11.1 Functions .................................................................................................................................. 400 11.2 Configuration............................................................................................................................ 402 11.3 Watch Timer Control Registers .............................................................................................. 402 11.4 Operation .................................................................................................................................. 404
11.4.1 Operation as watch timer............................................................................................................. 404 11.4.2 Operation as interval timer........................................................................................................... 404 11.4.3 Cautions ...................................................................................................................................... 405
11.5
Prescaler 3 ................................................................................................................................ 406
11.5.1 Control registers .......................................................................................................................... 406 11.5.2 Generation of count clock ............................................................................................................ 407
CHAPTER 12 WATCHDOG TIMER FUNCTIONS ...............................................................................408 12.1 Watchdog Timer 1 .................................................................................................................... 408
12.1.1 Functions ..................................................................................................................................... 408 12.1.2 Configuration ............................................................................................................................... 410 12.1.3 Watchdog timer 1 control register ................................................................................................ 410 12.1.4 Operation ..................................................................................................................................... 413
12.2
Watchdog Timer 2 .................................................................................................................... 416
12.2.1 Functions ..................................................................................................................................... 416 12.2.2 Configuration ............................................................................................................................... 417 12.2.3 Watchdog timer 2 control register ................................................................................................ 417 12.2.4 Operation ..................................................................................................................................... 419
CHAPTER 13 A/D CONVERTER ..........................................................................................................420 13.1 Function .................................................................................................................................... 420 13.2 Configuration............................................................................................................................ 421 13.3 Control Registers ..................................................................................................................... 423 13.4 Relationship Between Analog Input Voltage and A/D Conversion Result ......................... 427 14
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13.5
Operation ...................................................................................................................................428
13.5.1 Basic operation.............................................................................................................................428 13.5.2 Conversion operation (software trigger mode) .............................................................................429 13.5.3 Power fail monitoring function ......................................................................................................429
13.6 13.7
Cautions.....................................................................................................................................430 How to Read A/D Converter Characteristics Table ...............................................................432
CHAPTER 14 D/A CONVERTER ..........................................................................................................436 14.1 Functions ...................................................................................................................................436 14.2 Configuration.............................................................................................................................437 14.3 D/A Converter Control Register...............................................................................................437 14.4 Operation ...................................................................................................................................439
14.4.1 Operation in normal mode ............................................................................................................439 14.4.2 Operation in real-time output mode ..............................................................................................439 14.4.3 Cautions .......................................................................................................................................440
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) .....................................................441 2 15.1 Selecting UART2 or I C1 Mode ................................................................................................441 15.2 Features .....................................................................................................................................442 15.3 Configuration.............................................................................................................................443 15.4 Control Registers ......................................................................................................................445 15.5 Interrupt Requests ....................................................................................................................452 15.6 Operation ...................................................................................................................................453
15.6.1 Data format...................................................................................................................................453 15.6.2 Transmit operation........................................................................................................................454 15.6.3 Continuous transmission operation ..............................................................................................456 15.6.4 Receive operation.........................................................................................................................460 15.6.5 Reception error.............................................................................................................................461 15.6.6 Parity types and corresponding operation ....................................................................................463 15.6.7 Receive data noise filter ...............................................................................................................464
15.7
Dedicated Baud Rate Generator n (BRGn).............................................................................465
15.7.1 Baud rate generator n (BRGn) configuration ................................................................................465 15.7.2 Serial clock generation .................................................................................................................466 15.7.3 Baud rate setting example............................................................................................................469 15.7.4 Allowable baud rate range during reception .................................................................................470 15.7.5 Transfer rate during continuous transmission...............................................................................472
15.8
Cautions.....................................................................................................................................472
CHAPTER 16 CLOCKED SERIAL INTERFACE 0 (CSI0).................................................................473 16.1 Features .....................................................................................................................................473 16.2 Configuration.............................................................................................................................474 16.3 Control Registers ......................................................................................................................477 16.4 Operation ...................................................................................................................................485
16.4.1 Single transfer mode ....................................................................................................................485 16.4.2 Repeat transfer mode...................................................................................................................492
16.5
Output Pins................................................................................................................................500
CHAPTER 17 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION .................................................................................501
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17.1 17.2 17.3 17.4
Functions .................................................................................................................................. 501 Configuration............................................................................................................................ 502 Control Registers ..................................................................................................................... 504 Operation .................................................................................................................................. 513
17.4.1 Operation stop mode ................................................................................................................... 513 17.4.2 3-wire serial I/O mode.................................................................................................................. 513 17.4.3 3-wire serial I/O mode with automatic transmit/receive function .................................................. 521
CHAPTER 18 I C BUS ...........................................................................................................................544 2 18.1 Selecting UART2 or I C1 Mode................................................................................................ 544 18.2 Features .................................................................................................................................... 545 18.3 Configuration............................................................................................................................ 548 18.4 Control Registers ..................................................................................................................... 550 18.5 Functions .................................................................................................................................. 563
18.5.1 Pin configuration .......................................................................................................................... 563
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18.6
I C Bus Definitions and Control Methods .............................................................................. 564
18.6.1 Start condition.............................................................................................................................. 564 18.6.2 Addresses.................................................................................................................................... 565 18.6.3 Transfer direction specification .................................................................................................... 566 18.6.4 Acknowledge signal (ACK) .......................................................................................................... 567 18.6.5 Stop condition .............................................................................................................................. 568 18.6.6 Wait signal (WAIT)....................................................................................................................... 569
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18.7
I C Interrupt Requests (INTIICn).............................................................................................. 571
18.7.1 Master device operation .............................................................................................................. 571 18.7.2 Slave device operation (when receiving slave address data (match with SVAn))........................ 574 18.7.3 Slave device operation (when receiving extension code) ............................................................ 578 18.7.4 Operation without communication................................................................................................ 582 18.7.5 Arbitration loss operation (operation as slave after arbitration loss) ............................................ 582 18.7.6 Operation when arbitration loss occurs (no communication after arbitration loss) ....................... 584
2
18.8 18.9 18.10 18.11 18.12 18.13 18.14 18.15 18.16
Interrupt Request (INTIICn) Generation Timing and Wait Control ...................................... 589 Address Match Detection Method .......................................................................................... 590 Error Detection ......................................................................................................................... 590 Extension Code ........................................................................................................................ 590 Arbitration ................................................................................................................................. 591 Wakeup Function ..................................................................................................................... 592 Communication Reservation .................................................................................................. 593 Cautions .................................................................................................................................... 596 Communication Operations .................................................................................................... 597
18.16.1 Master operations ........................................................................................................................ 597 18.16.2 Slave operation............................................................................................................................ 599
18.17 Timing of Data Communication .............................................................................................. 600 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION................................................607 19.1 Overview ................................................................................................................................... 607
19.1.1 Features ...................................................................................................................................... 607
19.2
Non-Maskable Interrupts ......................................................................................................... 614
19.2.1 Operation ..................................................................................................................................... 617 19.2.2 Restore ........................................................................................................................................ 618 19.2.3 NP flag......................................................................................................................................... 619
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19.2.4 Noise elimination for NMI pin........................................................................................................619 19.2.5 Edge detection function for NMI pin..............................................................................................620
19.3
Maskable Interrupts ..................................................................................................................622
19.3.1 Operation......................................................................................................................................622 19.3.2 Restore.........................................................................................................................................624 19.3.3 Priorities of maskable interrupts ...................................................................................................625 19.3.4 Interrupt control register (xxlCn) ...................................................................................................629 19.3.5 Interrupt mask registers 0 to 2 (IMR0 to IMR2).............................................................................634 19.3.6 In-service priority register (ISPR)..................................................................................................637 19.3.7 Maskable interrupt status flag.......................................................................................................638 19.3.8 Watchdog timer mode register 1 (WDTM1) ..................................................................................639 19.3.9 Elimination of noise from INTP0 to INTP6 ....................................................................................639 19.3.10 INTP0 to INTP6 edge detection function ......................................................................................640
19.4
Software Exceptions.................................................................................................................643
19.4.1 Operation......................................................................................................................................643 19.4.2 Restore.........................................................................................................................................644 19.4.3 Exception status flag (EP) ............................................................................................................645
19.5
Exception Trap ..........................................................................................................................646
19.5.1 Illegal op code ..............................................................................................................................646 19.5.2 Debug trap....................................................................................................................................648
19.6 19.7 19.8
Multiple Interrupt Servicing Control........................................................................................650 Interrupt Response Time..........................................................................................................652 Periods in Which Interrupts Are Not Acknowledged by CPU ..............................................653
CHAPTER 20 KEY INTERRUPT FUNCTION ......................................................................................654 20.1 Function .....................................................................................................................................654 20.2 Key Interrupt Control Register ................................................................................................655 CHAPTER 21 STANDBY FUNCTION ...................................................................................................656 21.1 Overview ....................................................................................................................................656 21.2 HALT Mode ................................................................................................................................659
21.2.1 Setting and operation status.........................................................................................................659 21.2.2 Releasing HALT mode .................................................................................................................659
21.3
IDLE Mode..................................................................................................................................661
21.3.1 Setting and operation status.........................................................................................................661 21.3.2 Releasing IDLE mode...................................................................................................................661
21.4 STOP Mode ...................................................................................................................................663
21.4.1 Setting and operation status.........................................................................................................663 21.4.2 Releasing STOP mode.................................................................................................................663
21.5 21.6
Securing Oscillation Stabilization Time .................................................................................665 Subclock Operation Mode........................................................................................................666
21.6.1 Setting and operation status.........................................................................................................666 21.6.2 Releasing subclock operation mode.............................................................................................666
21.7
Sub-IDLE Mode..........................................................................................................................668
21.7.1 Setting and operation status.........................................................................................................668 21.7.2 Releasing sub-IDLE mode............................................................................................................668
21.8
Control Registers ......................................................................................................................670
CHAPTER 22 RESET FUNCTION ........................................................................................................671
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22.1 22.2 22.3
Overview ................................................................................................................................... 671 Configuration............................................................................................................................ 671 Operation .................................................................................................................................. 672
CHAPTER 23 REGULATOR ..................................................................................................................675 23.1 Overview ................................................................................................................................... 675 23.2 Operation .................................................................................................................................. 675 CHAPTER 24 ROM CORRECTION FUNCTION..................................................................................677 24.1 Overview ................................................................................................................................... 677 24.2 Control Registers ..................................................................................................................... 678
24.2.1 Correction address registers 0 to 3 (CORAD0 to CORAD3)........................................................ 678 24.2.2 Correction control register (CORCN) ........................................................................................... 679
24.3
ROM Correction Operation and Program Flow ..................................................................... 679
CHAPTER 25 FLASH MEMORY ...........................................................................................................681 25.1 Features .................................................................................................................................... 681 25.2 Writing with Flash Programmer.............................................................................................. 682 25.3 Programming Environment..................................................................................................... 688 25.4 Communication Mode.............................................................................................................. 688 25.5 Pin Processing ......................................................................................................................... 691
25.5.1 VPP pin ......................................................................................................................................... 691 25.5.2 Serial interface pins ..................................................................................................................... 692 25.5.3 RESET pin ................................................................................................................................... 694 25.5.4 Port pins ...................................................................................................................................... 694 25.5.5 Other signal pins.......................................................................................................................... 694 25.5.6 Power supply ............................................................................................................................... 694
25.6
Programming Method .............................................................................................................. 695
25.6.1 Controlling flash memory ............................................................................................................. 695 25.6.2 Flash memory programming mode .............................................................................................. 696 25.6.3 Selecting communication mode ................................................................................................... 696 25.6.4 Communication commands ......................................................................................................... 697 25.6.5 Resources used........................................................................................................................... 698
CHAPTER 26 ELECTRICAL SPECIFICATIONS ..................................................................................699 CHAPTER 27 PACKAGE DRAWINGS .................................................................................................741 CHAPTER 28 RECOMMENDED SOLDERING CONDITIONS ............................................................745 APPENDIX A REGISTER INDEX ..........................................................................................................748 APPENDIX B REVISION HISTORY ......................................................................................................755
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LIST OF FIGURES (1/6)
Figure No. 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 4-33 Title Page
CPU Address Space .................................................................................................................................. 108 Address Space Image................................................................................................................................ 109 Data Memory Map (Physical Addresses) ................................................................................................... 111 Program Memory Map ............................................................................................................................... 112 Internal ROM/Internal Flash Memory Area (128 KB) ................................................................................. 113 Internal ROM Area (96 KB) ........................................................................................................................ 114 Internal ROM Area (64 KB) ........................................................................................................................ 114 Internal RAM Area (6 KB) .......................................................................................................................... 116 Internal RAM Area (4 KB) .......................................................................................................................... 117 On-Chip Peripheral I/O Area ...................................................................................................................... 118 Block Diagram of P00 and P01 .................................................................................................................. 147 Block Diagram of P02 to P06 ..................................................................................................................... 148 Block Diagram of P10 and P11 .................................................................................................................. 152 Block Diagram of P30 ................................................................................................................................ 160 Block Diagram of P31, P32, and P34......................................................................................................... 161 Block Diagram of P33 and P35 .................................................................................................................. 162 Block Diagram of P36 and P37 .................................................................................................................. 163 Block Diagram of P38 and P39 .................................................................................................................. 164 Block Diagram of P40 ................................................................................................................................ 169 Block Diagram of P41 ................................................................................................................................ 170 Block Diagram of P42 ................................................................................................................................ 171 Block Diagram of P50, P51, and P53......................................................................................................... 178 Block Diagram of P52 ................................................................................................................................ 179 Block Diagram of P54 ................................................................................................................................ 180 Block Diagram of P55 ................................................................................................................................ 181 Block Diagram of P60 to P65, and P611.................................................................................................... 188 Block Diagram of P66, P69, P610, and P612 ............................................................................................ 189 Block Diagram of P67 ................................................................................................................................ 190 Block Diagram of P68 ................................................................................................................................ 191 Block Diagram of P613 .............................................................................................................................. 192 Block Diagram of P614 and P615 .............................................................................................................. 193 Block Diagram of P70 to P715 ................................................................................................................... 197 Block Diagram of P80 ................................................................................................................................ 202 Block Diagram of P81 ................................................................................................................................ 203 Block Diagram of P90, P92, P94, and P96 ................................................................................................ 217 Block Diagram of P91 ................................................................................................................................ 218 Block Diagram of P93, P95, P97, and P910 .............................................................................................. 219 Block Diagram of P98 and P911 ................................................................................................................ 220 Block Diagram of P99 and P912 ................................................................................................................ 221 Block Diagram of P913 to P915 ................................................................................................................. 222 Block Diagram of PCD0 to PCD3............................................................................................................... 226 Block Diagram of PCM0 and PCM3........................................................................................................... 231 Block Diagram of PCM1 and PCM2........................................................................................................... 232
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LIST OF FIGURES (2/6)
Figure No. 4-34 4-35 4-36 4-37 4-38 4-39 4-40 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 6-1 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 Title Page
Block Diagram of PCM4 and PCM5 ...........................................................................................................233 Block Diagram of PCS0 to PCS3 ...............................................................................................................238 Block Diagram of PCS4 to PCS7 ...............................................................................................................239 Block Diagram of PCT0, PCT1, PCT4, and PCT6 .....................................................................................244 Block Diagram of PCT2, PCT3, PCT5, and PCT7 .....................................................................................245 Block Diagram of PDH0 to PDH7...............................................................................................................250 Block Diagram of PDL0 to PDL15 ..............................................................................................................254 Data Memory Map (V850ES/KF1)..............................................................................................................266 Data Memory Map (V850ES/KG1) .............................................................................................................267 Data Memory Map (V850ES/KJ1) ..............................................................................................................268 Little Endian Address in Word ....................................................................................................................271 Example of Inserting Wait States ...............................................................................................................279 Multiplex Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access) ..................................................................285 Multiplex Bus Read Timing (Bus Size: 8 Bits) ............................................................................................285 Multiplex Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access)...................................................................286 Multiplex Bus Write Timing (Bus Size: 8 Bits) ............................................................................................286 Multiplex Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access)....................................................................287 Separate Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access) ..................................................................288 Separate Bus Read Timing (Bus Size: 8 Bits)............................................................................................288 Separate Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access) ..................................................................289 Separate Bus Write Timing (Bus Size: 8 Bits) ............................................................................................289 Separate Bus Hold Timing (Bus Size: 8 Bits, Write)...................................................................................290 Address Wait Timing (Separate Bus Read, Bus Size: 16 Bits, 16-Bit Access)...........................................290 Clock Generator .........................................................................................................................................293 Block Diagram of 16-Bit Timer/Event Counter 0n.......................................................................................304 Control Register Setting Contents During Interval Timer Operation ...........................................................320 Configuration of Interval Timer ...................................................................................................................320 Timing of Interval Timer Operation.............................................................................................................321 Control Register Settings in PPG Output Operation...................................................................................323 Configuration of PPG Output......................................................................................................................324 PPG Output Operation Timing ...................................................................................................................325 Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register .........................................................................................................................327 Configuration for Pulse Width Measurement with Free-Running Counter ..................................................327 Timing of Pulse Width Measurement with Free-Running Counter and One Capture Register (with Both Edges Specified) .......................................................................................................................328 Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter ..................329 CR0n1 Capture Operation with Rising Edge Specified ..............................................................................330 Timing of Pulse Width Measurement with Free-Running Counter (with Both Edges Specified).................330 Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers........................................................................................................................331
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Figure No. 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 7-26 7-27 7-28 7-29 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 10-1 10-2 10-3 11-1 11-2 11-3 11-4 Title Timing of Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) ...................................................................................................................... 332 Control Register Settings for Pulse Width Measurement by Restarting ..................................................... 333 Timing of Pulse Width Measurement by Restarting (with Rising Edge Specified)...................................... 333 Control Register Settings in External Event Counter Mode ....................................................................... 335 Configuration of External Event Counter.................................................................................................... 336 Timing of External Event Counter Operation (with Rising Edge Specified) ................................................ 336 Control Register Settings in Square-Wave Output Mode........................................................................... 338 Timing of Square-Wave Output Operation ................................................................................................. 339 Control Register Settings for One-Shot Pulse Output with Software Trigger ............................................. 341 Timing of One-Shot Pulse Output Operation with Software Trigger........................................................... 342 Control Register Settings for One-Shot Pulse Output with External Trigger .............................................. 343 Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) .............. 344 Start Timing of 16-Bit Timer Counter 0n .................................................................................................... 345 Data Hold Timing of Capture Register ....................................................................................................... 345 Operation Timing of OVF0n Flag ............................................................................................................... 347 Block Diagram of 8-Bit Timer/Event Counters 50 and 51........................................................................... 351 Timing of Interval Timer Operation............................................................................................................. 356 Timing of External Event Counter Operation (with Rising Edge Specified) ................................................ 358 Timing of Square-Wave Output Operation ................................................................................................. 360 Timing of PWM Output Operation .............................................................................................................. 362 Timing of Operation Based on CR5n Register Transitions ........................................................................ 363 Cascade Connection Mode with 16-Bit Resolution .................................................................................... 365 Start Timing of Timer 5n............................................................................................................................. 368 Block Diagram of 8-Bit Timers H0 and H1 ................................................................................................. 370 Register Settings in Interval Timer Mode ................................................................................................... 376 Timing of Interval Timer Operation............................................................................................................. 377 Register Settings in PWM Pulse Generator Mode ..................................................................................... 379 Operation Timing in PWM Pulse Generator Mode ..................................................................................... 381 Connection Example of 8-Bit Timer Hn and 8-Bit Timer/Event Counter 5n................................................ 385 Transfer Timing.......................................................................................................................................... 386 Register Settings in Carrier Generator Mode ............................................................................................. 387 Carrier Generator Mode ............................................................................................................................. 389 Block Diagram of RTO ............................................................................................................................... 392 Example of Operation Timing of RTO0 (When EXTR0 = 0, BYTE0 = 0) ................................................... 396 Block Diagram of Security Function ........................................................................................................... 398 Block Diagram of Watch Timer .................................................................................................................. 400 Block Diagram of Prescaler 3..................................................................................................................... 401 Operation Timing of Watch Timer/Interval Timer ....................................................................................... 405 Example of Generation of Watch Timer Interrupt Request (INTWT) (When Interrupt Period = 0.5 s)........ 405
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LIST OF FIGURES (4/6)
Figure No. 12-1 12-2 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 13-12 14-1 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 15-10 15-11 15-12 15-13 15-14 15-15 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 Title Page
Block Diagram of Watchdog Timer 1..........................................................................................................409 Block Diagram of Watchdog Timer 2..........................................................................................................416 Block Diagram of A/D Converter ................................................................................................................420 Operation Sequence ..................................................................................................................................424 Relationship Between Analog Input Voltages and A/D Conversion Results...............................................427 Power Fail Monitoring Function (PFCM = 0) ..............................................................................................429 Timing of A/D Converter Sampling and A/D Conversion Start Delay .........................................................430 Overall Error...............................................................................................................................................432 Quantization Error ......................................................................................................................................433 Zero-Scale Error.........................................................................................................................................433 Full-Scale Error ..........................................................................................................................................434 Differential Linearity Error...........................................................................................................................434 Integral Linearity Error................................................................................................................................435 Sampling Time ...........................................................................................................................................435 Block Diagram of D/A Converter ................................................................................................................436 Selecting Mode of UART2 or I C1 ..............................................................................................................441 Block Diagram of Asynchronous Serial Interface n ....................................................................................444 Format of Asynchronous Serial Interface Transmit/Receive Data..............................................................453 Asynchronous Serial Interface Transmission Completion Interrupt Timing ................................................455 Continuous Transmission Processing Flow................................................................................................457 Continuous Transmission Starting Procedure ............................................................................................458 Continuous Transmission End Procedure ..................................................................................................459 Asynchronous Serial Interface Reception Completion Interrupt Timing .....................................................461 When Reception Error Interrupt Is Separated from INTSRn Interrupt (ISRMn Bit = 0)...............................462 When Reception Error Interrupt Is Included in INTSRn Interrupt (ISRMn Bit = 1) ......................................462 Noise Filter Circuit......................................................................................................................................464 Timing of RXDn Signal Judged as Noise ...................................................................................................464 Configuration of Baud Rate Generator n (BRGn).......................................................................................465 Allowable Baud Rate Range During Reception..........................................................................................470 Transfer Rate During Continuous Transmission ........................................................................................472 Block Diagram of Clocked Serial Interface .................................................................................................476 Timing Chart in Single Transfer Mode........................................................................................................486 Timing Chart According to Clock Phase Selection .....................................................................................488 Timing Chart of Interrupt Request Signal Output in Delay Mode................................................................490 Repeat Transfer (Receive-Only) Timing Chart ...........................................................................................493 Repeat Transfer (Transmission/Reception) Timing Chart ..........................................................................495 Timing Chart of Next Transfer Reservation Period.....................................................................................496 Transfer Request Clear and Register Access Conflict ...............................................................................498 Interrupt Request and Register Access Conflict.........................................................................................499
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Figure No. 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 17-10 17-11 17-12 17-13 17-14 17-15 17-16 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 18-10 18-11 18-12 18-13 18-14 18-15 18-16 18-17 18-18 18-19 18-20 Title Page
Block Diagram of CSIAn ............................................................................................................................ 503 3-Wire Serial I/O Mode Timing................................................................................................................... 518 Format of Transmit/Receive Data .............................................................................................................. 519 Transfer Bit Order Switching Circuit........................................................................................................... 520 Automatic Transmission/Reception Mode Operation Timings.................................................................... 529 Automatic Transmission/Reception Mode Flowchart ................................................................................. 530 Internal Buffer RAM Operation in 6-Byte Transmission/Reception (in Automatic Transmission/Reception Mode)............................................................................................ 531 Automatic Transmission Mode Operation Timing ...................................................................................... 533 Automatic Transmission Mode Flowchart .................................................................................................. 534 Internal Buffer RAM Operation in 6-Byte Transmission (in Automatic Transmission Mode) ...................... 535 Repeat Transmission Mode Operation Timing........................................................................................... 537 Repeat Transmission Mode Flowchart....................................................................................................... 538 Internal Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmission Mode)........................... 539 Format of CSIAn Transmit/Receive Data ................................................................................................... 541 Automatic Transmission/Reception Suspension and Restart..................................................................... 542 Automatic Data Transmit/Receive Interval Time ........................................................................................ 543 Selecting Mode of UART2 or I C1.............................................................................................................. 544 Block Diagram of I Cn ................................................................................................................................ 546 Serial Bus Configuration Example Using I C Bus....................................................................................... 547 Pin Configuration Diagram ......................................................................................................................... 563 I C Bus's Serial Data Transfer Timing........................................................................................................ 564 Start Conditions ......................................................................................................................................... 564 Address...................................................................................................................................................... 562 Transfer Direction Specification ................................................................................................................. 566 ACK Signal................................................................................................................................................. 567 Stop Condition ........................................................................................................................................... 568 Wait Signal................................................................................................................................................. 569 Arbitration Timing Example ........................................................................................................................ 591 Communication Reservation Timing .......................................................................................................... 594 Timing for Accepting Communication Reservations................................................................................... 594 Communication Reservation Flowchart ..................................................................................................... 595 Master Operation Flowchart (1) ................................................................................................................. 597 Master Operation Flowchart (2) ................................................................................................................. 598 Slave Operation Flowchart......................................................................................................................... 599 Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) ..................................................................... 601 Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) ..................................................................... 604
2 2 2 2
19-1 19-2 19-3
Acknowledging Non-Maskable Interrupt Requests .................................................................................... 615 Non-Maskable Interrupt Servicing.............................................................................................................. 617 RETI Instruction Processing....................................................................................................................... 618
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LIST OF FIGURES (6/6)
Figure No. 19-4 19-5 19-6 19-7 19-8 19-9 19-10 19-11 19-12 19-13 19-14 20-1 21-1 21-2 22-1 22-2 22-3 23-1 23-2 24-1 24-2 25-1 25-2 25-3 25-4 25-5 25-6 25-7 25-8 25-9 25-10 25-11 25-12 25-13 25-14 Title Page
Maskable Interrupt Servicing......................................................................................................................623 RETI Instruction Processing.......................................................................................................................624 Example of Interrupt Nesting......................................................................................................................626 Example of Servicing Simultaneously Generated Interrupt Requests ........................................................628 Software Exception Processing..................................................................................................................643 RETI Instruction Processing.......................................................................................................................644 Exception Trap Processing ........................................................................................................................647 Processing Flow for Restore from Exception Trap .....................................................................................647 Debug Trap Processing..............................................................................................................................648 Processing Flow for Restore from Debug Trap ..........................................................................................649 Pipeline Operation During Interrupt Request Acknowledgment (Outline)...................................................652 Key Return Block Diagram .........................................................................................................................654 Status Transition ........................................................................................................................................657 Oscillation Stabilization Time .....................................................................................................................665 Reset Block Diagram..................................................................................................................................671 Hardware Status on RESET Input..............................................................................................................674 Operation on Power Application.................................................................................................................674 Regulator....................................................................................................................................................675 REGC Pin Connection................................................................................................................................676 Block Diagram of ROM Correction .............................................................................................................677 ROM Correction Operation and Program Flow ..........................................................................................680 Wiring Example of V850ES/KF1 Flash Writing Adapter (FA-80GC-8BT, FA-80GK-9EU) ..........................683 Wiring Example of V850ES/KG1 Flash Writing Adapter (FA-100GC-8EU) ................................................685 Wiring Example of V850ES/KJ1 Flash Writing Adapter (FA-144GJ-UEN) .................................................687 Environment for Writing Program to Flash Memory ...................................................................................688 Communication with Dedicated Flash Programmer (UART0) ....................................................................688 Communication with Dedicated Flash Programmer (CSI00) ......................................................................689 Communication with Flash Programmer (CSI00+HS) ................................................................................689 Example of Connection of VPP Pin .............................................................................................................691 Signal Collision (Input Pin of Serial Interface) ............................................................................................692 Malfunction of Other Device .......................................................................................................................693 Signal Collision (RESET Pin) .....................................................................................................................694 Flash Memory Manipulation Procedure......................................................................................................695 Flash Memory Programming Mode ............................................................................................................696 Communication Commands .......................................................................................................................697
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LIST OF TABLES (1/4)
Table No. 2-1 2-2 2-3 2-4 3-1 3-2 3-3 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 5-1 5-2 5-3 5-4 5-5 5-6 Title Page
Pin I/O Buffer Power Supplies...................................................................................................................... 55 Pin Operation Status in Operation Modes of V850ES/KF1 .......................................................................... 64 Pin Operation Status in Operation Modes of V850ES/KG1 ......................................................................... 65 Pin Operation Status in Operation Modes of V850ES/KJ1 .......................................................................... 65 Program Registers ..................................................................................................................................... 100 System Register Numbers ......................................................................................................................... 101 Interrupt/Exception Table ........................................................................................................................... 115 Port Configuration (V850ES/KF1) .............................................................................................................. 141 Port Configuration (V850ES/KG1) ............................................................................................................. 141 Port Configuration (V850ES/KJ1) .............................................................................................................. 141 Alternate-Function Pins of Port 0 ............................................................................................................... 142 Valid Edge Specification ............................................................................................................................ 146 Alternate-Function Pins of Port 1 (V850ES/KG1, V850ES/KJ1) ................................................................ 149 Alternate-Function Pins of Port 3 (V850ES/KF1) ....................................................................................... 154 Alternate-Function Pins of Port 3 (V850ES/KG1, V850ES/KJ1) ................................................................ 154 Alternate-Function Pins of Port 4 ............................................................................................................... 165 Alternate-Function Pins of Port 5 ............................................................................................................... 172 Alternate-Function Pins of Port 6 (V850ES/KJ1)........................................................................................ 182 Alternate-Function Pins of Port 7 (V850ES/KF1, V850ES/KG1) ................................................................ 194 Alternate-Function Pins of Port 7 (V850ES/KJ1)........................................................................................ 195 Alternate-Function Pins of Port 8 (V850ES/KJ1)........................................................................................ 198 Alternate-Function Pins of Port 9 (V850ES/KF1) ....................................................................................... 205 Alternate-Function Pins of Port 9 (V850ES/KG1, V850ES/KJ1) ................................................................ 205 Valid Edge Specification ............................................................................................................................ 216 Alternate-Function Pins of Port CD (V850ES/KJ1) .................................................................................... 223 Alternate-Function Pins of Port CM (V850ES/KF1, V850ES/KG1) ............................................................ 227 Alternate-Function Pins of Port CM (V850ES/KJ1) .................................................................................... 227 Alternate-Function Pins of Port CS (V850ES/KF1, V850ES/KG1) ............................................................. 234 Alternate-Function Pins of Port CS (V850ES/KJ1)..................................................................................... 234 Alternate-Function Pins of Port CT (V850ES/KF1, V850ES/KG1) ............................................................. 240 Alternate-Function Pins of Port CT (V850ES/KJ1)..................................................................................... 240 Alternate-Function Pins of Port DH (V850ES/KG1) ................................................................................... 246 Alternate-Function Pins of Port DH (V850ES/KJ1) .................................................................................... 246 Alternate-Function Pins of Port DL............................................................................................................. 251 Settings When Port Pins Are Used for Alternate Functions ....................................................................... 255 V850ES/KF1 Bus Control Pins................................................................................................................... 263 V850ES/KG1 Bus Control Pins .................................................................................................................. 264 V850ES/KJ1 Bus Control Pins ................................................................................................................... 264 V850ES/KG1 Bus Control Pins .................................................................................................................. 264 V850ES/KJ1 Bus Control Pins ................................................................................................................... 265 Pin Status When Internal ROM, Internal RAM, or On-Chip Peripheral I/O Is Accessed ............................ 265
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LIST OF TABLES (2/4)
Table No. 5-7 6-1 7-1 7-2 7-3 7-4 8-1 9-1 10-1 10-2 10-3 10-4 11-1 11-2 11-3 12-1 12-2 12-3 12-4 12-5 13-1 13-2 13-3 14-1 15-1 15-2 15-3 15-4 16-1 16-2 17-1 17-2 Title Page
Bus Priority.................................................................................................................................................284 Operation Status of Each Clock .................................................................................................................299 Configuration of 16-Bit Timer/Event Counters 00 to 05 ..............................................................................303 Valid Edge of TI0n0 Pin and Capture Trigger of CR0n0 Register ..............................................................305 Valid Edge of TI0n1 Pin and Capture Trigger of CR0n0 Register ..............................................................305 Valid Edge of TI0n0 Pin and Capture Trigger of CR0n1 Register ..............................................................307 Configuration of 8-Bit Timer/Event Counters 50 and 51 .............................................................................351 Configuration of 8-Bit Timers H0 and H1....................................................................................................369 Configuration of RTO .................................................................................................................................393 Operation During Manipulation of Real-Time Output Buffer Registers n ....................................................393 Operation Modes and Output Triggers of Real-Time Output Port (n = 0)...................................................395 Operation Modes and Output Triggers of Real-Time Output Port (n = 1, V850ES/KJ1 only) .....................395 Interval Time of Interval Timer....................................................................................................................401 Configuration of Watch Timer.....................................................................................................................402 Interval Time of Interval Timer....................................................................................................................404 Configuration of Watchdog Timer 1............................................................................................................410 Program Loop Detection Time of Watchdog Timer 1 .................................................................................414 Interval Time of Interval Timer....................................................................................................................415 Configuration of Watchdog Timer 2............................................................................................................417 Watchdog Timer 2 Clock Selection ............................................................................................................418 Configuration of A/D Converter ..................................................................................................................421 Operation Mode Control .............................................................................................................................424 A/D Converter Sampling Time and A/D Conversion Start Delay Time (ADM Set Value) ...........................431 Configuration of D/A Converter ..................................................................................................................437 Generated Interrupts and Default Priorities ................................................................................................452 Reception Error Causes .............................................................................................................................461 Baud Rate Generator Setting Data ............................................................................................................469 Maximum and Minimum Allowable Baud Rate Error ..................................................................................471 SCK0n Pin Output Status...........................................................................................................................500 SO0n Pin Output Status .............................................................................................................................500 Configuration of CSIAn...............................................................................................................................502 Relationship Between Buffer RAM Address Values and ADTP0 Register Setting Values .........................509
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LIST OF TABLES (3/4)
Table No. 17-3 17-4 17-5 17-6 17-7 18-1 18-2 18-3 18-4 18-5 18-6 19-1 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 20-1 21-1 21-2 21-3 21-4 21-5 21-6 21-7 21-8 21-9 21-10 22-1 22-2 24-1 25-1 25-2 25-3 Title Page
Relationship Between Buffer RAM Address Values and ADTP1 Register Setting Values ......................... 509 CSIA0 Buffer RAM ..................................................................................................................................... 511 CSIA1 Buffer RAM ..................................................................................................................................... 512 Relationship Between Buffer RAM Address Values and ADTP0 Register Setting Values ......................... 526 Relationship Between Buffer RAM Address Values and ADTP1 Register Setting Values ......................... 526 Configuration of I Cn .................................................................................................................................. 548 Selection Clock Setting .............................................................................................................................. 562 INTIICn Generation Timing and Wait Control............................................................................................. 589 Extension Code Bit Definitions................................................................................................................... 591 Status During Arbitration and Interrupt Request Generation Timing .......................................................... 592 Wait Periods............................................................................................................................................... 593 Interrupt Source List (V850ES/KF1)........................................................................................................... 608 Interrupt Source List (V850ES/KG1) .......................................................................................................... 610 Interrupt Source List (V850ES/KJ1) ........................................................................................................... 612 NMI Valid Edge Specification..................................................................................................................... 621 Interrupt Control Registers (xxlCn) (V850ES/KF1)..................................................................................... 630 Interrupt Control Registers (xxlCn) (V850ES/KG1) .................................................................................... 631 Interrupt Control Registers (xxlCn) (V850ES/KJ1) ..................................................................................... 632 INTP0 to INTP3 Pins Valid Edge Specification .......................................................................................... 641 INTP4 to INTP6 Pins Valid Edge Specification .......................................................................................... 642 Assignment of Key Return Detection Pins ................................................................................................. 654 Standby Modes .......................................................................................................................................... 656 Operation After Releasing HALT Mode by Interrupt Request .................................................................... 659 Operation Status in HALT Mode ................................................................................................................ 660 Operation After Releasing IDLE Mode by Interrupt Request...................................................................... 661 Operation Status in IDLE Mode ................................................................................................................. 662 Operation After Releasing STOP Mode by Interrupt Request.................................................................... 663 Operation Status in STOP Mode................................................................................................................ 664 Operation Status in Subclock Operation Mode .......................................................................................... 667 Operation After Releasing Sub-IDLE Mode by Interrupt Request .............................................................. 668 Operation Status in Sub-IDLE Mode.......................................................................................................... 669 Hardware Status on RESET Pin Input or Occurrence of WDTRES2 ......................................................... 673 Hardware Status on Occurrence of WDTRES1 ......................................................................................... 673 Correspondence Between CORCN Register Bits and CORADn Registers ............................................... 679 Wiring Between PD70F3210 and 70F3210Y (V850ES/KF1), and PG-FP3 ............................................. 682 Wiring Between PD70F3214 and 70F3214Y (V850ES/KG1), and PG-FP3............................................. 684 Wiring Between PD70F3217 and 70F3217Y (V850ES/KJ1), and PG-FP3.............................................. 686
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LIST OF TABLES (4/4)
Table No. 25-4 25-5 25-6 25-7 25-8 28-1 Title Page
Signals Generated by Dedicated Flash Programmer (PG-FP3).................................................................690 Pins Used by Each Serial Interface............................................................................................................692 Communication Modes...............................................................................................................................696 Flash Memory Control Commands.............................................................................................................697 Response Commands................................................................................................................................698 Surface Mounting Type Soldering Conditions ............................................................................................745
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1.1 V850ES/KF1, V850ES/KG1, and V850ES/KJ1 Product Lineup
V850ES/KJ1 144-pin plastic LQFP (fine pitch) (20 x 20)
PD70F3217 PD70F3217Y PD703217 PD703217Y PD703216 PD703216Y
Flash memory: 128 KB, RAM: 6 KB I2C bus version Mask ROM: 128 KB, RAM: 6 KB I2C bus version Mask ROM: 96 KB, RAM: 6 KB I2C bus version
V850ES/KG1 100-pin plastic LQFP (fine pitch) (14 x 14)
PD70F3214 PD70F3214Y PD703214 PD703214Y PD703213 PD703213Y PD703212 PD703212Y
Flash memory: 128 KB, RAM: 6 KB I2C bus version Mask ROM: 128 KB, RAM: 6 KB I2C bus version Mask ROM: 96 KB, RAM: 4 KB I2C bus version Mask ROM: 64 KB, RAM: 4 KB I2C bus version
V850ES/KF1
80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12)
PD70F3210 PD70F3210Y PD703210 PD703210Y PD703209 PD703209Y PD703208 PD703208Y
Flash memory: 128 KB, RAM: 6 KB I2C bus version Mask ROM: 128 KB, RAM: 6 KB I2C bus version Mask ROM: 96 KB, RAM: 4 KB I2C bus version Mask ROM: 64 KB, RAM: 4 KB I2C bus version
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CHAPTER 1 INTRODUCTION
Differences Between Products
Function Part No. Timer 8-Bit 16-Bit TMH Watch WDT 2 ch 2 ch 2 ch 1 ch 2 ch CSI 2 ch Serial Interface CSIA UART 1 ch 2 ch IC - 1 ch - 1 ch - 1 ch - 1 ch 2 ch 4 ch 2 ch 1 ch 2 ch 2 ch 2 ch 2 ch - 1 ch - 1 ch - 1 ch - 1 ch 2 ch 6 ch 2 ch 1 ch 2 ch 3 ch 2 ch 3 ch - 2 ch - 2 ch - 2 ch 16 ch 2 ch 12 ch 128 - 8 ch 2 ch 6 ch 84 - 8 ch - 6 ch 67 -
2
A/D
D/A
RTO
I/O
Other
PD703208 PD703208Y
V850ES/KF1 V850ES/KG1 V850ES/KJ1
2
PD703209 PD703209Y PD703210 PD703210Y PD70F3210 PD70F3210Y PD703212 PD703212Y PD703213 PD703213Y PD703214 PD703214Y PD70F3214 PD70F3214Y PD703216 PD703216Y PD703217 PD703217Y PD70F3217 PD70F3217Y
Remark In this manual, the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 product names are used as follows. * Mask ROM versions V850ES/KF1: PD703208, 703208Y, 703209, 703209Y, 703210, 703210Y V850ES/KG1: PD703212, 703212Y, 703213, 703213Y, 703214, 703214Y V850ES/KJ1: PD703216, 703216Y, 703217, 703217Y * Flash memory versions V850ES/KF1: PD70F3210, 70F3210Y V850ES/KG1: PD70F3214, 70F3214Y V850ES/KJ1: PD70F3217, 70F3217Y * I C bus versions V850ES/KF1: PD703208Y, 703209Y, 703210Y, 70F3210Y V850ES/KG1: PD703212Y, 703213Y, 703214Y, 70F3214Y V850ES/KJ1: PD703216Y, 703217Y, 70F3217Y
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1.2 V850ES/KF1
1.2.1 Features (V850ES/KF1) Number of instructions: 83 Minimum instruction execution time: 50 ns (operation at main clock (fXX) = 20 MHz) General-purpose registers: 32 bits x 32 registers Instruction set: Signed multiplication (16 x 16 32): 1 to 2 clocks (Instructions without creating register hazards can be continuously executed in parallel) Saturated operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock Bit manipulation instructions Load/store instructions with long/short format Memory space: 64 MB of linear address space Memory block division function: 2 MB, 64 KB (Total of 2 blocks) External bus interface 16-bit data bus Internal memory
PD703208, 703208Y (Mask ROM: 64 KB/RAM: 4 KB) PD703209, 703209Y (Mask ROM: 96 KB/RAM: 4 KB) PD703210, 703210Y (Mask ROM: 128 KB/RAM: 6 KB) PD70F3210, 70F3210Y (Flash memory: 128 KB/RAM: 6 KB)
Interrupts and exceptions Non-maskable interrupts: 3 sources Maskable interrupts: Software exceptions: Exception trap: I/O lines: Timer/counter 16-bit timer/event counter: 2 channels 8-bit timer/event counter: 2 channels 8-bit timer H: 2 channels Watch timer: 1 channel Watchdog timers Watchdog timer 1 (also usable as oscillation stabilization timer): 1 channel Watchdog timer 2: 1 channel Serial interface (SIO) Asynchronous serial interface (UART): 2 channels 3-wire serial I/O (CSI0): 2 channels 3-wire serial I/O (with automatic transmit/receive function) (CSIA): 1 channel I C bus interface (I C): 1 channel (PD703208Y, 703209Y, 703210Y, 70F3210Y) A/D converter: 10-bit resolution x 8 channels Real-time output port: 6 bits x 1 channel Power-save functions: HALT/IDLE/STOP modes, subclock/sub-IDLE modes
2 2
30 sources (PD703208, 703209, 703210, 70F3210) 31 sources (PD703208Y, 703209Y, 703210Y, 70F3210Y) 32 sources 1 source
Total: 67
Key interrupt function
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CHAPTER 1 INTRODUCTION
ROM correction: 4 correction addresses specifiable Packages: 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 1.2.2 Applications (V850ES/KF1) Audio equipment, etc. 1.2.3 Ordering information (V850ES/KF1) Part Number Package 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic TQFP (fine pitch) (12 x 12)
Note
Quality Grade Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special
PD703208GC-xxx-8BT PD703208YGC-xxx-8BT PD703208GK-xxx-9EU PD703208YGK-xxx-9EU PD703209GC-xxx-8BT PD703209YGC-xxx-8BT PD703209GK-xxx-9EU PD703209YGK-xxx-9EU PD703210GC-xxx-8BT PD703210YGC-xxx-8BT PD703210GK-xxx-9EU PD703210YGK-xxx-9EU PD70F3210GC-8BT PD70F3210YGC-8BT PD70F3210GK-9EU PD70F3210YGK-9EU PD703208GC(A)-xxx-8BT PD703208YGC(A)-xxx-8BTNote PD703208GK(A)-xxx-9EU PD703209GC(A)-xxx-8BT
Note
80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic TQFP (fine pitch) (12 x 12)
PD703208YGK(A)-xxx-9EUNote
Note
PD703209YGC(A)-xxx-8BTNote PD703209GK(A)-xxx-9EU PD703210GC(A)-xxx-8BT
Note
PD703209YGK(A)-xxx-9EUNote
Note
PD703210YGC(A)-xxx-8BTNote PD703210GK(A)-xxx-9EU PD70F3210GC(A)-8BT
Note Note
PD703210YGK(A)-xxx-9EUNote PD70F3210YGC(A)-8BTNote PD70F3210GK(A)-9EU
Note
PD70F3210YGK(A)-9EUNote
Note Under development
Remark xxx indicates ROM code suffix.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
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1.2.4 Pin configuration (top view) (V850ES/KF1) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) PD703208GC-xxx-8BT PD703209GK-xxx-9EU PD703208YGC-xxx-8BT PD703209YGK-xxx-9EU PD703208GK-xxx-9EU PD703210GC-xxx-8BT PD703208YGK-xxx-9EU PD703210YGC-xxx-8BT PD703209GC-xxx-8BT PD703210GK-xxx-9EU PD703209YGC-xxx-8BT PD703210YGK-xxx-9EU PD703208GK(A)-xxx-9EU PD703210GC(A)-xxx-8BT PD703208YGK(A)-xxx-9EU PD703210YGC(A)-xxx-8BT PD703209GC(A)-xxx-8BT PD703210GK(A)-xxx-9EU PD703209YGC(A)-xxx-8BT PD703210YGK(A)-xxx-9EU PD703209GK(A)-xxx-9EU PD70F3210GC(A)-8BT PD703209YGK(A)-xxx-9EU PD70F3210YGC(A)-8BT
PD70F3210GC-8BT PD70F3210YGC-8BT PD70F3210GK-9EU PD70F3210YGK-9EU PD703208GC(A)-xxx-8BT PD703208YGC(A)-xxx-8BT PD70F3210GK(A)-9EU PD70F3210YGK(A)-9EU
PDL15/AD15
PDL14/AD14
PDL13/AD13
PDL12/AD12
PDL11/AD11
PDL10/AD10
PDL9/AD9
PDL8/AD8
PDL7/AD7
PDL6/AD6
PDL5/AD5
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 AVREF0 AVss P00/TOH0 P01/TOH1 P02/NMI P03/INTP0 P04/INTP1 VPPNote 1/ICNote 1 VDD REGC VSS X1 X2 RESET XT1 XT2 P05/INTP2 P06/INTP3 P40/SI00 P41/SO00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 PDL3/AD3 PDL2/AD2 PDL1/AD1 PDL0/AD0 PCT6/ASTB PCT4/RD PCT1/WR1 PCT0/WR0 PCM3/HLDRQ PCM2/HLDAK PCM1/CLKOUT PCM0/WAIT PCS1/CS1 PCS0/CS0 P915/INTP6 P914/INTP5 P913/INTP4 P99/SCK01 P98/SO01 P97/SI01
41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P38/SDA0Note 2
P39/SCL0Note 2
P35/TI010/TO01
EVDD
EVSS
P50/TI011/RTP00/KR0
P51/TI50/RTP01/KR1
P52/TO50/RTP02/KR2
P53/SIA0/RTP03/KR3
P54/SOA0/RTP04/KR4
P55/SCKA0/RTP05/KR5
P90/TXD1/KR6
P33/TI000/TO00
P91/RXD1/KR7
P42/SCK00
P30/TXD0
P31/RXD0
P32/ASCK0
P34/TI001
Notes 1. IC: Connect directly to VSS (PD703208, 703208Y, 703209, 703209Y, 703210, 703210Y). VPP: Connect to VSS in normal operation mode (PD70F3210, 70F3210Y). 2. SCL0 and SDA0 can be used only for the PD703208Y, 703209Y, 703210Y, and 70F3210Y. Caution Make EVDD the same potential as VDD.
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P96/TI51/TO51
PDL4/AD4
P70/ANI0
P71/ANI1
P72/ANI2
P73/ANI3
P74/ANI4
P75/ANI5
P76/ANI6
P77/ANI7
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CHAPTER 1 INTRODUCTION
Pin Identification (V850ES/KF1)
AD0 to AD15: ANI0 to ANI7: ASCK0: ASTB: AVREF0: AVSS: CLKOUT: CS0, CS1: EVDD: EVSS: HLDAK: HLDRQ: IC: INTP0 to INTP6: KR0 to KR7: NMI: P00 to P06: P30 to P35, P38, P39: P40 to P42: P50 to P55: P70 to P77: P90, P91, P96 to P99,: P913 to P915 PCM0 to PCM3: PCS0, PCS1: PCT0, PCT1, PCT4, PCT6: PDL0 to PDL15: Port CT Port DL Port CM Port CS Address/data bus Analog input Asynchronous serial clock Address strobe Analog reference voltage Ground for analog Clock output Chip select Power supply for port Ground for port Hold acknowledge Hold request Internally connected Interrupt request from peripherals Key return Non-maskable interrupt request Port 0 Port 3 Port 4 Port 5 Port 7 Port 9 RD: REGC: RESET: RTP00 to RTP05: RXD0, RXD1: SCK00, SCK01, SCKA0: SCL0: SDA0: SI00, SI01, SIA0: SO00, SO01, SOA0: TI000, TI001, TI010, TI011, TI50, TI51: TO00, TO01, TO50, TO51, TOH0, TOH1: TXD0, TXD1: VDD: VPP: VSS: WAIT: WR0: WR1: X1, X2: XT1, XT2: Timer output Transmit data Power supply Programming power supply Ground Wait Lower byte write strobe Upper byte write strobe Crystal for main clock Crystal for subclock Timer input Serial output Serial input Serial clock Serial clock Serial data Read strobe Regulator control Reset Real-time output port Receive data
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1.2.5 Function block configuration (V850ES/KF1) (1) Internal block diagram
NMI INTP0 to INTP6
ROM INTC
CPU PC
Note 1 16-bit timer/event counter: 2 ch 8-bit timer/event counter: 2 ch
Instruction queue Multiplier 16 x 1632
BCU ALU HLDRQ HLDAK ASTB RD WAIT WR0, WR1 CS0, CS1 AD0 to AD15
TI000, TI001,TI010, TI011 TO00, TO01
RAM
32-bit barrel shifter System registers
General-purpose registers 32 bits x 32
Note 2
TI50, TI51 TO50, TO51
ROM correction
TOH0, TOH1
8-bit timer H: 2 ch SIO
SO00, SO01 SI00, SI01 SCK00, SCK01 SOA0 SIA0 SCKA0 SDA0Note 3 SCL0Note 3 TXD0, TXD1 RXD0, RXD1 ASCK0
Ports
CSI0: 2 ch
PDL0 to PDL15 PCT0, PCT1, PCT4, PCT6 PCS0, PCS1 PCM0 to PCM3 P90, P91, P96 to P99, P913 to P915 P70 to P77 P50 to P55 P40 to P42 P30 to P35, P38, P39 P00 to P06
A/D converter
CG
AVREF0 AVSS ANI0 to ANI7
CLKOUT X1 X2 XT1 XT2 RESET
CSIA: 1 ch
I2CNote 3: 1 ch
Regulator
REGC
VDD ICNote 4 EVDD EVSS VPPNote 5 VSS
UART: 2 ch
Watchdog timer
RTP00 to RTP05
Key interrupt function Watch timer
KR0 to KR7
RTP: 1 ch
Notes 1. PD703208, 703208Y:
64 KB (mask ROM) 96 KB (mask ROM) 128 KB (mask ROM) 4 KB
PD703209, 703209Y: PD703210, 703210Y:
PD70F3210, 70F3210Y: 128 KB (flash memory)
2. PD703208, 703208Y, 703209, 703209Y:
PD703210, 703210Y, 70F3210, 70F3210Y: 6 KB
3. Only for the PD703208Y, 703209Y, 703210Y, and 70F3210Y 4. Only for the PD703208, 703208Y, 703209, 703209Y, 703210, and 703210Y 5. Only for the PD70F3210 and 70F3210Y
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(2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other types of instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits x 16 bits 32 bits) and a barrel shifter (32 bits) help accelerate processing of complex instructions. (b) Bus control unit (BCU) The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an internal instruction queue. (c) ROM This consists of a 128 KB, 96 KB, or 64 KB mask ROM or flash memory mapped to the address spaces from 0000000H to 001FFFFH, 0000000H to 0017FFFH, or 0000000H to 000FFFFH, respectively. ROM can be accessed by the CPU in one clock cycle during instruction fetch. (d) RAM This consists of a 6 KB or 4 KB RAM mapped to the address spaces from 3FFD800H to 3FFEFFFH or 3FFE000H to 3FFEFFFH, respectively. RAM can be accessed by the CPU in one clock cycle during data access. (e) Interrupt controller (INTC) This controller handles hardware interrupt requests (NMI, INTP0 to INTP6) from on-chip peripheral hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed for interrupt sources. (f) Clock generator (CG) The clock generator includes two types of oscillators: one for the main clock (fXX) and one for the subclock (fXT). It generates seven types of clocks (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT), and supplies one of them as the operating clock for the CPU (fCPU). (g) Timer/counter Two 16-bit timer/event counter channels and two 8-bit timer/event counter channels are incorporated, enabling measurement of pulse intervals and frequency as well as programmable pulse output. Two 8-bit timer/event counters can be connected in cascade to configure a 16-bit timer. Two 8-bit timer H channels are provided on chip. (h) Watch timer This timer counts the reference time (0.5 seconds) for counting the clock from the subclock (32.768 kHz) or fBRG (32.768 kHz) from the clock generator. At the same time, the watch timer can be used as an interval timer.
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(i)
Watchdog timer Two watchdog timer channels are provided on chip to detect program loops and system abnormalities. Watchdog timer 1 can be used as an interval timer. When used as a watchdog timer, it generates a nonmaskable interrupt request signal (INTWDT1) or system reset signal (WDTRES1) after an overflow occurs. When used as an interval timer, it generates a maskable interrupt request (INTWDTM1) after an overflow occurs. Watchdog timer 2 operates by default following reset release. It generates a non-maskable interrupt request signal (INTWDT2) or system reset signal (WDTRES2) after an overflow occurs.
(j)
Serial interface (SIO) The V850ES/KF1 includes four kinds of serial interfaces: an asynchronous serial interface (UARTn), a clocked serial interface (CSI0n), a clocked serial interface (with an automatic transmit/receive function) (CSIA0), and an I C bus interface (I C0). The PD703208, 703209, 703210, and 70F3210 can
2 2
simultaneously use up to five channels, and the PD703208Y, 703209Y, 703210Y, and 70F3210Y up to six channels. For UARTn, data is transferred via the TXDn and RXDn pins. For CSI0n, data is transferred via the SO0n, SI0n, and SCK0n pins. For CSIA0, data is transferred via the SOA0, SIA0, and SCKA0 pins. For I C0, data is transferred via the SDA0 and SCL0 pins. I C0 is provided only for the PD703208Y, 703209Y, 703210Y, and 70F3210Y.
2 2
For UART, a dedicated baud rate generator is provided on chip. Remark n = 0, 1 (k) A/D converter This high-speed, high-resolution 10-bit A/D converter includes 8 analog input pins. Conversion is performed using the successive approximation method. (l) ROM correction This function is used to replace part of a program in the mask ROM with that contained in the internal RAM. Up to four correction addresses can be specified. (m) Key interrupt function A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input pins. (n) Real-time output function This function transfers 6-bit data set beforehand to output latches upon occurrence of an external trigger signal or a timer compare register match signal. For the V850ES/KF1, a 1-channel 6-bit data real-time output function is provided on chip.
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(o) Ports As shown below, the following ports have general-purpose port functions and control pin functions.
Port P0 P3 P4 P5 P7 P9 PCM PCS PCT PDL I/O 7-bit I/O 8-bit I/O 3-bit I/O 6-bit I/O 8-bit input 9-bit I/O 4-bit I/O 2-bit I/O 4-bit I/O 16-bit I/O Port Function Control Function
General-purpose port NMI, external interrupt, timer output Serial interface, timer I/O Serial interface Serial interface, timer I/O, key interrupt function, real-time output function A/D converter analog input Serial interface, timer output, external interrupt, key interrupt function External bus interface Chip select output External bus interface External address/data bus
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1.3 V850ES/KG1
1.3.1 Features (V850ES/KG1) Number of instructions: 83 Minimum instruction execution time: 50 ns (operation at main clock (fXX) = 20 MHz) General-purpose registers: 32 bits x 32 registers Instruction set: Signed multiplication (16 x 16 32): 1 to 2 clocks (Instructions without creating register hazards can be continuously executed in parallel) Saturated operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock Bit manipulation instructions Load/store instructions with long/short format Memory space: 64 MB of linear address space Memory block division function: 2 MB, 2 MB (Total of 2 blocks) External bus interface 16-bit data bus Address bus: Separate output possible Internal memory
PD703212, 703212Y (Mask ROM: 64 KB/RAM: 4 KB) PD703213, 703213Y (Mask ROM: 96 KB/RAM: 4 KB) PD703214, 703214Y (Mask ROM: 128 KB/RAM: 6 KB) PD70F3214, 70F3214Y (Flash memory: 128 KB/RAM: 6 KB)
Interrupts and exceptions Non-maskable interrupts: 3 sources Maskable interrupts: Software exceptions: Exception trap: I/O lines: Timer/counter 16-bit timer/event counter: 4 channels 8-bit timer/event counter: 2 channels 8-bit timer H: 2 channels Watch timer: 1 channel Watchdog timers Watchdog timer 1 (also usable as oscillation stabilization timer): 1 channel Watchdog timer 2: 1 channel Serial interface (SIO) Asynchronous serial interface (UART): 2 channels 3-wire serial I/O (CSI0): 2 channels 3-wire serial I/O (with automatic transmit/receive function) (CSIA): 2 channels I C bus interface (I C): 1 channel (PD703212Y, 703213Y, 703214Y, 70F3214Y) A/D converter: 10-bit resolution x 8 channels D/A converter: 8-bit resolution x 2 channels Real-time output port: 6 bits x 1 channel Power-save functions: HALT/IDLE/STOP modes, subclock/sub-IDLE modes
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35 sources (PD703212, 703213, 703214, 70F3214) 36 sources (PD703212Y, 703213Y, 703214Y, 70F3214Y) 32 sources 1 source
Total: 84
Key interrupt function
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ROM correction: 4 correction addresses specifiable Packages: 100-pin plastic LQFP (fine pitch) (14 x 14) 1.3.2 Applications (V850ES/KG1) Audio equipment, etc. 1.3.3 Ordering information (V850ES/KG1) Part Number Package 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14)
Note
Quality Grade Standard Standard Standard Standard Standard Standard Standard Standard Special Special Special Special Special Special Special Special
PD703212GC-xxx-8EU PD703212YGC-xxx-8EU PD703213GC-xxx-8EU PD703213YGC-xxx-8EU PD703214GC-xxx-8EU PD703214YGC-xxx-8EU PD70F3214GC-8EU PD70F3214YGC-8EU PD703212GC(A)-xxx-8EUNote PD703212YGC(A)-xxx-8EU PD703213YGC(A)-xxx-8EU PD703214YGC(A)-xxx-8EU PD70F3214GC(A)-8EUNote PD70F3214YGC(A)-8EU
Note
PD703213GC(A)-xxx-8EUNote
Note
PD703214GC(A)-xxx-8EUNote
Note
Note Under development Remark xxx indicates ROM code suffix.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
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1.3.4 Pin configuration (top view) (V850ES/KG1) 100-pin plastic LQFP (fine pitch) (14 x 14) PD703212GC-xxx-8EU PD703212YGC-xxx-8EU PD703213GC-xxx-8EU PD703213YGC-xxx-8EU PD703212GC(A)-xxx-8EU PD703212YGC(A)-xxx-8EU PD703213GC(A)-xxx-8EU PD703213YGC(A)-xxx-8EU
PD703214GC-xxx-8EU PD703214YGC-xxx-8EU PD70F3214GC-8EU PD70F3214YGC-8EU PD703214GC(A)-xxx-8EU PD703214YGC(A)-xxx-8EU PD70F3214GC(A)-8EU PD70F3214YGC(A)-8EU
AVREF0 AVSS P10/ANO0 P11/ANO1 AVREF1 P00/TOH0 P01/TOH1 VPPNote 1/ICNote 1 VDD REGC VSS X1 X2 RESET XT1 XT2 P02/NMI P03/INTP0 P04/INTP1 P05/INTP2 P06/INTP3 P40/SI00 P41/SO00 P42/SCK00 P30/TXD0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P76/ANI6 P77/ANI7 PDH5/A21 PDH4/A20 PDH3/A19 PDH2/A18 PDH1/A17 PDH0/A16 PDL15/AD15 PDL14/AD14 PDL13/AD13 PDL12/AD12 PDL11/AD11 PDL10/AD10 PDL9/AD9 PDL8/AD8 PDL7/AD7 PDL6/AD6 PDL5/AD5
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
PDL4/AD4 PDL3/AD3 PDL2/AD2 PDL1/AD1 PDL0/AD0 BVDD BVSS PCT6/ASTB PCT4/RD PCT1/WR1 PCT0/WR0 PCM3/HLDRQ PCM2/HLDAK PCM1/CLKOUT PCM0/WAIT PCS1/CS1 PCS0/CS0 P915/A15/INTP6 P914/A14/INTP5 P913/A13/INTP4 P912/A12/SCKA1 P911/A11/SOA1 P910/A10/SIA1 P99/A9/SCK01 P98/A8/SO01
Notes 1. IC: Connect directly to VSS (PD703212, 703212Y, 703213, 703213Y, 703214, 703214Y). VPP: Connect to VSS in normal operation mode (PD70F3214, 70F3214Y). 2. SCL0 and SDA0 can be used only for the PD703212Y, 703213Y, 703214Y, and 70F3214Y. Caution Make EVDD the same potential as VDD. BVDD can be used when VDD = EVDD BVDD.
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P31/RXD0 P32/ASCK0 P33/TI000/TO00 P34/TI001 P35/TI010/TO01 P36 P37 EVSS EVDD P38/SDA0Note 2 P39/SCL0Note 2 P50/TI011/RTP00/KR0 P51/TI50/RTP01/KR1 P52/TO50/RTP02/KR2 P53/SIA0/RTP03/KR3 P54/SOA0/RTP04/KR4 P55/SCKA0/RTP05/KR5 P90/A0/TXD1/KR6 P91/A1/RXD1/KR7 P92/A2/TI020/TO02 P93/A3/TI021 P94/A4/TI030/TO03 P95/A5/TI031 P96/A6/TI51/TO51 P97/A7/SI01
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Pin Identification (V850ES/KG1)
A0 to A21: AD0 to AD15: ANI0 to ANI7: ANO0, ANO1: ASCK0: ASTB: AVREF0, AVREF1: AVSS: BVDD: BVSS: CLKOUT: CS0, CS1: EVDD: EVSS: HLDAK: HLDRQ: IC: INTP0 to INTP6: KR0 to KR7: NMI: P00 to P06: P10, P11: P30 to P39: P40 to P42: P50 to P55: P70 to P77: P90 to P915: PCM0 to PCM3: PCS0, PCS1: PCT0, PCT1, PCT4, PCT6: PDH0 to PDH5: PDL0 to PDL15: Port CT Port DH Port DL Address bus Address/data bus Analog input Analog output Asynchronous serial clock Address strobe Analog reference voltage Ground for analog Power supply for bus interface Ground for bus interface Clock output Chip select Power supply for port Ground for port Hold acknowledge Hold request Internally connected Interrupt request from peripherals Key return Non-maskable interrupt request Port 0 Port 1 Port 3 Port 4 Port 5 Port 7 Port 9 Port CM Port CS RD: REGC: RESET: RTP00 to RTP05: RXD0, RXD1: SCK00, SCK01, SCKA0, SCKA1: SCL0: SDA0: SI00, SI01, SIA0, SIA1: SO00, SO01, SOA0, SOA1: TI000, TI001, TI010, TI011, TI020, TI021, TI030, TI031, TI50, TI51: TO00 to TO03, TO50, TO51, TOH0, TOH1: TXD0, TXD1: VDD: VPP: VSS: WAIT: WR0: WR1: X1, X2: XT1, XT2: Timer output Transmit data Power supply Programming power supply Ground Wait Lower byte write strobe Upper byte write strobe Crystal for main clock Crystal for subclock Timer input Serial output Serial input Serial clock Serial clock Serial data Read strobe Regulator control Reset Real-time output port Receive data
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1.3.5 Function block configuration (V850ES/KG1) (1) Internal block diagram
NMI INTP0 to INTP6 TI000, TI001, TI010, TI011, TI020, TI021, TI030, TI031 TO00 to TO03
ROM INTC
CPU PC
Note 1 16-bit timer/event counter: 4 ch 8-bit timer/event counter: 2 ch
Instruction queue Multiplier 16 x 1632
BCU ALU HLDRQ HLDAK ASTB RD WAIT WR0, WR1 CS0, CS1 A0 to A21 AD0 to AD15
RAM
32-bit barrel shifter System registers
General-purpose registers 32 bits x 32
Note 2
TI50, TI51 TO50, TO51
ROM correction
TOH0, TOH1
8-bit timer H: 2 ch SIO
SO00, SO01 SI00, SI01 SCK00, SCK01 SOA0, SOA1 SIA0, SIA1 SCKA0, SCKA1 SDA0Note 3 SCL0
Note 3
Ports
CSI0: 2 ch
D/A converter
A/D converter
CG
CLKOUT X1 X2 XT1 XT2 RESET
I2CNote 3: 1 ch
ANO0, ANO1 AVREF1
AVREF0 AVSS ANI0 to ANI7
CSIA: 2 ch
PDL0 to PDL15 PDH0 to PDH5 PCT0, PCT1, PCT4, PCT6 PCS0, PCS1 PCM0 to PCM3 P90 to P915 P70 to P77 P50 to P55 P40 to P42 P30 to P39 P10, P11 P00 to P06
Regulator
REGC
VDD ICNote 4 BVDD BVSS EVDD
TXD0, TXD1 RXD0, RXD1 ASCK0
UART: 2 ch
Watchdog timer
RTP00 to RTP05
Key interrupt function Watch timer
KR0 to KR7
EVSS VPPNote 5 VSS
RTP : 1 ch
Notes 1. PD703212, 703212Y:
64 KB (mask ROM) 96 KB (mask ROM) 128 KB (mask ROM) 4 KB
PD703213, 703213Y: PD703214, 703214Y:
PD70F3214, 70F3214Y: 128 KB (flash memory)
2. PD703212, 703212Y, 703213, 703213Y:
PD703214, 703214Y, 70F3214, 70F3214Y: 6 KB
3. Only for the PD703212Y, 703213Y, 703214Y, and 70F3214Y 4. Only for the PD703212, 703212Y, 703213, 703213Y, 703214, and 703214Y 5. Only for the PD70F3214 and 70F3214Y
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(2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other types of instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits x 16 bits 32 bits) and a barrel shifter (32 bits) help accelerate processing of complex instructions. (b) Bus control unit (BCU) The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an internal instruction queue. (c) ROM This consists of a 128 KB, 96 KB, or 64 KB mask ROM or flash memory mapped to the address spaces from 0000000H to 001FFFFH, 0000000H to 0017FFFH, or 0000000H to 000FFFFH, respectively. ROM can be accessed by the CPU in one clock cycle during instruction fetch. (d) RAM This consists of a 6 KB or 4 KB RAM mapped to the address spaces from 3FFD800H to 3FFEFFFH or 3FFE000H to 3FFEFFFH, respectively. RAM can be accessed by the CPU in one clock cycle during data access. (e) Interrupt controller (INTC) This controller handles hardware interrupt requests (NMI, INTP0 to INTP6) from on-chip peripheral hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed for interrupt sources. (f) Clock generator (CG) The clock generator includes two types of oscillators: one for the main clock (fXX) and one for the subclock (fXT). It generates seven types of clocks (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT), and supplies one of them as the operating clock for the CPU (fCPU). (g) Timer/counter Four 16-bit timer/event counter channels and two 8-bit timer/event counter channels are incorporated, enabling measurement of pulse intervals and frequency as well as programmable pulse output. Two 8-bit timer/event counters can be connected in cascade to configure a 16-bit timer. Two 8-bit timer H channels are provided on chip. (h) Watch timer This timer counts the reference time (0.5 seconds) for counting the clock from the subclock (32.768 kHz) or fBRG (32.768 kHz) from the clock generator. At the same time, the watch timer can be used as an interval timer.
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(i)
Watchdog timer Two watchdog timer channels are provided on chip to detect program loops and system abnormalities. Watchdog timer 1 can be used as an interval timer. When used as a watchdog timer, it generates a nonmaskable interrupt request signal (INTWDT1) or system reset (WDTRES1) after an overflow occurs. When used as an interval timer, it generates a maskable interrupt request signal (INTWDTM1) after an overflow occurs. Watchdog timer 2 operates by default following reset release. It generates a non-maskable interrupt request signal (INTWDT2) or system reset signal (WDTRES2) after an overflow occurs.
(j)
Serial interface (SIO) The V850ES/KG1 includes four kinds of serial interfaces: an asynchronous serial interface (UARTn), a clocked serial interface (CSI0n), a clocked serial interface (with an automatic transmit/receive function) (CSIAn), and an I C bus interface (I C0). The PD703212, 703213, 703214, and 70F3214 can
2 2
simultaneously use up to six channels, and the PD703212Y, 703213Y, 703214Y, and 70F3214Y up to seven channels. For UARTn, data is transferred via the TXDn and RXDn pins. For CSI0n, data is transferred via the SO0n, SI0n, and SCK0n pins. For CSIA0, data is transferred via the SOAn, SIAn, and SCKAn pins. For I C0, data is transferred via the SDA0 and SCL0 pins. I C0 is provided only for the PD703212Y, 703213Y, 703214Y, and 70F3214Y.
2 2
For UART, a dedicated baud rate generator is provided on chip. Remark n = 0, 1 (k) A/D converter This high-speed, high-resolution 10-bit A/D converter includes 8 analog input pins. Conversion is performed using the successive approximation method. (l) D/A converter A two 8-bit resolution D/A converter channels are included on chip. It uses the R-2R ladder method. (m) ROM correction This function is used to replace part of a program in the mask ROM with that contained in the internal RAM. Up to four correction addresses can be specified. (n) Key interrupt function A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input pins. (o) Real-time output function This function transfers 6-bit data set beforehand to output latches upon occurrence of an external trigger signal or a timer compare register match signal. For the V850ES/KG1, a 1-channel 6-bit data real-time output function is provided on chip.
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(p) Ports As shown below, the following ports have general-purpose port functions and control pin functions.
Port P0 P1 P3 P4 P5 P7 P9 I/O 7-bit I/O 2-bit I/O 10-bit I/O 3-bit I/O 6-bit I/O 8-bit input 16-bit I/O Port Function Control Function
General-purpose port NMI, external interrupt, timer output D/A converter analog output Serial interface, timer I/O Serial interface Serial interface, timer I/O, key interrupt function, real-time output function A/D converter analog input External address bus, serial interface, timer output, external interrupt, key interrupt function External bus interface Chip select output External bus interface External address bus External address/data bus
PCM PCS PCT PDH PDL
4-bit I/O 2-bit I/O 4-bit I/O 6-bit I/O 16-bit I/O
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1.4 V850ES/KJ1
1.4.1 Features (V850ES/KJ1) Number of instructions: 83 Minimum instruction execution time: 50 ns (operation at main clock (fXX) = 20 MHz) General-purpose registers: 32 bits x 32 registers Instruction set: Signed multiplication (16 x 16 32): 1 to 2 clocks (Instructions without creating register hazards can be continuously executed in parallel) Saturated operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock Bit manipulation instructions Load/store instructions with long/short format Memory space: 64 MB of linear address space Memory block division function: 2 MB, 2 MB, 4 MB, 8 MB (Total of 4 blocks) External bus interface 16-bit data bus Address bus: Separate output possible Internal memory
PD703216, 703216Y (Mask ROM: 96 KB/RAM: 6 KB) PD703217, 703217Y (Mask ROM: 128 KB/RAM: 6 KB) PD70F3217, 70F3217Y (Flash memory: 128 KB/RAM: 6 KB)
Interrupts and exceptions Non-maskable interrupts: 3 sources Maskable interrupts: Software exceptions: Exception trap: I/O lines: Timer/counter 16-bit timer/event counter: 6 channels 8-bit timer/event counter: 2 channels 8-bit timer H: 2 channels Watch timer: 1 channel Watchdog timers Watchdog timer 1 (also usable as oscillation stabilization timer): 1 channel Watchdog timer 2: 1 channel Serial interface (SIO) Asynchronous serial interface (UART): 3 channels 3-wire serial I/O (CSI0): 3 channels 3-wire serial I/O (with automatic transmit/receive function) (CSIA): 2 channels I C bus interface (I C): 2 channels (PD703216Y, 703217Y, 70F3217Y) A/D converter: 10-bit resolution x 16 channels D/A converter: 8-bit resolution x 2 channels Real-time output port: 6 bit x 2 channels Power-save functions: HALT/IDLE/STOP modes, subclock/sub-IDLE modes
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43 sources (PD703216, 703217, 70F3217) 45 sources (PD703216Y, 703217Y, 70F3217Y) 32 sources 1 source
Total: 128
Key interrupt function
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ROM correction: 4 correction addresses specifiable Packages: 144-pin plastic LQFP (fine pitch) (20 x 20) 1.4.2 Applications (V850ES/KJ1) Audio equipment, etc. 1.4.3 Ordering information (V850ES/KJ1) Part Number Package 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20)
Note
Quality Grade Standard Standard Standard Standard Standard Standard Special Special Special Special Special Special
PD703216GJ-xxx-UEN PD703216YGJ-xxx-UEN PD703217GJ-xxx-UEN PD703217YGJ-xxx-UEN PD70F3217GJ-UEN PD70F3217YGJ-UEN PD703216GJ(A)-xxx-UENNote PD703216YGJ(A)-xxx-UEN PD703217YGJ(A)-xxx-UEN PD70F3217GJ(A)-UENNote PD70F3217YGJ(A)-UEN
Note
PD703217GJ(A)-xxx-UENNote
Note
Note Under development Remark xxx indicates ROM code suffix.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
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1.4.4 Pin configuration (top view) (V850ES/KJ1) 144-pin plastic LQFP (fine pitch) (20 x 20)
PD703216GJ-xxx-UEN PD703216YGJ-xxx-UEN PD703217GJ-xxx-UEN PD703217YGJ-xxx-UEN
PD70F3217GJ-UEN PD70F3217YGJ-UEN PD703216GJ(A)-xxx-UEN PD703216YGJ(A)-xxx-UEN
PD703217GJ(A)-xxx-UEN PD703217YGJ(A)-xxx-UEN PD70F3217GJ(A)-UEN PD70F3217YGJ(A)-UEN
AVREF0 AVSS P10/ANO0 P11/ANO1 AVREF1 P00/TOH0 P01/TOH1 VPPNote 1/ICNote 1 VDD REGC VSS X1 X2 RESET XT1 XT2 P02/NMI P03/INTP0 P04/INTP1 P05/INTP2 P06/INTP3 P40/SI00 P41/SO00 P42/SCK00 P30/TXD0 P31/RXD0 P32/ASCK0 P33/TI000/TO00 P34/TI001 P35/TI010/TO01 P36 P37 EVSS EVDD P38/SDA0Note 2 P39/SCL0Note 2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P76/ANI6 P77/ANI7 P78/ANI8 P79/ANI9 P710/ANI10 P711/ANI11 P712/ANI12 P713/ANI13 P714/ANI14 P715/ANI15 PDH7/A23 PDH6/A22 PDH5/A21 PDH4/A20 PDH3/A19 PDH2/A18 PDH1/A17 PDH0/A16 PDL15/AD15 PDL14/AD14 PDL13/AD13 PDL12/AD12 PDL11/AD11 PDL10/AD10 PDL9/AD9 PDL8/AD8 PDL7/AD7 PDL6/AD6 PDL5/AD5 PDL4/AD4
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PDL3/AD3 PDL2/AD2 PDL1/AD1 PDL0/AD0 BVDD BVSS PCT7 PCT6/ASTB PCT5 PCT4/RD PCT3 PCT2 PCT1/WR1 PCT0/WR0 PCS7 PCS6 PCS5 PCS4 PCM5 PCM4 PCM3/HLDRQ PCM2/HLDAK PCM1/CLKOUT PCM0/WAIT PCS3/CS3 PCS2/CS2 PCS1/CS1 PCS0/CS0 PCD3 PCD2 PCD1 PCD0 P915/A15/INTP6 P914/A14/INTP5 P913/A13/INTP4 P912/A12/SCKA1
Notes 1. IC: Connect directly to VSS (PD703216, 703216Y, 703217, 703217Y). VPP: Connect to VSS in normal operation mode (PD70F3217, 70F3217Y). 2. SCL0, SDA0, SCL1, and SDA1 can be used only for the PD703216Y, 703217Y, and 70F3217Y. Caution Make EVDD the same potential as VDD. BVDD can be used when VDD = EVDD BVDD.
P50/TI011/RTP00/KR0 P51/TI50/RTP01/KR1 P52/TO50/RTP02/KR2 P53/SIA0/RTP03/KR3 P54/SOA0/RTP04/KR4 P55/SCKA0/RTP05/KR5 P60/RTP10 P61/RTP11 P62/RTP12 P63/RTP13 P64/RTP14 P65/RTP15 P66/SI02 P67/SO02 P68/SCK02 P69/TI040 P610/TI041 P611/TO04 P612/TI050 P613/TI051/TO05 P614 P615 P80/RXD2/SDA1Note 2 P81/TXD2/SCL1Note 2 P90/A0/TXD1/KR6 P91/A1/RXD1/KR7 P92/A2/TI020/TO02 P93/A3/TI021 P94/A4/TI030/TO03 P95/A5/TI031 P96/A6/TI51/TO51 P97/A7/SI01 P98/A8/SO01 P99/A9/SCK01 P910/A10/SIA1 P911/A11/SOA1
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CHAPTER 1 INTRODUCTION
Pin Identification (V850ES/KJ1)
A0 to A23: AD0 to AD15: ANI0 to ANI15: ANO0, ANO1: ASCK0: ASTB: AVREF0, AVREF1: AVSS: BVDD: BVSS: CLKOUT: CS0 to CS3: EVDD: EVSS: HLDAK: HLDRQ: IC: INTP0 to INTP6: KR0 to KR7: NMI: P00 to P06: P10, P11: P30 to P39: P40 to P42: P50 to P55: P60 to P615: P70 to P715: P80, P81: P90 to P915: PCD0 to PCD3: PCM0 to PCM5: PCS0 to PCS7: PCT0 to PCT7: PDH0 to PDH7: Address bus Address/data bus Analog input Analog output Asynchronous serial clock Address strobe Analog reference voltage Ground for analog Power supply for bus interface Ground for bus interface Clock output Chip select Power supply for port Ground for port Hold acknowledge Hold request Internally connected Interrupt request from peripherals Key return Non-maskable interrupt request Port 0 Port 1 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port CD Port CM Port CS Port CT Port DH PDL0 to PDL15: RD: REGC: RESET: RTP00 to RTP05, RTP10 to RTP15: RXD0 to RXD2: SCK00 to SCK02, SCKA0, SCKA1: SCL0, SCL1: SDA0, SDA1: SI00 to SI02, SIA0, SIA1: SO00 to SO02, SOA0, SOA1: TI000, TI001, TI010, TI011, TI020, TI021, TI030, TI031, TI040, TI041, TI050, TI051, TI50, TI51: TO00 to TO05, TO50, TO51, TOH0, TOH1: TXD0 to TXD2: VDD: VPP: VSS: WAIT: WR0: WR1: X1, X2: XT1, XT2: Timer output Transmit data Power supply Programming power supply Ground Wait Lower byte write strobe Upper byte write strobe Crystal for main clock Crystal for subclock Timer input Serial output Serial input Serial clock Serial clock Serial data Real-time output port Receive data Port DL Read strobe Regulator control Reset
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1.4.5 Function block configuration (V850ES/KJ1) (1) Internal block diagram
NMI INTP0 to INTP6 TI000, TI001, TI010, TI011, TI020, TI021, TI030, TI031, TI040, TI041, TI050, TI051 TO00 to TO05
ROM INTC
CPU PC
Note 1 16-bit timer/event counter: 6 ch 8-bit timer/event counter: 2 ch
Instruction queue Multiplier 16 x 1632
BCU ALU HLDRQ HLDAK ASTB RD WAIT WR0, WR1 CS0 to CS3 A0 to A23 AD0 to AD15
RAM
32-bit barrel shifter System registers
General-purpose registers 32 bits x 32
6 KB
TI50, TI51 TO50, TO51
ROM correction
TOH0, TOH1
8-bit timer H: 2 ch SIO
SO00 to SO02 SI00 to SI02 SCK00 to SCK02 SOA0, SOA1 SIA0, SIA1 SCKA0, SCKA1 SDA0, SDA1Note 2 SCL0, SCL1Note 2 TXD0 to TXD2 RXD0 to RXD2 ASCK0
Ports
CSI0: 3 ch
PDL0 to PDL15 PDH0 to PDH7 PCT0 to PCT7 PCS0 to PCS7 PCM0 to PCM5 PCD0 to PCD3 P90 to P915 P80,P81 P70 to P715 P60 to P615 P50 to P55 P40 to P42 P30 to P39 P10,P11 P00 to P06
D/A converter
A/D converter
CG
CLKOUT X1 X2 XT1 XT2 RESET
I2CNote 3: 2 ch
ANO0, ANO1 AVREF1
AVREF0 AVSS ANI0 to ANI15
CSIA: 2 ch
Regulator
REGC
VDD ICNote 3 BVDD BVSS EVDD
UART: 3 ch
Watchdog timer
RTP00 to RTP05, RTP10 to RTP15
Key interrupt function Watch timer
KR0 to KR7
EVSS VPPNote 4 VSS
RTP: 2 ch
Notes 1. PD703216, 703216Y:
96 KB (mask ROM) 128 KB (mask ROM)
PD703217, 703217Y:
PD70F3217, 70F3217Y: 128 KB (flash memory)
2. Only for the PD703216Y, 703217Y, 70F3217Y 3. Only for the PD703216, 703216Y, 703217, and 703217Y 4. Only for the PD70F3217 and 70F3217Y
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CHAPTER 1 INTRODUCTION
(2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other types of instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits x 16 bits 32 bits) and a barrel shifter (32 bits) help accelerate processing of complex instructions. (b) Bus control unit (BCU) The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an internal instruction queue. (c) ROM This consists of a 128 KB or 96 KB mask ROM or flash memory mapped to the address spaces from 0000000H to 001FFFFH or 0000000H to 0017FFFH, respectively. ROM can be accessed by the CPU in one clock cycle during instruction fetch. (d) RAM This consists of a 6 KB RAM mapped to the address spaces from 3FFD800H to 3FFEFFFH. RAM can be accessed by the CPU in one clock cycle during data access. (e) Interrupt controller (INTC) This controller handles hardware interrupt requests (NMI, INTP0 to INTP6) from on-chip peripheral hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed for interrupt sources. (f) Clock generator (CG) The clock generator includes two types of oscillators: one for the main clock (fXX) and one for the subclock (fXT). It generates seven types of clocks (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT), and supplies one of them as the operating clock for the CPU (fCPU). (g) Timer/counter Six 16-bit timer/event counter channels and two 8-bit timer/event counter channels are incorporated, enabling measurement of pulse intervals and frequency as well as programmable pulse output. Two 8-bit timer/event counters can be connected in cascade to configure a 16-bit timer. Two 8-bit timer H channels are provided on chip. (h) Watch timer This timer counts the reference time (0.5 seconds) for counting the clock from the subclock (32.768 kHz) or fBRG (32.768 kHz) from the clock generator. At the same time, the watch timer can be used as an interval timer.
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(i)
Watchdog timer Two watchdog timer channels are provided on chip to detect program loops and system abnormalities. Watchdog timer 1 can be used as an interval timer. When used as a watchdog timer, it generates a nonmaskable interrupt request signal (INTWDT1) or system reset signal (WDTRES1) after an overflow occurs. When used as an interval timer, it generates a maskable interrupt request signal (INTWDTM1) after an overflow occurs. Watchdog timer 2 operates by default following reset release. It generates a non-maskable interrupt request signal (INTWDT2) or system reset signal (WDTRES2) after an overflow occurs.
(j)
Serial interface (SIO) The V850ES/KJ1 includes four kinds of serial interfaces: an asynchronous serial interface (UARTn), a clocked serial interface (CSI0n), a clocked serial interface (with an automatic transmit/receive function) (CSIAm), and an I C bus interface (I Cm). The PD703216, 703217, and 70F3217 can simultaneously
2 2
use up to eight channels, and the PD703216Y, 703217Y, and 70F3217Y up to nine channels. For UARTn, data is transferred via the TXDn and RXDn pins. For CSI0n, data is transferred via the SO0n, SI0n, and SCK0n pins. For CSIAm, data is transferred via the SOAm, SIAm, and SCKAm pins. For I Cm, data is transferred via the SDAm and SCLm pins. I Cm is provided only for the PD703216Y, 703217Y, and 70F3217Y.
2 2
For UART, a dedicated baud rate generator is provided on chip. Remark n = 0 to 2 m = 0, 1 (k) A/D converter This high-speed, high-resolution 10-bit A/D converter includes 16 analog input pins. Conversion is performed using the successive approximation method. (l) D/A converter Two 8-bit resolution D/A converter channels are included on chip. It uses the R-2R ladder method. (m) ROM correction This function is used to replace part of a program in the mask ROM with that contained in the internal RAM. Up to four correction addresses can be specified. (n) Key interrupt function A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input pins. (o) Real-time output function This function transfers 6-bit data set beforehand to output latches upon occurrence of an external trigger signal or a timer compare register match signal. For the V850ES/KJ1, a 2-channel 6-bit data real-time output function is provided on chip.
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(p) Ports As shown below, the following ports have general-purpose port functions and control pin functions.
Port P0 P1 P3 P4 P5 P6 P7 P8 P9 PCD PCM PCS PCT PDH PDL I/O 7-bit I/O 2-bit I/O 10-bit I/O 3-bit I/O 6-bit I/O 16-bit I/O 16-bit input 2-bit I/O 16-bit I/O 4-bit I/O 6-bit I/O 8-bit I/O 8-bit I/O 8-bit I/O 16-bit I/O External bus interface Chip select output External bus interface External address bus External address/data bus Port Function Control Function
General-purpose port NMI, external interrupt, timer output D/A converter analog output Serial interface, timer I/O Serial interface Serial interface, timer I/O, key interrupt function, real-time output function Serial interface, timer I/O, real-time output function A/D converter analog input Serial interface External address bus, serial interface, timer output, external interrupt, key interrupt function -
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The names and functions of the pins of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 are described below, divided into port pins and non-port pins. The pin I/O buffer power supplies are divided into three systems; AVREF0/AVREF1, BVDD, and EVDD. The relationship between these power supplies and the pins is shown below. Table 2-1. Pin I/O Buffer Power Supplies
Power Supply AVREF0 AVREF1 BVDD EVDD Port 7 Port 1 Port CD, port CM, port CS, port CT, port DH, port DL Port 0, port 3, port 4, port 5, port 6, port 8, port 9, RESET Corresponding Pin
2.1 List of Pin Functions
(1) Port pins (1/4)
Pin Name P00 P01 P02 P03 P04 P05 P06 P10 P11 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 SDA0 SCL0
Note 2
I/O I/O
Pull-up Resistor Yes Port 0
Function
Alternate Function TOH0 TOH1 NMI INTP0 INTP1 INTP2 INTP3
Products All products
I/O port Input/output can be specified in 1-bit units.
I/O
Yes
Port 1 I/O port Input/output can be specified in 1-bit units.
ANO0 ANO1 TXD0 RXD0 ASCK0 TI000/TO00 TI001 TI010/TO01
KG1, KJ1
I/O
Yes
Port 3 I/O port Input/output can be specified in 1-bit units.
All products
No
Note 1
- -
KG1, KJ1
All products
Note 2
Notes 1. An on-chip pull-up resistor can be provided by a mask option (only for the mask ROM versions). 2. Only for products with an I C bus Remark KG1: V850ES/KG1, KJ1: V850ES/KJ1
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55
CHAPTER 2 PIN FUNCTIONS
(2/4)
Pin Name P40 P41 P42 P50 P51 P52 P53 P54 P55 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P610 P611 P612 P613 P614 P615 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P710 P711 P712 Input No Port 7 Input port ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANI12 KJ1 No
Note
I/O I/O
Pull-up Resistor Yes Port 4
Function
Alternate Function SI00 SO00 SCK00 TI011/RTP00/KR0 TI50/RTP01/KR1 TO50/RTP02/KR2 SIA0/RTP03/KR3 SOA0/RTP04/KR4 SCKA0/RTP05/KR5
Products All products
I/O port Input/output can be specified in 1-bit units. I/O Yes Port 5 I/O port Input/output can be specified in 1-bit units.
All products
I/O
Yes
Port 6 I/O port Input/output can be specified in 1-bit units.
RTP10 RTP11 RTP12 RTP13 RTP14 RTP15 SI02 SO02 SCK02 TI040 TI041 TO04 TI050 TI051/TO05 - -
KJ1
All products
Note An internal pull-up resistor can be provided by a mask option (only for the mask ROM versions). Remark KJ1: V850ES/KJ1
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(3/4)
Pin Name P713 P714 P715 P80 P81 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P910 P911 P912 P913 P914 P915 PCD0 PCD1 PCD2 PCD3 PCM0 PCM1 PCM2 PCM3 PCM4 PCM5 PCS0 PCS1 PCS2 PCS3 PCS4 PCS5 PCS6 PCS7 I/O No Port CS I/O port Input/output can be specified in 1-bit units. CS0 CS1 CS2 CS3 - - - - KJ1 I/O No Port CM I/O port Input/output can be specified in 1-bit units. WAIT CLKOUT HLDAK HLDQR - - All products KJ1 I/O No Port CD I/O port Input/output can be specified in 1-bit units. I/O Yes I/O Yes Port 8 I/O port Input/output can be specified in 1-bit units. Port 9 I/O port Input/output can be specified in 1-bit units. I/O Input Pull-up Resistor No Port 7 Input port Function Alternate Function ANI13 ANI14 ANI15 RXD2/SDA1 TXD2/SCL1
Note
Products KJ1
KJ1
Note
A0/TXD1/KR6 A1/RXD1/KR7 A2/TI020/TO02 A3/TI021 A4/TI030/TO03 A5/TI031 A6/TI51/TO51 A7/SI01 A8/SO01 A9/SCK01 A10/SIA1 A11/SOA1 A12/SCKA1 A13/INTP4 A14/INTP5 A15/INTP6 - - - -
All products
KG1, KJ1
All products
KG1, KJ1
All products
KJ1
All products
Note Only for the PD703216Y, 703217Y, and 70F3217Y Remarks 1. KG1: V850ES/KG1, KJ1: V850ES/KJ1 2. The A0 to A15 pins are not provided in the V850ES/KF1.
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CHAPTER 2 PIN FUNCTIONS
(4/4)
Pin Name PCT0 PCT1 PCT2 PCT3 PCT4 PCT5 PCT6 PCT7 PDH0 PDH1 PDH2 PDH3 PDH4 PDH5 PDH6 PDH7 PDL0 PDL1 PDL2 PDL3 PDL4 PDL5 PDL6 PDL7 PDL8 PDL9 PDL10 PDL11 PDL12 PDL13 PDL14 PDL15 I/O No Port DL I/O port Input/output can be specified in 1-bit units. I/O No Port DH I/O port Input/output can be specified in 1-bit units. A16 A17 A18 A19 A20 A21 A22 A23 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 All products KJ1 ASTB - RD - I/O I/O Pull-up Resistor No Function Port CT I/O port Input/output can be specified in 1-bit units. Alternate Function WR0 WR1 - - All products KJ1 All products KJ1 KG1, KJ1 KJ1 Products All products
Remark KG1: V850ES/KG1, KJ1: V850ES/KJ1
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(2) Non-port pins (1/5)
Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 I/O No Address/data bus for external memory Output No Address bus for external memory I/O Output Pull-up Resistor Yes Function Address bus for external memory (when using a separate bus) Alternate Function P90/TDX1/KR6 P91/RXD1/KR7 P92/TI020/TO2 P93/TI021 P94/TI030/TO3 P95/TI031 P96/TI51/TO51 P97/SI01 P98/SO01 P99/SCK01 P910/SIA1 P911/SOA1 P912/SCKA1 P913/INTP4 P914/INTP5 P915/INTP6 PDH0 PDH1 PDH2 PDH3 PDH4 PDH5 PDH6 PDH7 PDL0 PDL1 PDL2 PDL3 PDL4 PDL5 PDL6 PDL7 PDL8 PDL9 PDL10 PDL11 PDL12 PDL13 PDL14 PDL15 All products KJ1 KG1, KJ1 Products KG1, KJ1
Remark KG1: V850ES/KG1, KJ1: V850ES/KJ1
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(2/5)
Pin Name ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANI12 ANI13 ANI14 ANI15 ANO0 ANO1 ASCK0 ASTB AVREF0 AVREF1 AVSS BVDD BVSS CLKOUT CS0 CS1 CS2 CS3 EVDD EVSS HLDAK HLDRQ IC
Note
I/O Input
Pull-up Resistor No
Function Analog voltage input for A/D converter
Alternate Function P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P710 P711 P712 P713 P714 P715
Products All products
KJ1
Output
Yes
Analog voltage output for D/A converter
P10 P11
KG1, KJ1
Input Output - - - - - Output Output
Yes No - - - - - No No
UART0 serial clock input Address strobe signal output for exter nal m e m ory Reference voltage for A/D converter Reference voltage for D/A converter Gr ound potential for A/ D and D/A co nv erters Positive power supply for bus interface and alternate-function ports Ground potential for bus interface and alternate-function ports Internal system clock output Chip select output
P32 PCT6 - - - - - PCM1 PCS0 PCS1 PCS2 PCS3
All products All products All products KG1, KJ1 All products KG1, KJ1 KG1, KJ1 All products All products
KJ1
- - Output Input - Input Yes No No
- -
Positive power supply for external Ground potential for external Bus hold acknowledge output Bus hold request input PCM2 PCM3
- -
All products All products All products All products
-
Internally connected External interrupt request input (maskable, analog noise elimination) P03 P04 P05 P06
-
All products All products
INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6
P913/A13 P914/A14 P915/A15
Note Only for the mask ROM versions Remark KG1: V850ES/KG1, KJ1: V850ES/KJ1
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Pin Name KR0 KR1 KR2 KR3 KR4 KR5 KR6 KR7 NMI Input Yes External interrupt input (non-maskable, analog noise elimination) Read strobe signal output for external memory - - Yes Connecting capacitor for regulator output stabilization System reset input Real-time output port I/O Input Pull-up Resistor Yes Key return input Function Alternate Function P50/TI011/RTP00 P51/TI50/RTP01 P52/TO50/RTP02 P53/SIA0/RTP03 P54/SOA0/RTP04 P55/SCKA0/RTP05 P90/A0/TXD1 P91/A1/RXD1 P02 All products Products All products
RD REGC RESET RTP00 RTP01 RTP02 RTP03 RTP04 RTP05 RTP10 RTP11 RTP12 RTP13 RTP14 RTP15 RXD0 RXD1 RXD2 SCK00 SCK01 SCK02 SCKA0 SCKA1 SCL0 SCL1
Note 1
Output - Input Output
No
PCT4 - - P50/TI011/KR0 P51/TI50/KR1 P52/TO50/KR2 P53/SIA0/KR3 P54/SOA0/KR4 P55/SCKA0/KR5 P60 P61 P62 P63 P64 P65
All products All products All products All products
KJ1
Input
Yes
Serial receive data input for UART0 Serial receive data input for UART1 Serial receive data input for UART2
P31 P91/A1/KR7 P80/SDA1Note 1 P42 P99/A9 P68 P55/RTP05/KR5 P912/A12 P39 P81/TXD2
All products
KJ1 All products
I/O
Yes
Serial clock I/O for CSI00 Serial clock I/O for CSI01 Serial clock I/O for CSI02 Serial clock I/O for CSIA0 Serial clock I/O for CSIA1
KJ1 All products KG1, KJ1 All products KJ1 All products KJ1
I/O
No
Note 2
Serial clock I/O for I C0, I C1
2
2
Note 3
Yes I/O No
Note 2
SDA0 SDA1
Note 1
Serial transmit/receive data I/O for I C0, I C1
2
2
P38 P80/RXD2
Note 3
Yes
2
Notes 1. Only for products with an I C bus 2. An on-chip pull-up resistor can be provided by a mask option (only for the mask ROM and I C bus versions). 3. Only for the PD703216Y, 703217Y, and 70F3217Y Remark KG1: V850ES/KG1, KJ1: V850ES/KJ1
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CHAPTER 2 PIN FUNCTIONS
(4/5)
Pin Name SI00 SI01 SI02 SIA0 SIA1 SO00 SO01 SO02 SOA0 SOA1 TI000 TI001 TI010 TI011 TI020 TI021 TI030 TI031 TI040 TI041 TI050 TI051 TI50 TI51 TO00 TO01 TO02 TO03 TO04 TO05 TO50 TO51 TOH0 TOH1 TXD0 TXD1 TXD2 VDD VPP VSS - - - - - - Output Yes Output Yes Input Yes Output Yes I/O Input Pull-up Resistor Yes Function Serial receive data input for CSI00 Serial receive data input for CSI01 Serial receive data input for CSI02 Serial receive data input for CSIA0 Serial receive data input for CSIA1 Serial transmit data output for CSI00 Serial transmit data output for CSI01 Serial transmit data output for CSI02 Serial transmit data output for CSIA0 Serial transmit data output for CSIA1 External event/clock input for TM00 External event/clock input for TM00 External event/clock input for TM01 External event/clock input for TM01 External event/clock input for TM02 External event/clock input for TM02 External event/clock input for TM03 External event/clock input for TM03 External event/clock input for TM04 External event/clock input for TM04 External event/clock input for TM05 External event/clock input for TM05 External event/clock input for TM50 External event/clock input for TM51 Timer output for TM00 Timer output for TM01 Timer output for TM02 Timer output for TM03 Timer output for TM04 Timer output for TM05 Timer output for TM50 Timer output for TM51 Timer output for TMH0 Timer output for TMH1 Serial transmit data output for UART0 Serial transmit data output for UART1 Serial transmit data output for UART2 Positive power supply pin for internal High-voltage application pin for program write/verify Ground potential for internal Alternate Function P40 P97/A7 P66 P53/RTP03/KR3 P910/A10 P41 P98/A8 P67 P54/RTP04/KR4 P911/A11 P33/TO00 P34 P35/TO01 P50/RTP00/KR0 P92/A2/TO02 P93/A3 P94/A4/TO03 P95/A5 P69 P610 P612 P613/TO05 P51/RTP01/KR1 P96/A6/TO51 P33/TI000 P35/TI010 P92/A2/TI020 P94/A4/TI030 P611 P613/TI051 P52/RTP02/KR2 P96/A6/TI51 P00 P01 P30 P90/A0/KR6 P81/SCL1Note 1 - - - KJ1 All products All productsNote 2 All products All products All products KJ1 KG1, KJ1 All products All products KJ1 KG1, KJ1 KJ1 All products KG1, KJ1 All products KJ1 All products KG1, KJ1 All products Products All products
Notes 1. Only for the PD703216Y, 703217Y, and 70F3217Y 2. Only for products with flash memory Remark KG1: V850ES/KG1, KJ1: V850ES/KJ1
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Pin Name WAIT WR0 WR1 X1 X2 XT1 XT2 Input - Input - No No No No Connecting resonator for subclock I/O Input Output Pull-up Resistor No No External wait input Write strobe for external memory (lower 8 bits) Write strobe for external memory (higher 8 bits) Connecting resonator for main clock Function Alternate Function PCM0 PCT0 PCT1 - - - - Products All products All products All products All products All products All products All products
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2.2 Pin Status
The address bus becomes undefined during accesses to the internal RAM and ROM. The data bus goes into the high-impedance state without data output. The external bus control signal becomes inactive. During peripheral I/O access, the address bus outputs the addresses of the on-chip peripheral I/Os that are accessed. The data bus goes into the high-impedance state without data output. The external bus control signal becomes inactive. Table 2-2. Pin Operation Status in Operation Modes of V850ES/KF1
Operating Status Pin AD0 to AD15 (PDL0 to PDL15) WAIT (PCM0) CLKOUT (PCM1) CS0, CS1 (PCS0, PCS1) WR0, WR1 (PCT0, PCT1) RD (PCT4) ASTB (PCT6) HLDAK (PCM2) HLDRQ (PCM3) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Operating Operating Operating Operating Operating Operating Operating Operating Operating ResetNote 1 HALT Mode IDLE Mode/ STOP Mode Hi-Z - L H H H H H - Idle StateNote 2 Bus Hold
Held - Operating Held H H H H -
Hi-Z - Operating Hi-Z Hi-Z Hi-Z Hi-Z L Operating
Notes 1. Since the bus control pin is also used as a port pin, it is initialized to the port mode (input) after reset. 2. The pin statuses in the idle state inserted after the T3 state are listed. Remark Hi-Z: High impedance H: L: -: High-level output Low-level output Input without sampling (input acknowledgement not possible)
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Table 2-3. Pin Operation Status in Operation Modes of V850ES/KG1
Operating Status Pin AD0 to AD15 (PDL0 to PDL15) A0 to A15 (P90 to P915) A16 to A21 (PDH0 to PDH5) WAIT (PCM0) CLKOUT (PCM1) CS0, CS1 (PCS0, PCS1) WR0, WR1 (PCT0, PCT1) RD (PCT4) ASTB (PCT6) HLDAK (PCM2) HLDRQ (PCM3) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating ResetNote 1 HALT Mode IDLE Mode/ STOP Mode Hi-Z Hi-Z Hi-Z - L H H H H H - Idle StateNote 2 Bus Hold
Held Held Held - Operating Held H H H H -
Hi-Z Hi-Z Hi-Z - Operating Hi-Z Hi-Z Hi-Z Hi-Z L Operating
Notes 1. Since the bus control pin is also used as a port pin, it is initialized to the port mode (input) after reset. 2. The pin statuses in the idle state inserted after the T3 state in the multiplex mode and after the T2 state in the separate mode are listed. Remark Hi-Z: High impedance H: L: -: High-level output Low-level output Input without sampling (input acknowledgement not possible) Table 2-4. Pin Operation Status in Operation Modes of V850ES/KJ1
Operating Status Pin AD0 to AD15 (PDL0 to PDL15) A0 to A15 (P90 to P915) A16 to A23 (PDH0 to PDH7) WAIT (PCM0) CLKOUT (PCM1) CS0 to CS3 (PCS0 to PCS3) WR0, WR1 (PCT0, PCT1) RD (PCT4) ASTB (PCT6) HLDAK (PCM2) HLDRQ (PCM3) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating ResetNote 1 HALT Mode IDLE Mode/ STOP Mode Hi-Z Hi-Z Hi-Z - L H H H H H - Idle StateNote 2 Bus Hold
Held Held Held - Operating Held H H H H -
Hi-Z Hi-Z Hi-Z - Operating Hi-Z Hi-Z Hi-Z Hi-Z L Operating
Notes 1. Since the bus control pin is also used as a port pin, it is initialized to the port mode (input) after reset. 2. The pin statuses in the idle state inserted after the T3 state in the multiplex mode and after the T2 state in the separate mode are listed. Remark Hi-Z: High impedance H: L: -: High-level output Low-level output Input without sampling (input acknowledgement not possible)
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2.3 Description of Pin Functions
2.3.1 V850ES/KF1 (1) P00 to P06 (Port 0) ... I/O Port 0 is a 7-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P00 to P06 can also be used for NMI input, external interrupt request input, and timer H output in the control mode. The port mode and control mode (alternate functions) can be selected as the operation mode for each bit, and are specified by the port 0 mode control register (PMC0). (a) Port mode P00 to P06 can be set to input or output in 1-bit units by the port 0 mode register (PM0). (b) Control mode (alternate function) P00 to P06 can be set to the port mode or control mode in 1-bit units by the port 0 mode control register (PMC0). (i) NMI (non-maskable interrupt request) ... Input This is a non-maskable interrupt request input pin. (ii) INTP0 to INTP3 (interrupt request from peripherals) ... Input These are external interrupt request input pins. (iii) TOH0, TOH1 (timer output) ... Output These are timer H pulse signal output pins. (2) P30 to P35, P38, P39 (Port 3) ... I/O Port 3 is an 8-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P30 to P35, P38, and P39 can also be used for serial interface (UART0, I C0) I/O and 16-bit timer input in control mode 1, and for 16-bit timer output in control mode 2. The port mode and control mode can be selected as the operation mode for each bit, and are specified by the port 3 mode control register (PMC3). P33 and P35 can be set to control mode 1 and control mode 2 in 1-bit units by the port 3 function control register (PFC3). When used as outputs, P38 and P39 are fixed to N-ch open-drain output. (a) Port mode P30 to P35, P38, and P39 can be set to input or output in 1-bit units by the port 3 mode register (PM3). (b) Control mode P30 to P35, P38, and P39 can be set to the port mode or control mode in 1-bit units by the port 3 mode control register (PMC3). P33 and P35 can be set to control mode 1 and control mode 2 in 1-bit units by the port 3 function control register (PFC3). (i) TXD0 (transmit data) ... Output This is the serial transmit data output pin for UART0.
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(ii)
RXD0 (receive data) ... Input This is the serial receive data input pin for UART0.
(iii) ASCK0 (asynchronous serial clock) ... Input This is the serial baud rate clock input pin for UART0. (iv) TI000, TI001, TI010 (timer input) ... Input These are the external count clock input pins for the 16-bit timer. (v) TO00, TO01 (timer output) ... Output These are the pulse signal output pins for the 16-bit timer. (vi) SDA0 (serial data) ... I/O This is the serial transmit/receive data I/O pin for I C0 (only for the PD703208Y, 703209Y, 703210Y,
2
and 70F3210Y). (vii) SCL0 (serial clock) ... I/O This is the serial clock I/O pin for I C0 (only for the PD703208Y, 703209Y, 703210Y, and
2
70F3210Y). (3) P40 to P42 (port 4) ... I/O Port 4 is a 3-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P40 to P42 can also be used for serial interface (CSI00) I/O in the control mode. The port mode and control mode can be selected as the operation mode for each bit, and are specified by the port 4 mode control register (PMC4). Normal output and N-ch open-drain output can be selected for P41 and P42. (a) Port mode P40 to P42 can be set to input or output in 1-bit units by the port 4 mode register (PM4). (b) Control mode P40 to P42 can be set to the port mode or control mode in 1-bit units by the PMC4 register. (i) SO00 (serial output) ... Output This is the serial transmit data output pin for CSI00. (ii) SI00 (serial input) ... Input This is the serial receive data input pin for CSI00. (iii) SCK00 (serial clock) ... I/O This is the serial clock I/O pin for CSI00.
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(4) P50 to P55 (port 5) ... I/O Port 5 is a 6-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P50 to P55 can also be used as 16-bit timer input, 8-bit timer I/O, and serial interface (CSIA0) I/O pins in control mode 1, and as real-time output port pins in control mode 2. They can also be used as key interrupt inputs by setting key return mode register KRM while in the input port mode. The port mode and control mode (alternate functions) can be selected as the operation mode in 1-bit units, and are specified by the port 5 mode control register (PMC5). P50 to P55 can be set to control mode 1 or control mode 2 in 1-bit units by the port 5 function control register (PFC5). Normal output and N-ch open-drain output can be selected for P54 and P55. (a) Port mode P50 to P55 can be set to input or output in 1-bit units by the port 5 mode register (PM5). (b) Control mode (alternate function) P50 to P55 can be set to the port mode or control mode in 1-bit units by the port 5 mode control register (PMC5). (i) TI011 (timer input) ... Input This is the external count clock input pin for the 16-bit timer. (ii) TI50 (timer input) ... Input This is the external count clock input pin for the 8-bit timer. (iii) TO50 (timer output) ... Output This is the pulse signal output pin for the 8-bit timer. (iv) SOA0 (serial output) ... Output This is the CSIA0 serial transmit data output pin. (v) SIA0 (serial input) ... Input This is the CSIA0 serial receive data input pin. (vi) SCKA0 (serial clock) ... I/O This is the CSIA0 serial clock I/O pin. (vii) RTP00 to RTP05 (real-time output port) ... Output These pins operate as a real-time output port. (viii) KR0 to KR5 (key return) ... Input These are the key interrupt input pins. Their operation is specified by the key return mode register (KRM) in the input port mode.
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(6) P70 to P77 (port 7) ... Input Port 7 is an 8-bit input-only port in which all the pins are fixed to input. In addition to functioning as input ports pins, P70 to P77 can also be used for A/D converter (ADC) analog input in the control mode. Normally, when port and function pins are shared, their operation can be selected by the port mode control register, but in the case of P70 to P77, such a register does not exist. Therefore, these pins cannot be switched between input port and analog input pins for the A/D converter (ADC). For the state of each pin, read the port. (a) Port mode P70 to P77 are input-only pins. (b) Control mode (alternate function) P70 to P77 are shared with ANI0 to ANI7, but switching is not possible. (i) ANI0 to ANI7 (analog input) ... Input These are the analog input pins to the A/D converter (ADC). (7) P90, P91, P96 to P99, P913 to P915 (port 9) ... I/O Port 9 is a 9-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P90, P91, P96 to P99, and P913 to P915 can also be used for serial interface (UART1, CSI01) I/O, 16-bit timer I/O, 8-bit timer output, and external interrupt request input in the control mode. Moreover, they can also function as 16-bit timer inputs, 8-bit timer inputs, and key interrupts in the input port mode. The port mode and control mode can be selected as the operation mode for each bit, and are specified by the port 9 mode control register (PMC9). P90, P91, P96 to P99, and 913 to P915 can be set to control mode 2 in 1-bit units by the port 9 function control register (PFC9). (There is no control mode 1 for these pins. Setting to control mode 1 (PMC9n bit of port 9 mode control register (PMC9) = 1 and PFC9n bit of PFC9 register = 0) is prohibited since output is undefined.) (n = 0, 1, 6 to 9, 13 to 15) Normal output or N-ch open-drain output can be selected for P98 and P99. (a) Port mode P90, P91, P96 to P99, and P913 to P915 can be set to input or output in 1-bit units by the port 9 mode register (PM9). (b) Control mode (alternate function) P90, P91, P96 to P99, and P913 to P915 can be set to the port mode or control mode in 1-bit units by the port 9 mode control register (PMC9). (i) TXD1 (transmit data) ... Output This is the serial transmit data output pin for UART1. (ii) RXD1 (receive data) ... Input This is the serial receive data input pin for UART1. (iii) TI51 (timer input) ... Input This is the external count clock input pin for the 8-bit timer.
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(iv) TO51 (timer output) ... Output This is the pulse signal output pin for the 8-bit timer. (v) SO01 (serial output) ... Output This is the serial transmit data output pin for CSI01. (vi) SI01 (serial input) ... Input This is the serial receive data input pin for CSI01. (vii) SCK01 (serial clock) ... I/O This is the serial clock I/O pin for CSI01. (viii) INTP4 to INTP6 (interrupt request from peripherals) ... Input These are the external interrupt request input pins. (ix) KR6, KR7 (key return) ... Input These are the key interrupt input pins. Their operations are specified by the key return mode register (KRM) in the input port mode. (8) PCM0 to PCM3 (port CM) ... I/O Port CM is a 4-bit I/O port for which input or output can be set in 1-bit units. In addition to functioning as a port, these pins can also be used for wait insertion signal input, internal system clock output, and bus hold control signal I/O in the control mode. The port mode and control mode can be selected as the operation mode for each bit, and are specified by the port CM mode control register (PMCCM). (a) Port mode PCM0 to PCM3 can be set to input or output in 1-bit units by the port CM mode register (PMCM). (b) Control mode PCM0 to PCM3 can be set to the port mode or control mode in 1-bit units by the PMCCM register. (i) WAIT (wait) ... Input This is a control signal input pin that inserts data waits in a bus cycle. This pin supports asynchronous input for CLKOUT. Sampling starts at the falling edge of the CLKOUT signal in the T2 and TW states of the bus cycle. If the setup/hold times in the sampling timing are not satisfied, wait insertion may not be performed. (ii) CLKOUT (clock output) ... Output This is the internal system clock output pin. Since, in the single-chip mode, it is in the port mode during the reset period, output is not performed from CLKOUT. To perform CLKOUT output, set this pin to the control mode by the port CM mode control register (PMCCM). (iii) HLDAK (hold acknowledge) ... Output This is the output pin for the acknowledge signal that indicates that the V850ES/KF1 has received a bus hold request and set the external address/data bus and the strobe pins to high impedance. When this signal is active, the external address/data bus and the strobe pins are in high impedance, and the bus mastership is handed to the external bus master.
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(iv) HLDRQ (hold request) ... Input This is the input pin by which an external device requests the V850ES/KF1 to release the external address/data bus and strobe pins. This pin supports asynchronous input for CLKOUT. When this pin is active, the external address/data bus and strobe pins are set to high impedance either when the V850ES/KF1 completes execution of the current bus cycle, or immediately if no bus cycle is being executed. The HLDAK signal is then made active and the bus is released. To ensure that the bus hold state is entered, keep the HLDRQ signal active until the HLDAK signal is output. (9) PCS0, PCS1 (port CS) ... I/O Port CS is a 2-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as a port, PCS0 and PCS1 can also be used for chip select signal output when the memory is expanded externally in the control mode. The port mode and control mode can be selected as the operation mode for each bit, and are specified by the port CS mode control register (PMCCS). (a) Port mode PCS0 and PCS1 can be set to input or output in 1-bit units by the port CS mode register (PMCS). (b) Control mode PCS0 and PCS1 can be set to the port mode or control mode in 1-bit units by the PMCCS register. (i) CS0, CS1 (chip select) ... Output These are the chip select signals for external memory and external peripheral I/Os. Signal CSn is allocated to memory block n (n = 0, 1). These pins become active when a bus cycle for accessing the corresponding memory block is started. In the idle state (TI), these pins are inactive. (10) PCT0, PCT1, PCT4, PCT6 (port CT) ... I/O Port CT is a 4-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as a port, PCT0, PCT1, PCT4, and PCT6 can also be used for control signal output when the memory is expanded externally in the control mode. The port mode and control mode can be selected as the operation mode for each bit, and are specified by the port CT mode control register (PMCCT). (a) Port mode PCT0, PCT1, PCT4, and PCT6 can be set to input or output in 1-bit units by the port CT mode register (PMCT). (b) Control mode PCT0, PCT1, PCT4, and PCT6 can be set to the port mode or control mode in 1-bit units by the PMCCT register. (i) WR0 (lower byte write strobe) ... Output This is the write strobe signal output pin for the lower data of the external 16-bit data bus.
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(ii)
WR1 (upper byte write strobe) ... Output This is the write strobe signal output pin for the higher data of the external 16-bit data bus.
(iii) RD (read strobe) ... Output This is the strobe signal that indicates that the bus cycle currently being executed is a read cycle for the external memory or external peripheral I/O. In the idle state (TI), this pin is inactive. (iv) ASTB (address strobe) ... Output This is the latch strobe signal output pin for the external address bus. The output becomes low level in synchronization with the falling edge of the clock in the T1 state of the bus cycle, and becomes high level in synchronization with the falling edge of the clock in the T3 state. (11) PDL0 to PDL15 (Port DL) ... I/O Port DL is a 16-bit I/O port that can be set to input or output in 1-bit units. In addition to functioning as a port, PDL0 to PDL15 can also be used as an address/data bus (AD0 to AD15) when the memory is expanded externally in the control mode (external expansion mode). The port mode and control mode can be selected as the operation mode for each bit the port DL mode control register (PMCDL). Note When specifying the port mode/control mode (alternate function) for each bit, pay careful attention to the operation of the alternate functions. (a) Port mode PDL0 to PDL15 can be set to input or output in 1-bit units by the port DL mode register (PMDL). (b) Control mode PDL0 to PDL15 can be used as AD0 to AD15 with the PMCDL register. (i) AD0 to AD15 (address/data bus) ... I/O This is a multiplexed address/data bus during external access. In the address timing (T1 state), these pins function as 16-bit address A0 to A15 output pins, and in the data timing (T2, TW, and T3), they function as data I/O bus pins. (12) RESET (reset) ... Input RESET input is an asynchronous input, and when a signal that has a certain low-level width is input, regardless of the operation clock, system reset is executed with priority over all other actions. In addition to normal initialize and start, RESET can also be used to release the standby mode (HALT, IDLE, and STOP). (13) REGC (regulator control) ... Input This is the pin for connecting a capacitor for the regulator. (14) X1, X2 (crystal for main clock) These pins are used to connect the resonator that generates the main clock. An external clock can also be input. (15) XT1, XT2 (crystal for subclock) These pins are used to connect the resonator that generates the subclock.
Note
, and are specified by
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(16) AVSS (ground for analog) This is the ground pin for the A/D converter. (17) AVREF0 (analog reference voltage) ... Input This is the pin for supplying the reference voltage for the A/D converter. (18) EVDD (power supply for ports) These are the positive power supply pins for the peripheral interface. (19) EVSS (ground for ports) This is the ground pin for the peripheral interface. (20) VDD (power supply) These are the positive power supply pins. Connect all VDD pins to a positive power supply. (21) VPP (programming power supply) This is a positive power supply pin for the flash memory programming mode. It is provided for products with flash memory. During normal mode operation, connect this pin to VSS. (22) VSS (ground) These are the ground pins. Connect all VSS pins to a positive power supply. (23) IC (internally connected) This is an internally connected pin. Connect this pin directly to VSS in the normal operation mode.
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2.3.2 V850ES/KG1 (1) P00 to P06 (port 0) ... I/O Port 0 is a 7-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P00 to P06 can also be used for NMI input, external interrupt request input, and timer H output in the control mode. The port mode and control mode (alternate functions) can be selected as the operation mode for each bit, and are specified by the port 0 mode control register (PMC0). (a) Port mode P00 to P06 can be set to input or output in 1-bit units by the port 0 mode register (PM0). (b) Control mode (alternate function) P00 to P06 can be set to the port mode or control mode in 1-bit units by the port 0 mode control register (PMC0). (i) NMI (non-maskable interrupt request) ... Input This is a non-maskable interrupt request input pin. (ii) INTP0 to INTP3 (interrupt request from peripherals) ... Input These are external interrupt request input pins. (iii) TOH0, TOH1 (timer output) ... Output These are timer H pulse signal output pins. (2) P10, P11 (port 1) ... I/O Port 1 is a 2-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P10 and P11 can also be used for D/A converter analog output. The port mode and control mode cannot be selected as the operation mode for each bit. To use these pins as D/A converter analog output pins, set the port 1 mode register (PM1) to output (03H). (a) Port mode P10 and P11 can be set to input or output in 1-bit units by the port 1 mode register (PM1). (i) ANO0, ANO1 (analog output) ... Output These are analog output pins to the D/A converter (DAC). (3) P30 to P39 (port 3) ... I/O Port 3 is a 10-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P30 to P39 can also be used for serial interface (UART0, I C0) I/O and 16-bit timer input in control mode 1, and for 16-bit timer output in control mode 2. The port mode and control mode can be selected as the operation mode for each bit, and are specified by the port 3 mode control register (PMC3). P33 and P35 can be set to control mode 1 or control mode 2 in 1-bit units by the port 3 function control register (PFC3). When used as outputs, P36 to P39 are fixed to N-ch open-drain output. (a) Port mode P30 to P39 can be set to input or output in 1-bit units by the port 3 mode register (PM3).
2
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(b) Control mode P30 to P39 can be set to the port mode or control mode in 1-bit units by the port 3 mode control register (PMC3). P33 and P35 can be set to control mode 1 or control mode 2 in 1-bit units by the port 3 function control register (PFC3). (i) TXD0 (transmit data) ... Output This is the serial transmit data output pin for UART0. (ii) RXD0 (receive data) ... Input This is the serial receive data input pin for UART0. (iii) ASCK0 (asynchronous serial clock) ... Input This is the serial baud rate clock input pin for UART0. (iv) TI000, TI001, TI010 (timer input) ... Input These are the external count clock input pins for the 16-bit timer. (v) TO00, TO01 (timer output) ... Output These are the pulse signal output pins for the 16-bit timer. (vi) SDA0 (serial data) ... I/O This is the serial transmit/receive data I/O pin for I C0 (only for the PD703212Y, 703213Y, 703214Y,
2
and 70F3214Y). (vii) SCL0 (serial clock) ... I/O This is the serial clock I/O pin for I C0 (only for the PD703212Y, 703213Y, 703214Y, and 70F3214Y).
2
(4) P40 to P42 (port 4) ... I/O Port 4 is a 3-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P40 to P42 can also be used for serial interface (CSI00) I/O in the control mode. The port mode and control mode can be selected as the operation mode for each bit, and are specified by the port 4 mode control register (PMC4). Normal output and N-ch open-drain output can be selected for P41 and P42. (a) Port mode P40 to P42 can be set to input or output in 1-bit units by the port 4 mode register (PM4). (b) Control mode P40 to P42 can be set to the port mode or control mode in 1-bit units by the PMC4 register. (i) SO00 (serial output) ... Output This is the serial transmit data output pin for CSI00. (ii) SI00 (serial input) ... Input This is the serial receive data input pin for CSI00.
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(iii) SCK00 (serial clock) ... I/O This is the serial clock I/O pin for CSI00. (5) P50 to P55 (port 5) ... I/O Port 5 is a 6-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P50 to P55 can also be used as 16-bit timer input, 8-bit timer I/O, and serial interface (CSIA0) I/O pins in control mode 1, and as real-time output port pins in control mode 2. They can also be used for key interrupt input by setting key return mode register KRM while in the input port mode. The port mode and control mode (alternate functions) can be selected as the operation mode in 1-bit units, and are specified by the port 5 mode control register (PMC5). P50 to P55 can be set to control mode 1 or control mode 2 in 1-bit units by the port 5 function control register (PFC5). Normal output and N-ch open-drain output can be selected for P54 and P55. (a) Port mode P50 to P55 can be set to input or output in 1-bit units by the port 5 mode register (PM5). (b) Control mode (alternate function) P50 to P55 can be set to the port mode or control mode in 1-bit units by the port 5 mode control register (PMC5). (i) TI011 (timer input) ... Input This is the external count clock input pin for the 16-bit timer. (ii) TI50 (timer input) ... Input This is the external count clock input pin for the 8-bit timer. (iii) TO50 (timer output) ... Output This is the pulse signal output pin for the 8-bit timer. (iv) SOA0 (serial output) ... Output This is the CSIA0 serial transmit data output pin. (v) SIA0 (serial input) ... Input This is the CSIA0 serial receive data input pin. (vi) SCKA0 (serial clock) ... I/O This is the CSIA0 serial clock I/O pin. (vii) RTP00 to RTP05 (real-time output port) ... Output These pins operate as a real-time output port. (viii) KR0 to KR5 (key return) ... Input These are the key interrupt input pins. Their operation is specified by the key return mode register (KRM) in the input port mode.
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(6) P70 to P77 (port 7) ... Input Port 7 is an 8-bit input-only port in which all the pins are fixed to input. In addition to functioning as input ports pins, P70 to P77 can also be used for A/D converter (ADC) analog input in the control mode. Normally, when port and function pins are shared, their operation can be selected by the port mode control register, but in the case of P70 to P77, such a register does not exist. Therefore, these pins cannot be switched between input port and analog input pins for the A/D converter (ADC). For the state of each pin, read the port. (a) Port mode P70 to P77 are input-only pins. (b) Control mode (alternate function) P70 to P77 are shared with ANI0 to ANI7, but switching is not possible. (i) ANI0 to ANI7 (analog input) ... Input These are the analog input pins to the A/D converter (ADC). (7) P90 to P915 (port 9) ... I/O Port 9 is a 16-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P90 to P915 can also be used for lower 16-bit address output within a 22-bit address on the address bus during external access in control mode 1, and for serial interface (UART1, CSI01, CSIA1) I/O, 16-bit timer I/O, 8-bit timer output, and external interrupt request input in control mode 2. Moreover, they can also function as 16-bit timer inputs, 8-bit timer inputs, and key interrupts in the input port mode. The port mode and control mode (alternate functions) can be selected as the operation mode for each bit, and are specified by the port 9 mode control register (PMC9). P90 to P915 can be set to control mode 1 or control mode 2 in 1-bit units by the port 9 function control register (PFC9). Normal output or N-ch open-drain output can be selected for P98, P99, P911, and P912. (a) Port mode P90 to P915 can be set to input or output in 1-bit units by the port 9 mode register (PM9) (when used as the A0 to A15 pins, mode switching in 16-bit units is necessary). (b) Control mode (alternate function) P90 to P915 can be set to the port mode or control mode in 1-bit units by the port 9 mode control register (PMC9). (i) A0 to A15 (address bus) ... Output These are the lower 16-bit address output pins within a 22-bit address on the address bus during external access. (ii) TXD1 (transmit data) ... Output This is the serial transmit data output pin for UART1. (iii) RXD1 (receive data) ... Input This is the serial receive data input pin for UART1.
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(iv) TI020, TI021, TI030, TI031 (timer input) ... Input These are the external count clock input pins for the 16-bit timer. (v) TO02, TO03 (timer output) ... Output These are the pulse signal output pins for the 16-bit timer. (vi) TI51 (timer input) ... Input This is the external count clock input pin for the 8-bit timer. (vii) TO51 (timer output) ... Output This is the pulse signal output pin for the 8-bit timer. (viii) SO01, SOA1 (serial output) ... Output These are the serial transmit data output pins for CSI01 and CSIA1. (ix) SI01, SIA1 (serial input) ... Input These are the serial receive data input pins for CSI01 and CSIA1. (x) CSK01, SCKA1 (serial clock) ... I/O These are the serial clock I/O pins for CSI01 and CSIA1. (ix) INTP4 to INTP6 (interrupt request from peripherals) ... Input These are the external interrupt request input pins. (iix) KR6, KR7 (key return) ... Input These are the key interrupt input pins. Their operation is specified by the key return mode register (KRM) in the input port mode. (8) PCM0 to PCM3 (port CM) ... I/O Port CM is a 4-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, PCM0 to PCM3 can also be used for wait insertion signal input, internal system clock output, and bus hold control signal I/O in the control mode. The port mode and control mode can be selected as the operation mode for each bit, and are specified by the port CM mode control register (PMCCM). (a) Port mode PCM0 to PCM3 can be set to input or output in 1-bit units by the port CM mode register (PMCM). (b) Control mode PCM0 to PCM3 can be set to the port mode or control mode in 1-bit units by the PMCCM register. (i) WAIT (wait) ... Input This is a control signal input pin that inserts data waits in a bus cycle. This pin supports asynchronous input for CLKOUT. In the multiplex mode, sampling starts at the falling edge of the CLKOUT signal in the T2 and TW states of the bus cycle. In the separate mode, sampling starts at the rising edge of the CLKOUT signal in the T1 and TW states of the bus cycle. If the setup/hold times in the sampling timing are not satisfied, wait insertion may not be performed.
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(ii)
CLKOUT (clock output) ... Output This is the internal system clock output pin. Since it is in the port mode during the reset period, output is not performed from the CLKOUT pin. To perform CLKOUT output, set this pin to the control mode with the port CM mode control register (PMCCM).
(iii) HLDAK (hold acknowledge) ... Output This is the output pin for the acknowledge signal that indicates that the V850ES/KG1 has received a bus hold request and set the external address/data bus and the strobe pins to high impedance. When this signal is active, the external address/data bus and the strobe pins are in high impedance, and the bus mastership is handed to the external bus master. (iv) HLDRQ (hold request) ... Input This is the input pin by which an external device requests the V850ES/KG1 to release the external address/data bus and strobe pins. This pin supports asynchronous input for CLKOUT. When this pin is active, the external address/data bus and strobe pins are set to high impedance either when the V850ES/KG1 completes execution of the current bus cycle, or immediately if no bus cycle is being executed. The HLDAK signal is then made active and the bus is released. To ensure that the bus hold state is entered, keep the HLDRQ signal active until the HLDAK signal is output. (9) PCS0, PCS1 (port CS) ... I/O Port CS is a 2-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as a port, PCS0 and PCS1 can also be used for chip select signal output when the memory is expanded externally in the control mode. The port mode and control mode can be selected as the operation mode for each bit, and are specified by the port CS mode control register (PMCCS). (a) Port mode PCS0 and PCS1 can be set to input or output in 1-bit units by the port CS mode register (PMCS). (b) Control mode PCS0 and PCS1 can be set to the port mode or control mode in 1-bit units by the PMCCS register. (i) CS0, CS1 (chip select) ... Output These are the chip select signals for external memory and external peripheral I/Os. Signal CSn is allocated to memory block n (n = 0, 1). These pins become active when a bus cycle for accessing the corresponding memory block is started. In the idle state (TI), these pins are inactive. (10) PCT0, PCT1, PCT4, PCT6 (port CT) ... I/O Port CT is a 4-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as a port, PCT0, PCT1, PCT4, and PCT6 can also be used for control signal output when the memory is expanded externally in the control mode. The port mode and control mode can be selected as the operation mode for each bit, and are specified by the port CT mode control register (PMCCT).
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(a) Port mode PCT0, PCT1, PCT4, and PCT6 can be set to input or output in 1-bit units by the port CT mode register (PMCT). (b) Control mode PCT0, PCT1, PCT4, and PCT6 can be set to the port mode or control mode in 1-bit units by the PMCCT register. (i) WR0 (lower byte write strobe) ... Output This is the write strobe signal output pin for the lower data of the external 16-bit data bus. (ii) WR1 (upper byte write strobe) ... Output This is the write strobe signal output pin for the higher data of the external 16-bit data bus. (iii) RD (read strobe) ... Output This is the strobe signal that indicates that the bus cycle currently being executed is a read cycle for the external memory or external peripheral I/O. In the idle state (TI), this pin is inactive. (iv) ASTB (address strobe) ... Output This is the latch strobe signal output pin for the external address bus. The output becomes low level in synchronization with the falling edge of the clock in the T1 state of the bus cycle, and becomes high level in synchronization with the falling edge of the clock in the T3 state. (11) PDH0 to PDH5 (Port DH) ... I/O Port DH is a 6-bit I/O port that can be set to input or output in 1-bit units. In addition to functioning as a port, PDH0 to PDH5 can also be used as an address bus (A16 to A21) when the memory is expanded externally in the control mode (external expansion mode). The port mode and control mode can be selected as the operation mode for each bit the port DH mode control register (PMCDH). Note When specifying the port mode/control mode (alternate function) for each bit, pay careful attention to the operation of the alternate functions. (a) Port mode PDH0 to PDH5 can be set to input or output in 1-bit units by the port DH mode register (PMDH). (b) Control mode PDH0 to PDH5 can be used as A16 to A21 by the PMCDH register. (i) A16 to A21 (address bus) ... Output These are the higher 6-bit address output pins within a 22-bit address on the address bus during external access. (12) PDL0 to PDL15 (Port DL) ... I/O Port DL is a 16-bit I/O port that can be set to input or output in 1-bit units.
Note
, and are specified by
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In addition to functioning as a port, PDL0 to PDL15 can also be used as an address/data bus in the multiplex mode and as a data bus in the separate mode when the memory is expanded externally in the control mode (external expansion mode). The port mode and control mode can be selected as the operation mode for each bit the port DL mode control register (PMCDL). Note When specifying the port mode/control mode (alternate function) for each bit, pay careful attention to the operation of the alternate functions. (a) Port mode PDL0 to PDL15 can be set to input or output in 1-bit units by the port DL mode register (PMDL). (b) Control mode PDL0 to PDL15 can be used as AD0 to AD15 by the PMCDL register. (i) AD0 to AD15 (address/data bus) ... I/O This is a multiplexed address/data bus during external access. In the address timing (T1 state), these pins function as 22-bit address A0 to A15 output pins, and in the data timing (T2, TW, and T3), they function as 16-bit data I/O bus pins. (13) RESET (reset) ... Input RESET input is an asynchronous input, and when a signal that has a certain low-level width is input, regardless of the operation clock, system reset is executed with priority over all other actions. In addition to normal initialize and start, RESET can also be used to release the standby mode (HALT, IDLE, and STOP). (14) REGC (regulator control) ... Input This is the pin for connecting a capacitor for the regulator. (15) X1, X2 (crystal for main clock) These pins are used to connect the resonator that generates the main clock. An external clock can also be input. (16) XT1, XT2 (crystal for subclock) These pins are used to connect the resonator that generates the subclock. (17) AVSS (ground for analog) This is the ground pin for the A/D converter and D/A converter. (18) AVREF0 (analog reference voltage) ... Input This is the pin for supplying the reference voltage for the A/D converter. (19) AVREF1 (analog reference voltage) ... Input This is the pin for supplying the reference voltage for the D/A converter. (20) BVDD (power supply for bus interface) This is the positive power supply pin for the bus interface.
Note
, and are specified by
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(21) BVSS (ground for bus interface) This is the ground pin for the bus interface. (22) EVDD (power supply for ports) This is the power supply pin for the peripheral interface. (23) EVSS (ground for ports) This is the ground pin for the peripheral interface. (24) VDD (power supply) These are the positive power supply pins. All VDD pins should be connected to a positive power supply. (25) VPP (programming power supply) This is the positive power supply pin used for the flash memory programming mode. It is provided for products with flash memory. During normal mode operation, connect this pin to VSS. (26) VSS (ground) These are the ground pins. Connect all VSS pins to a positive power supply. (27) IC (internally connected) This is an internally connected pin. Connect this pin directly to VSS in the normal operation mode.
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2.3.3 V850ES/KJ1 (1) P00 to P06 (port 0) ... I/O Port 0 is a 7-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P00 to P06 can also be used for NMI input, external interrupt request input, and timer H output in the control mode. The port mode and control mode (alternate functions) can be selected as the operation mode for each bit, and are specified by the port 0 mode control register (PMC0). (a) Port mode P00 to P06 can be set to input or output in 1-bit units by the port 0 mode register (PM0). (b) Control mode (alternate function) P00 to P06 can be set to the port mode or control mode in 1-bit units by the port 0 mode control register (PMC0). (i) NMI (non-maskable interrupt request) ... Input This is a non-maskable interrupt request input pin. (ii) INTP0 to INTP3 (interrupt request from peripherals) ... Input These are external interrupt request input pins. (iii) TOH0, TOH1 (timer output) ... Output These are timer H pulse signal output pins. (2) P10, P11 (port 1) ... I/O Port 1 is a 2-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P10 and P11 can also be used for D/A converter analog output. The port mode and control mode cannot be selected as the operation mode for each bit. To use these pins as D/A converter analog output pins, set the port 1 mode register (PM1) to output (03H). (a) Port mode P10 and P11 can be set to input or output in 1-bit units by the port 1 mode register (PM1). (i) ANO0, ANO1 (analog output) ... Output These are analog output pins to the D/A converter (DAC). (3) P30 to P39 (port 3) ... I/O Port 3 is a 10-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P30 to P39 can also be used for serial interface (UART0, I C0) I/O and 16-bit timer input in control mode 1, and for 16-bit timer output in control mode 2. The port mode and control mode can be selected as the operation mode for each bit, and are specified by the port 3 mode control register (PMC3). P33 and P35 can be set to control mode 1 or control mode 2 in 1-bit units by the port 3 function control register (PFC3). When used as outputs, P36 to P39 are fixed to N-ch open-drain output. (a) Port mode P30 to P39 can be set to input or output in 1-bit units by the port 3 mode register (PM3).
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(b) Control mode P30 to P39 can be set to the port mode or control mode in 1-bit units by the port 3 mode control register (PMC3). P33 and P35 can be set to control mode 1 or control mode 2 in 1-bit units by the port 3 function control register (PFC3). (i) TXD0 (transmit data) ... Output This is the serial transmit data output pin for UART0. (ii) RXD0 (receive data) ... Input This is the serial receive data input pin for UART0. (iii) ASCK0 (asynchronous serial clock) ... Input This is the serial baud rate clock input pin for UART0. (iv) TI000, TI001, TI010 (timer input) ... Input These are the external count clock input pins for the 16-bit timer. (v) TO00, TO01 (timer output) ... Output These are the pulse signal output pins for the 16-bit timer. (vi) SDA0 (serial data) ... I/O This is the serial transmit/receive data I/O pin for I C0 (only for the PD703216Y, 703217Y, and
2
70F3217Y). (vii) SCL0 (serial clock) ... I/O This is the serial clock I/O pin for I C0 (only for the PD703216Y, 703217Y, and 70F3217Y).
2
(4) P40 to P42 (port 4) ... I/O Port 4 is a 3-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P40 to P42 can also be used for serial interface (CSI00) I/O in the control mode. The port mode and control mode can be selected as the operation mode for each bit, and are specified by the port 4 mode control register (PMC4). Normal output and N-ch open-drain output can be selected for P41 and P42. (a) Port mode P40 to P42 can be set to input or output in 1-bit units by the port 4 mode register (PM4). (b) Control mode P40 to P42 can be set to the port mode or control mode in 1-bit units by the PMC4 register. (i) SO00 (serial output) ... Output This is the serial transmit data output pin for CSI00. (ii) SI00 (serial input) ... Input This is the serial receive data input pin for CSI00.
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(iii) SCK00 (serial clock) ... I/O This is the serial clock I/O pin for CSI00. (5) P50 to P55 (port 5) ... I/O Port 5 is a 6-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P50 to P55 can also be used as 16-bit timer input, 8-bit timer I/O, and serial interface (CSIA0) I/O pins in control mode 1, and as real-time output port pins in control mode 2. They can also be used for key interrupt input by setting key return mode register (KRM) while in the input port mode. The port mode and control mode (alternate functions) can be selected as the operation mode in 1-bit units, and are specified by the port 5 mode control register (PMC5). P50 to P55 can be set to control mode 1 or control mode 2 in 1-bit units by the port 5 function control register (PFC5). Normal output and N-ch open-drain output can be selected for P54 and P55. (a) Port mode P50 to P55 can be set to input or output in 1-bit units by the port 5 mode register (PM5). (b) Control mode (alternate function) P50 to P55 can be set to the port mode or control mode in 1-bit units by the port 5 mode control register (PMC5). (i) TI011 (timer input) ... Input This is the external count clock input pin for the 16-bit timer. (ii) TI50 (timer input) ... Input This is the external count clock input pin for the 8-bit timer. (iii) TO50 (timer output) ... Output This is the pulse signal output pin for the 8-bit timer. (iv) SOA0 (serial output) ... Output This is the CSIA0 serial transmit data output pin. (v) SIA0 (serial input) ... Input This is the CSIA0 serial receive data input pin. (vi) SCKA0 (serial clock) ... I/O This is the CSIA0 serial clock I/O pin. (vii) RTP00 to RTP05 (real-time output port) ... Output These pins operate as a real-time output port. (viii) KR0 to KR5 (key return) ... Input These are the key interrupt input pins. Their operation is specified by the key return mode register (KRM) in the input port mode.
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(6) P60 to P615 (port 6) ... I/O Port 6 is a 16-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P60 to P615 can also be used for real-time output port function, serial interface (CSI02) I/O, and 16-bit timer I/O in control mode 1, and for 16-bit timer output in control mode 2. The port mode and control mode (alternate functions) can be selected as the operation mode for each bit, and are specified by the port 6 mode control register (PMC6). P613 can be set to control mode 1 or control mode 2 in 1-bit units by the port 6 function control register (PFC6). Normal output or N-ch open-drain output can be selected for P67 and P68. (a) Port mode P60 to P615 can be set to input or output in 1-bit units by the port 6 mode register (PM6). (b) Control mode (alternate function) P60 to P615 can be set to the port mode or control mode in 1-bit units by the port 6 mode control register (PMC6). (i) RTP10 to RTP15 (real-time output port) ... Output These pins operate as a real-time output port. (ii) SO02 (serial output) ... Output This is the serial transmit data output pin for CSI02. (iii) SI02 (serial input) ... Input This is the serial receive data input pin for CSI02. (iv) SCK02 (serial clock) ... I/O This is the serial clock I/O pin for CSI02. (v) TI040, TI041, TI050, TI051 (timer input) ... Input These are the external count clock input pins for the 16-bit timer. (vi) TO04, TO05 (timer output) ... Output These are the pulse signal output pins for the 16-bit timer. (7) P70 to P715 (port 7) ... Input Port 7 is a 16-bit input-only port in which all the pins are fixed to input. In addition to functioning as an input port, P70 to P715 can also be used as A/D converter (ADC) analog input pins in the control mode. Normally, when port and function pins are shared, their operation can be selected by the port mode control register, but in the case of P70 to P715, such a register does not exist. Therefore, these pins cannot be switched between input port and analog input pins for the A/D converter (ADC). For the state of each pin, read the port. (a) Port mode P70 to P715 are input-only pins.
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(b) Control mode (alternate function) P70 to P715 are shared with ANI0 to ANI15, but switching is not possible. (i) ANI0 to ANI15 (analog input) ... Input These are the analog input pins to the A/D converter (ADC). (8) P80, P81 (port 8) ... Input Port 8 is a 2-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P80 and P81 can also be used for serial interface (UART2) I/O in control mode 1, and for serial interface (I C1) I/O in control mode 2. The port mode and control mode (alternate functions) can be selected as the operation mode for each bit, and are specified by the port 8 mode control register (PMC8). P80 and P81 can be set to control mode 1 or control mode 2 in 1-bit units by the port 8 function control register (PFC8). (a) Port mode P80 and P81 can be set to input or output in 1-bit units by the port 8 mode register (PM8). (b) Control mode (alternate function) P80 and P81 can be set to the port mode or control mode in 1-bit units by the port 8 mode control register (PMC8). (i) TXD2 (transmit data) ... Output This is the serial transmit data output pin for UART2. (ii) RXD2 (receive data) ... Input This is the serial receive data input pin for UART2. (iii) SDA1 (serial data) ... I/O This is the serial transmit/receive data I/O pin for I C1 (only for the PD703216Y, 703217Y, and
2 2
70F3217Y). (iv) SCL1 (serial clock) ... I/O This is the serial clock I/O pin for I C1 (only for the PD703216Y, 703217Y, and 70F3217Y).
2
(9) P90 to P915 (port 9) ... I/O Port 9 is a 16-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P90 to P915 can also be used for lower 16-bit address output within a 24-bit address on the address bus during external access in control mode 1, and for serial interface (UART1, CSI01, CSIA1) I/O, 16-bit timer I/O, 8-bit timer output, and external interrupt request input in control mode 2. Moreover, they can also function as 16-bit timer inputs, 8-bit timer inputs, and key interrupt inputs in the input port mode. The port mode and control mode (alternate functions) can be selected as the operation mode for each bit, and are specified by the port 9 mode control register (PMC9). P90 to P915 can be set to control mode 1 or control mode 2 in 1-bit units by the port 9 function control register (PFC9). Normal output or N-ch open-drain output can be selected for P98, P99, P911, and P912.
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(a) Port mode P90 to P915 can be set to input or output in 1-bit units by the port 9 mode register (PM9). (b) Control mode (alternate function) P90 to P915 can be set to the port mode or control mode in 1-bit units by the port 9 mode control register (PMC9) (when used as the A0 to A15 pins, mode switching in 16-bit units is necessary). (i) A0 to A15 (address bus) ... Output These are the lower 16-bit address output pins within a 24-bit address on the address bus during external access. (ii) TXD1 (transmit data) ... Output This is the serial transmit data output pin for UART1. (iii) RXD1 (receive data) ... Input This is the serial receive data input pin for UART1. (iv) TI020, TI021, TI030, TI031 (timer input) ... Input These are the external count clock input pins for the 16-bit timer. (v) TO02, TO03 (timer output) ... Output These are the pulse signal output pins for the 16-bit timer. (vi) TI51 (timer input) ... Input This is the external count clock input pin for the 8-bit timer. (vii) TO51 (timer output) ... Output This is the pulse signal output pin for the 8-bit timer. (viii) SO01, SOA1 (serial output) ... Output These are the serial transmit data output pins for CSI01 and CSIA1. (ix) SI01, SIA1 (serial input) ... Input These are the serial receive data input pins for CSI01 and CSIA1. (x) CSK01, SCKA1 (serial clock) ... I/O These are the serial clock I/O pins for CSI01 and CSIA1. (ix) INTP4 to INTP6 (interrupt request from peripherals) ... Input These are the external interrupt request input pins. (iix) KR6, KR7 (key return) ... Input These are the key interrupt input pins. Their operation is specified by the key return mode register (KRM) in the input port mode.
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(10) PCD0 to PCD3 (port CD) ... I/O Port CD is a 4-bit I/O port for which input and output can be set in 1-bit units. PCD0 to PCD3 operate as an I/O port. (a) Port mode PCD0 to PCD3 can be set to input or output in 1-bit units by the port CD mode register (PMCD). (11) PCM0 to PCM5 (port CM) ... I/O Port CM is a 6-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, PCM0 to PCM5 can also be used for wait insertion signal input, internal system clock output, and bus hold control signal I/O in the control mode. The port mode and control mode can be selected as the operation mode for each bit, and are specified by the port CM mode control register (PMCCM). (a) Port mode PCM0 to PCM5 can be set to input or output in 1-bit units by the port CM mode register (PMCM). (b) Control mode PCM0 to PCM5 can be set to the port mode or control mode in 1-bit units by the PMCCM register. (i) WAIT (wait) ... Input This is a control signal input pin that inserts data waits in a bus cycle. This pin supports asynchronous input for CLKOUT. In the multiplex mode, sampling starts at the falling edge of the CLKOUT signal in the T2 and TW states of the bus cycle. In the separate mode, sampling starts at the rising edge of the CLKOUT signal in the T1 and TW states of the bus cycle. If the setup/hold times in the sampling timing are not satisfied, wait insertion may not be performed. (ii) CLKOUT (clock output) ... Output This is the internal system clock output pin. Since it is in the port mode during the reset period, output is not performed from the CLKOUT pin. To perform CLKOUT output, set this pin to the control mode by the port CM mode control register (PMCCM). (iii) HLDAK (hold acknowledge) ... Output This is the output pin for the acknowledge signal that indicates that the V850ES/KJ1 has received a bus hold request and set the external address/data bus and the strobe pins to high impedance. When this signal is active, the external address/data bus and the strobe pins are in high impedance, and the bus mastership is handed to the external bus master. (iv) HLDRQ (hold request) ... Input This is the input pin by which an external device requests the V850ES/KJ1 to release the external address/data bus and strobe pins. This pin supports asynchronous input for CLKOUT. When this pin is active, the external address/data bus and strobe pins are set to high impedance either when the V850ES/KJ1 completes execution of the current bus cycle, or immediately if no bus cycle is being executed. The HLDAK signal is then made active and the bus is released. To ensure that the bus hold state is entered, keep the HLDRQ signal active until the HLDAK signal is output.
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(12) PCS0 to PCS7 (port CS) ... I/O Port CS is an 8-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as a port, PCS0 to PCS7 can also be used for chip select signal output when the memory is expanded externally in the control mode. The port mode and control mode can be selected as the operation mode for each bit, and are specified by the port CS mode control register (PMCCS). (a) Port mode PCS0 to PCS7 can be set to input or output in 1-bit units by the port CS mode register (PMCS). (b) Control mode PCS0 to PCS7 can be set to the port mode or control mode in 1-bit units by the PMCCS register. (i) CS0 to CS3 (chip select) ... Output These are the chip select signals for external memory and external peripheral I/Os. Signal CSn is allocated to memory block n (n = 0 to 3). These pins become active when a bus cycle for accessing the corresponding memory block is started. In the idle state (TI), these pins are inactive. (13) PCT0 to PCT7 (port CT) ... I/O Port CT is an 8-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as a port, PCT0 to PCT7 can also be used for control signal output when the memory is expanded externally in the control mode. The port mode and control mode can be selected as the operation mode for each bit, and are specified by the port CT mode control register (PMCCT). (a) Port mode PCT0 to PCT7 can be set to input or output in 1-bit units by the port CT mode register (PMCT). (b) Control mode PCT0 to PCT7 can be set to the port mode or control mode in 1-bit units by the PMCCT register. (i) WR0 (lower byte write strobe) ... Output This is the write strobe signal output pin for the lower data of the external 16-bit data bus. (ii) WR1 (upper byte write strobe) ... Output This is the write strobe signal output pin for the higher data of the external 16-bit data bus. (iii) RD (read strobe) ... Output This is the strobe signal that indicates that the bus cycle currently being executed is a read cycle for the external memory or external peripheral I/O. In the idle state (TI), this pin is inactive. (iv) ASTB (address strobe) ... Output This is the latch strobe signal output pin for the external address bus. The output becomes low level in synchronization with the falling edge of the clock in the T1 state of the bus cycle, and becomes high level in synchronization with the falling edge of the clock in the T3 state.
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(14) PDH0 to PDH7 (port DH) ... I/O Port DH is an 8-bit I/O port that can be set to input or output in 1-bit units. In addition to functioning as a port, PDH0 to PDH7 can also be used as an address bus (A16 to A23) when the memory is expanded externally in the control mode (external expansion mode). The port mode and control mode can be selected as the operation mode for each bit the port DH mode control register (PMCDH). Note When specifying the port mode/control mode (alternate function) for each bit, pay careful attention to the operation of the alternate functions. (a) Port mode PDH0 to PDH7 can be set to input or output in 1-bit units by the port DH mode register (PMDH). (b) Control mode PDH0 to PDH7 can be used as A16 to A23 by the PMCDH register. (i) A16 to A23 (address bus) ... Output These are the higher 8-bit address output pins within a 24-bit address on the address bus during external access. (15) PDL0 to PDL15 (port DL) ... I/O Port DL is a 16-bit I/O port that can be set to input or output in 1-bit units. In addition to functioning as a port, PDL0 to PDL15 can also be used as an address/data bus in the multiplex mode and as a data bus in the separate mode when the memory is expanded externally in the control mode (external expansion mode). The port mode and control mode can be selected as the operation mode for each bit the port DL mode control register (PMCDL). Note When specifying the port mode/control mode (alternate function) for each bit, pay careful attention to the operation of the alternate functions. (a) Port mode PDL0 to PDL15 can be set to input or output in 1-bit units by the port DL mode register (PMDL). (b) Control mode PDL0 to PDL15 can be used as AD0 to AD15 by the PMCDL register. (i) AD0 to AD15 (address/data bus) ... I/O This is a multiplexed address/data bus during external access. In the address timing (T1 state), these pins function as 24-bit address A0 to A15 output pins, and in the data timing (T2, TW, and T3), they function as 16-bit data I/O bus pins. (16) RESET (reset) ... Input RESET input is an asynchronous input, and when a signal that has a certain low-level width is input, regardless of the operation clock, system reset is executed with priority over all other actions. In addition to normal initialize and start, RESET can also be used to release the standby mode (HALT, IDLE, and STOP).
Note Note
, and are specified by
, and are specified by
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(17) REGC (regulator control) ... Input This is the pin for connecting a capacitor for the regulator. (18) X1, X2 (crystal for main clock) These pins are used to connect the resonator that generates the main clock. An external clock can also be input. (19) XT1, XT2 (crystal for subclock) These pins are used to connect the resonator that generates the subclock. (20) AVSS (ground for analog) This is the ground pin for the A/D converter and D/A converter. (21) AVREF0 (analog reference voltage) ... Input This is the pin for supplying the reference voltage for the A/D converter. (22) AVREF1 (analog reference voltage) ... Input This is the pin for supplying the reference voltage for the D/A converter. (23) BVDD (power supply for bus interface) This is the positive power supply pin for the bus interface. (24) BVSS (ground for bus interface) This is the ground pin for the bus interface. (25) EVDD (power supply for ports) This is the power supply pin for the peripheral interface. (26) EVSS (ground for ports) This is the ground pin for the peripheral interface. (27) VDD (power supply) These are the positive power supply pins. All VDD pins should be connected to a positive power supply. (28) VPP (programming power supply) This is the positive power supply pin used for the flash memory programming mode. It is provided for products with flash memory. During normal mode operation, connect this pin to VSS. (29) VSS (ground) These are the ground pins. Connect all VSS pins to a positive power supply. (30) IC (internally connected) This is an internally connected pin. Connect this pin directly to VSS in the normal operation mode.
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2.4 Pin I/O Circuits and Recommended Connection of Unused Pins
(1/3)
Pin P00 P01 P02 P03 to P06 P10 P11 P30 P31 P32 P33 P34 P35 P36, P37 P38 P39 P40 P41 P42 P50 P51 P52 P53 P54 P55 P60 to P65 P66 P67 P68 P69 P610 P611 P612 P613 P614, P615 P70 to P77 P78 to P715 SDA0 SCL0 SI00 SO00 SCK00 TI011/RTP00/KR0 TI50/RTP01/KR1 TO50/RTP02/KR2 SIA0/RTP03/KR3 SOA0/RTP04/KR4 SCKA0/RTP05/KR5 RTP10 to RTP15 SI02 SO02 SCK02 TI040 TI041 TO04 TI050 TI051/TO05 - ANI0 to ANI7 ANI8 to ANI15
2
Note
Alternate Function TOH0 TOH1 NMI INTP0 to INTP3 ANO0 ANO1 TXD0 RXD0 ASCK0 TI000/TO00 TI001 TI010/TO01 -
I/O Circuit Type 5-A
Recommended Connection Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open.
Product All products
5-W
12-B
Input: Independently connect to AVREF1 or AVSS via a resistor. Output: Leave open.
KG1, KJ1
5-A 5-W
Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open
All products
13-B 13-AE
KG1, KJ1 All products
Note
5-W 10-E 10-F 8-A
All products
All products
10-A
5-A 5-W 10-E 10-F 5-W
KJ1
5-A 5-W
13-B 9-C Connect to AVREF0 or AVSS. All products KJ1
Note Only for products with an I C bus. Remark KG1: V850ES/KG1, KJ1: V850ES/KJ1
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(2/3)
Pin P80 P81 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P910 P911 P912 P913 P914, P915 PCD0 to PCD3 PCM0 PCM1 PCM2 PCM3 PCM4,PCM5 PCS0, PCS1 PCS2, PCS3 PCS4 to PCS7 PCT0 PCT1 PCT2,PCT3 PCT4 PCT5 PCT6 PCT7 ASTB - 5 5 RD - WR0 WR1 - KJ1 All products KJ1 All products KJ1 All products KG1, KJ1 KJ1 - - - - - - Directly connect to VDD. Directly connect to VDD. - All products KG1, KJ1 All products CS0, CS1 CS2, CS3 - 5 All products WAIT CLKOUT HLDAK HLDRQ - 5 KJ1 All products KJ1 Alternate Function RXD2/SDA1Note TXD2/SCL1
Note
I/O Circuit Type 10-F
Recommended Connection Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open.
Product KJ1
A0/TXD1/KR6 A1/RXD1/KR7 A2/TI020/TO02 A3/TI021 A4/TI030/TO03 A5/TI031 A6/TI51/TO51 A7/SI01 A8/SO01 A9/SCK01 A10/SIA1 A11/SOA1 A12/SCKA1 A13/INTP4 A14/INTP5, A15/INTP6 -
8-A
All products
KG1, KJ1 5-W 8-A 5-W 8-A 5-W 10-E 10-F 5-W 10-E 10-F 5-W 8-A 5 5 Input: Independently connect to BVDD or BVSS via a resistor. (For the V850ES/KF1, independently connect to EVDD or EVSS via a resistor.) Output: Leave open KJ1 All products All products KG1, KJ1 All products
PDL0 to PDL15 AD0 to AD15 PDH0 to PDH5 PDH6, PDH7 AVREF0 AVREF1 AVSS A16 to A21 A22, A23
Note Only for the PD703216Y, 703217Y, and 70F3217Y Remark KG1: V850ES/KG1, KJ1: V850ES/KJ1
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(3/3)
Pin BVDD BVSS EVDD EVSS IC
Note 1
Alternate Function - - - - -
I/O Circuit Type - - - - -
Recommended Connection - - - - Directly connect to EVSS or VSS or pull down with a 10 k resistor. - Directly connect to EVSS or VSS or pull down with a 10 k resistor. - - - - Directly connect to VSS. Leave open.
Target Product KG1, KJ1 KG1, KJ1 All products All products All products
RESET VPP
Note 2
- -
2 -
All products All products
VDD VSS X1 X2 XT1 XT2
- - - - - -
- - - - 16 16
All products All products All products All products All products All products
Notes 1. Only for products with a mask ROM 2. Only for products with flash memory Remark KG1: V850ES/KG1, KJ1: V850ES/KJ1
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2.5 Pin I/O Circuits
(1/2)
Type 2 Type 8-A Pullup enable VDD IN Data P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics Output disable N-ch VDD
P-ch
Type 5 VDD Data
Type 9-C
P-ch P-ch IN/OUT IN N-ch
+ -
Comparator
Output disable
N-ch
AVREF0 (threshold voltage)
Input enable
Input enable
Type 5-A
VDD
Type 10-A Pullup enable VDD Data IN/OUT P-ch
VDD P-ch
Pullup enable Data
P-ch VDD P-ch
Output disable Input enable Type 5-W Pullup enable
N-ch
Open drain Output disable
IN/OUT N-ch
VDD P-ch VDD
Type 10-E Pullup enable VDD Data P-ch
VDD P-ch
Data
P-ch IN/OUT Open drain Output disable
IN/OUT N-ch
Output disable
N-ch
Input enable
Input enable
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(2/2)
Type 10-F Pullup enable VDD Data Open drain Output disable P-ch IN/OUT N-ch RD Input enable Type 12-B Pullup enable AVREF1 Data Output disable P-ch IN/OUT N-ch AVSS AVREF1 P-ch Type 16 Feedback cut-off P-ch P-ch VDD P-ch Data Output disable VSS VDD Type 13-B Mask option IN/OUT N-ch VDD
Medium-voltage input buffer
Input enable P-ch Analog output voltage N-ch XT1 XT2
Type 13-AE
VDD Mask option
Data Output disable N-ch VSS Input enable
IN/OUT
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The CPU of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 is based on the RISC architecture and executes most instructions in one clock cycle by using a 5-stage pipeline control.
3.1 Features
Number of instructions: 83 62.5 ns (@ 16 MHz operation, 4.0 to 5.5 V, using regulator) 100 ns (@ 10 MHz operation: 2.7 to 5.5 V, not using regulator) Memory space Program space: Data space: 64 MB linear 4 GB linear : 2 MB, 2 MB/Total of 2 blocks (V850ES/KG1) : 2 MB, 2 MB, 4 MB, 8 MB/Total of 4 blocks (V850ES/KJ1) General-purpose registers: 32 bits x 32 Internal 32-bit architecture 5-stage pipeline control Multiply/divide instructions Saturated operation instructions 32-bit shift instruction: 1 clock Load/store instruction with long/short format Four types of bit manipulation instructions * SET1 * CLR1 * NOT1 * TST1
Minimum instruction execution time: 50.0 ns (@ 20 MHz operation, 4.5 to 5.5 V, not using regulator)
* Memory block division function: 2 MB, 64 KB/Total of 2 blocks (V850ES/KF1)
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3.2 CPU Register Set
The CPU registers of the V850ES/KF1, V850ES/KG1 and V850ES/KJ1 can be classified into two categories: a general-purpose program register set and a dedicated system register set. All the registers have 32-bit width. For details, refer to the V850ES Architecture User's Manual.
(1) Program register set
31 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 (Element pointer (EP)) (Link pointer (LP)) CTBP DBPC DBPSW CTPC CTPSW PSW (Stack pointer (SP)) (Global pointer (GP)) (Text pointer (TP)) ECR FEPC FEPSW 0 (Zero register) (Assembler-reserved register) 31 EIPC EIPSW
(2) System register set
0 (Interrupt status saving register) (Interrupt status saving register)
(NMI status saving register) (NMI status saving register)
(Interrupt source register)
(Program status word)
(CALLT execution status saving register) (CALLT execution status saving register)
(Exception/debug trap status saving register) (Exception/debug trap status saving register)
(CALLT base pointer)
31 PC (Program counter)
0
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3.2.1 Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are available. All of these registers can be used as a data variable or address variable. However, r0 and r30 are implicitly used by instructions and care must be exercised when using these registers. r0 always holds 0 and is used for operations that use 0 and offset 0 addressing. r30 is used as a base pointer when performing memory access with the SLD and SST instructions. Also, r1, r3 to r5, and r31 are implicitly used by the assembler and C compiler. Therefore, before using these registers, their contents must be saved so that they are not lost, and they must be restored to the registers after the registers have been used. There are cases when r2 is used by the real-time OS. If r2 is not used by the real-time OS, r2 can be used as a variable register. Table 3-1. Program Registers
Name r0 r1 r2 r3 r4 r5 r6 to r29 r30 r31 PC Usage Zero register Assembler-reserved register Always holds 0 Working register for generating 32-bit immediate Operation
Address/data variable register (when r2 is not used by the real-time OS to be used) Stack pointer Global pointer Text pointer Address/data variable register Element pointer Link pointer Program counter Base pointer when memory is accessed Used by compiler when calling function Holds instruction address during program execution Used to generate stack frame when function is called Used to access global variable in data area Register to indicate the start of the text area (area for placing program code)
(2) Program counter (PC) This register holds the address of the instruction under execution. The lower 26 bits of this register are valid, and bits 31 to 26 are fixed to 0. If a carry occurs from bit 25 to bit 26, it is ignored. Bit 0 is fixed to 0, and branching to an odd address cannot be performed.
31 PC Fixed to 0
26 25 Instruction address under execution
10 0 After reset 00000000H
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3.2.2 System register set System registers control the status of the CPU and hold interrupt information. Read from and write to system registers are performed by setting the system register numbers shown below with the system register load/store instructions (LDSR, STSR instructions). Table 3-2. System Register Numbers
Register No. System Register Name Operand Specification Enabled LDSR Instruction 0 1 2 3 4 5 6 to 15 16 17 18 19 20 21 to 31 Interrupt status saving register (EIPC)Note 1 Interrupt status saving register (EIPSW) NMI status saving register (FEPC)
Note 1 Note 1
STSR Instruction Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes No
Yes Yes Yes Yes No Yes No Yes Yes Yes Yes
Note 2
NMI status saving register (FEPSW) Interrupt source register (ECR) Program status word (PSW)
Note 1
Reserved numbers for future function expansion (The operation is not guaranteed if accessed.) CALLT execution status saving register (CTPC) CALLT execution status saving register (CTPSW) Exception/debug trap status saving register (DBPC) Exception/debug trap status saving register (DBPSW) CALLT base pointer (CTBP) Reserved numbers for future function expansion (The operation is not guaranteed if accessed.)
Note 2
Yes No
Notes 1. Since only one set of these registers is available, the contents of this register must be saved by the program when multiple interrupt servicing is enabled. 2. Can be accessed only during DBTRAP instruction execution. Caution Even if bit 0 of EIPC, FEPC, or CTPC is set to (1) by the LDSR instruction, bit 0 is ignored during return with the RETI instruction following interrupt servicing (because bit 0 of PC is fixed to 0). If setting a value to EIPC, FEPC, and CTPC, set an even number (bit 0 = 0).
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(1) Interrupt status saving registers (EIPC, EIPSW) There are two interrupt status saving registers, EIPC and EIPSW. Upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (PC) are saved to EIPC and the contents of the program status word (PSW) are saved to EIPSW (upon occurrence of a non-maskable interrupt (NMI), the contents are saved to the NMI status saving registers (FEPC, FEPSW)). The address of the next instruction following the instruction executed when a software exception or maskable interrupt occurs is saved to EIPC, except for some instructions. The current PSW contents are saved to EIPSW. Since there is only one set of interrupt status saving registers, the contents of these registers must be saved by the program when multiple interrupt servicing is enabled. Bits 31 to 26 of EIPC and bits 31 to 8 of EIPSW are reserved (fixed to 0) for future function expansion.
31 EIPC
26 25 (PC contents)
0 After reset 0xxxxxxxH (x: Undefined) 87 (PSW contents) 0 After reset 000000xxH (x: Undefined)
000000
31 EIPSW
000000000000000000000000
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(2) NMI status saving registers (FEPC, FEPSW) There are two NMI status saving registers, FEPC and FEPSW. Upon occurrence of a non-maskable interrupt (NMI), the contents of the program counter (PC) are saved to FEPC and the contents of the program status word (PSW) are saved to FEPSW. The address of the next instruction following the instruction executed when a non-maskable interrupt occurs is saved to FEPC, except for some instructions. The current PSW contents are saved to FEPSW. Since there is only one set of NMI status saving registers, the contents of these registers must be saved by the program when multiple interrupt servicing is performed. Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved (fixed to 0) for future function expansion.
31 FEPC
26 25 (PC contents)
0 After reset 0xxxxxxxH (x: Undefined) 87 (PSW contents) 0 After reset 000000xxH (x: Undefined)
000000
31 FEPSW
000000000000000000000000
(3) Interrupt source register (ECR) Upon occurrence of an interrupt or an exception, the interrupt source register (ECR) holds the source of an interrupt or an exception. The value held by ECR is the exception code coded for each interrupt source. This register is a read-only register, and thus data cannot be written to it using the LDSR instruction.
31 ECR FECC
16 15 EICC
0 After reset 00000000H
Bit position 31 to 16 15 to 0
Bit name FECC EICC
Description Non-maskable interrupt (NMI) exception code Exception, maskable interrupt exception code
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(4) Program status word (PSW) A program status word (PSW) is a collection of flags that indicate the program status (instruction execution result) and the CPU status. When the contents of this register are changed using the LDSR instruction, the new contents become valid immediately following completion of the LDSR instruction execution. However, if the ID flag is set to 1, interrupt request acknowledgement during LDSR instruction execution is prohibited. Bits 31 to 8 are reserved (fixed to 0) for future function expansion. (1/2)
31 PSW RFU 876543210 NP EP ID SAT CY OV S Z After reset 00000020H
Bit position 31 to 8 7
Flag name RFU NP Reserved field. Fixed to 0.
Description
Indicates that non-maskable interrupt (NMI) servicing is in progress. This flag is set to 1 when an NMI request is acknowledged, and disables multiple interrupts. 0: NMI servicing not in progress 1: NMI servicing in progress Indicates that exception processing is in progress. This flag is set to 1 when an exception occurs. Moreover, interrupt requests can be acknowledged even when this bit is set. 0: Exception processing not in progress 1: Exception processing in progress Indicates whether maskable interrupt request acknowledgment is enabled. 0: Interrupt enabled 1: Interrupt disabled Indicates that the result of executing a saturated operation instruction has overflowed and that the calculation result is saturated. Since this is a cumulative flag, it is set to 1 when the result of a saturated operation instruction becomes saturated, and it is not cleared to 0 even if the operation results of successive instructions do not become saturated. This flag is neither set nor cleared when arithmetic operation instructions are executed. 0: Not saturated 1: Saturated Indicates whether carry or borrow occurred as the result of an operation. 0: No carry or borrow occurred 1: Carry or borrow occurred Indicates whether overflow occurred during an operation. 0: No overflow occurred 1: Overflow occurred. Indicates whether the result of an operation is negative. 0: Operation result is positive or 0. 1: Operation result is negative. Indicates whether operation result is 0. 0: Operation result is not 0. 1: Operation result is 0.
6
EP
5
ID
4
SATNote
3
CY
2
OVNote
1
SNote
0
Z
Remark Note is explained on the following page.
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(2/2) Note During saturated operation, the saturated operation results are determined by the contents of the OV flag and S flag. The SAT flag is set to 1 only when the OV flag is set to 1 during saturated operation.
Operation result status SAT Maximum positive value exceeded Maximum negative value exceeded Positive (maximum value not exceeded) Negative (maximum value not exceeded) 1 1 1 1 Flag status OV 0 1 0 1 S Saturated operation result 7FFFFFFFH 80000000H Actual operation result
Holds value 0 before operation
(5) CALLT execution status saving registers (CTPC, CTPSW) There are two CALLT execution status saving registers, CTPC and CTPSW. When the CALLT instruction is executed, the contents of the program counter (PC) are saved to CTPC, and the program status word (PSW) contents are saved to CTPSW. The contents saved to CTPC consist of the address of the next instruction after the CALLT instruction. The current PSW contents are saved to CTPSW. Bits 31 to 26 CTPC and bits 31 to 8 of CTPSW are reserved (fixed to 0) for future function expansion.
31 CTPC
26 25 (PC contents)
0 After reset 0xxxxxxxH (x: Undefined) 87 (PSW contents) 0 After reset 000000xxH (x: Undefined)
000000
31 CTPSW
000000000000000000000000
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(6) Exception/debug trap status saving registers (DBPC, DBPSW) There are two exception/debug trap status saving registers, DBPC and DBPSW. Upon occurrence of an exception trap or debug trap, the contents of the program counter (PC) are saved to DBPC, and the program status word (PSW) contents are saved to DBPSW. The contents saved to DBPC consist of the address of the next instruction after the instruction executed when an exception trap or debug trap occurs. The current PSW contents are saved to DBPSW. Bits 31 to 26 of DBPC and bits 31 to 8 of DBPSW are reserved (fixed to 0) for future function expansion.
31 DBPC
26 25 (PC contents)
0 After reset 0xxxxxxxH (x: Undefined) 87 (PSW contents) 0 After reset 000000xxH (x: Undefined)
000000
31 DBPSW
000000000000000000000000
(7) CALLT base pointer (CTBP) The CALLT base pointer (CTBP) is used to specify table addresses and generate target addresses (bit 0 is fixed to 0). Bits 31 to 26 are reserved (fixed to 0) for future function expansion.
31 CTBP
26 25 (Base address)
0 0 After reset 0xxxxxxxH (x: Undefined)
000000
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3.3 Operation Modes
The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 have the following operating modes. (1) Normal operating mode After the system has been released from the reset state, the pins related to the bus interface are set to the port mode, execution branches to the reset entry address of the internal ROM, and instruction processing is started. An external device can be connected to the external memory area by setting the PMCDH, PMCDL, PMCCM, PMCCS, and PMCCT registers to the control mode via software. (2) Flash memory programming mode
PD70F3210, 70F3210Y: V850ES/KF1 PD70F3214, 70F3214Y: V850ES/KG1 PD70F3217, 70F3217Y: V850ES/KJ1
The internal flash memory can be written or erased when 10 V 0.3 V is applied to the VPP pin.
VPP 0 100.3 V VDD Operating Mode Normal operation mode Flash memory programming mode Setting prohibited
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3.4 Address Space
3.4.1 CPU address space The CPU of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 uses a 32-bit architecture and supports up to 4 GB of linear address space (data space) during operand addressing (data access). When addressing instruction addresses, a linear address space (program space) of up to 64 MB is supported. However, both the program and data spaces include areas whose use is prohibited. For details, refer to Figure 3-2. Figure 3-1 shows the CPU address space. Figure 3-1. CPU Address Space
CPU address space FFFFFFFFH
Data area (4 GB linear)
04000000H 03FFFFFFH Program area (64 MB linear) 00000000H
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3.4.2 Image Up to 16 MB of external memory area in a linear address space (program area) of up to 16 MB, internal ROM area, and internal RAM area are supported for instruction address addressing. During operand addressing (data access), up to 4 GB of linear address space (data space) is supported. However, the 4 GB address space is viewed as 64 images of a 64 MB physical address space. In other words, the same 64 MB physical address space is accessed regardless of the value of bits 31 to 26. Figure 3-2. Address Space Image
Image 63
4 GB * * *
Data space On-chip peripheral I/O area Image 1
Program space Reserved area
Internal RAM area
Internal RAM area Access-prohibited area 64 MB Access-prohibited area 64 MB Image 0 External memory area
External memory area 16 MB Internal ROM area (external memory) Internal ROM area (external memory)
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3.4.3 Wraparound of CPU address space (1) Program space Of the 32 bits of the program counter (PC), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. Even if a carry or borrow occurs from bit 25 to bit 26 as a result of branch address calculation, the higher 6 bits ignore this and remain 0. Therefore, the lower-limit address of the program space, 00000000H, and the upper-limit address, 03FFFFFFH, are contiguous addresses, and the program space is wrapped around at the boundary of these addresses. Caution No instructions can be fetched from the 4 KB area of 03FFF000H to 03FFFFFFH because this area is an on-chip peripheral I/O area. Therefore, do not execute any branch operation instructions in which the destination address will reside in any part of this area.
03FFFFFEH 03FFFFFFH
Program space
(+) direction 00000000H 00000001H Program space
(-) direction
(2) Data space The result of an operand address calculation that exceeds 32 bits is ignored. Therefore, the lower-limit address of the data space, address 00000000H, and the upper-limit address, FFFFFFFFH, are contiguous addresses, and the data space is wrapped around at the boundary of these addresses.
FFFFFFFEH FFFFFFFFH
Data space
(+) direction 00000000H 00000001H Data space
(-) direction
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3.4.4 Memory map The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 have reserved areas as shown below. Figure 3-3. Data Memory Map (Physical Addresses)
3FFFFFFH (80 KB) 3FEC000H 3FEBFFFH
On-chip peripheral I/O area (4 KB)
3FFFFFFH 3FFF000H 3FFEFFFH
Internal RAM area (60 KB)
Access-prohibited area
3FFF000H 3FFEFFFH Access-prohibited area
1000000H 0FFFFFFH
3FEC000H
External memory areaNote 1 (8 MB)
CS3
0800000H 07FFFFFH
External memory areaNote 1 (4 MB) 0400000H 03FFFFFH 0200000H 01FFFFFH 0000000H External memory area (2 MB)Note 2
CS2
01FFFFFH CS1 External memory area (1 MB)Note 2 Internal ROM areaNote 3 (1 MB) 0000000H
0100000H 00FFFFFH
(2 MB)
CS0
Notes 1. Only for the V850ES/KJ1. Access-prohibited area for the V850ES/KF1 and V850ES/KG1. 2. 64 KB for the V850ES/KF1 3. Fetch access and read access to addresses 0000000H to 00FFFFFH is performed for the internal ROM area, but in the case of data write access, it is performed for an external memory area.
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Figure 3-4. Program Memory Map
03FFFFFFH 03FFF000H 03FFEFFFH
Access-prohibited area (Program fetch disabled area)
Internal RAM area (60 KB) 3FF0000H 3FEFFFFH Access-prohibited area (Program fetch disabled area) 01000000H 00FFFFFFH
External memory areaNote 1 (8 MB)
CS3
00800000H 007FFFFFH External memory areaNote 1 (4 MB) 00400000H 003FFFFFH 00200000H 001FFFFFH 00100000H 000FFFFFH 00000000H
CS2
External memory area (2 MB)Note 2 External memory area (1 MB)Note 2 Internal ROM area (1 MB)
CS1
CS0
Notes 1. Only for the V850ES/KJ1. Access-prohibited area for the V850ES/KF1 and V850ES/KG1. 2. 64 KB for the V850ES/KF1 Remark Instruction execution for external memory areas without branching from the internal ROM area to an external memory area can be performed.
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3.4.5 Areas (1) Internal ROM area An area of 1 MB from 0000000H to 00FFFFFH is reserved for the internal ROM area. (a) Internal ROM/internal flash memory (128 KB) A 128 KB area from 0000000H to 001FFFFH is provided in the following products. Addresses 0020000H to 00FFFFFH are an access-prohibited area. * V850ES/KF1 (PD703210, 703210Y, 70F3210, 70F3210Y) * V850ES/KG1 (PD703214, 703214Y, 70F3214, 70F3214Y) * V850ES/KJ1 (PD703217, 703217Y, 70F3217, 70F3217Y) Figure 3-5. Internal ROM/Internal Flash Memory Area (128 KB)
00FFFFFH
Access-prohibited area
0020000H 001FFFFH Internal ROM area 0000000H
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(b) Internal ROM/internal flash memory area (96 KB) A 96 KB area from 0000000H to 0017FFFH is provided in the following products. Addresses 0018000H to 00FFFFFH are an access-prohibited area. * V850ES/KF1 (PD703209, 703209Y) * V850ES/KG1 (PD703213, 703213Y) * V850ES/KJ1 (PD703216, 703216Y) Figure 3-6. Internal ROM Area (96 KB)
00FFFFFH
Access-prohibited area
0018000H 0017FFFH Internal ROM area 0000000H
(c) Internal ROM/internal flash memory area (64 KB) A 64 KB area from 000000H to 000FFFFH is provided in the following products. Addresses 0010000 to 00FFFFFH are an access-prohibited area. * V850ES/KF1 (PD703208, 703208Y) * V850ES/KG1 (PD703212, 703212Y) Figure 3-7. Internal ROM Area (64 KB)
00FFFFFH
Access-prohibited area
0010000H 000FFFFH Internal ROM area 0000000H
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* Interrupt/exception table The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 increase the interrupt response speed by assigning handler addresses corresponding to interrupts/exceptions. This group of handler addresses is called an interrupt/exception table. This table is located in the internal ROM area. When an interrupt/exception request is acknowledged, execution jumps to the handler address and the program written in that memory is executed. Table 3-3 lists the interrupt/exception sources and the corresponding addresses. Table 3-3. Interrupt/Exception Table
Start Address of Interrupt/ Exception Table 00000000H 00000010H 00000020H 00000030H 00000040H 00000050H 00000060H 00000080H 00000090H 000000A0H 000000B0H 000000C0H 000000D0H 000000E0H 000000F0H 00000100H 00000110H 00000120H 00000130H 00000140H 00000150H 00000160H 00000170H 00000180H 00000190H 000001A0H Interrupt/ Exception Source RESET NMI INTWDT1 INTWDT2 TRAP0n (n = 0 to F) TRAP1n (n = 0 to F) ILGOP/DBG0 INTWDTM1 INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTTM000 INTTM001 INTTM010 INTTM011 INTTM50 INTTM51 INTCSI00 INTCSI01 INTSRE0 INTSR0 INTST0
2
Start Address of Interrupt/ Exception Table 000001B0H 000001C0H 000001D0H 000001E0H 000001F0H 00000200H 00000210H 00000220H 00000230H 00000240H 00000250H 00000260H 00000270H 00000280H 00000290H 000002A0H 000002B0H 000002C0H 000002D0H 000002E0H 000002F0H 00000300H 00000310H 00000320H 00000330H 00000340H
Interrupt/ Exception Source INTSRE1 INTSR1 INTST1 INTTMH0 INTTMH1 INTCSIA0 INTIIC0Note 1 INTAD INTKR INTWTI INTWT INTBRG INTTM020Note 2 INTTM021Note 2 INTTM030Note 2 INTTM031Note 2 INTCSIA1Note 2 INTTM040Note 3 INTTM041Note 3 INTTM050Note 3 INTTM051Note 3 INTCSI02Note 3 INTSRE2Note 3 INTSR2Note 3 INTST2Note 3 INTIIC1Note 4
Notes 1. Only for products with an I C bus 2. Only for the V850ES/KG1 and V850ES/KJ1 3. Only for the V850ES/KJ1 4. Only for the PD703216Y, 703217Y, and 70F3217Y
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(2) Internal RAM area An area of 60 KB maximum from 3FF0000H to 3FFEFFFH is reserved for the internal RAM area. (a) Internal RAM (6 KB) A 6 KB area from 3FFD800H to 3FFEFFFH is provided as physical internal RAM. Addresses 3FF0000H to 3FFD7FFH are an access-prohibited area. * V850ES/KF1 (PD703210, 703210Y, 70F3210, 70F3210Y) * V850ES/KG1 (PD703214, 703214Y, 70F3214, 70F3214Y) * V850ES/KJ1 (PD703216, 703216Y, 703217, 703217Y, 70F3217, 70F3217Y) Figure 3-8. Internal RAM Area (6 KB)
3FFEFFFH Internal RAM (6 KB) 3FFD800H 3FFD7FFH
Access-prohibited area
3FF0000H
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(b) Internal RAM area (4 KB) A 4 KB area from 3FFE000H to 3FFEFFFH is provided as physical internal RAM in the following products. Addresses 3FF0000H to 3FFDFFFH are an access-prohibited area. * V850ES/KF1 (PD703218, 703218Y, 703219, 703219Y) * V850ES/KG1 (PD703212, 703212Y, 703213, 70F3213Y) Figure 3-9. Internal RAM Area (4 KB)
3FFEFFFH Internal RAM area (4 KB) 3FFE000H 3FFDFFFH
Access-prohibited area
3FF0000H
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(3) On-chip peripheral I/O area A 4 KB area from 3FFF000H to 3FFFFFFH is reserved as the on-chip peripheral I/O area. Figure 3-10. On-Chip Peripheral I/O Area
3FFFFFFH
On-chip peripheral I/O area (4 KB) 3FFF000H
Peripheral I/O registers assigned with functions such as on-chip peripheral I/O operation mode specification and state monitoring are mapped to the on-chip peripheral I/O area. Program fetches are not allowed in this area. Cautions 1. If word access of a register is attempted, halfword access to the word area is performed twice, first for the lower bits, then for the higher bits, ignoring the lower 2 address bits. 2. If a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits become undefined if the access is a read operation. If a write access is performed, only the data in the lower 8 bits is written to the register. 3. Addresses that are not defined as registers are reserved for future expansion. If these addresses are accessed, the operation is undefined and not guaranteed. (4) External memory area 15 MB (0100000H to 0FFFFFFH) are provided as the external memory area. For details, refer to CHAPTER 5 BUS CONTROL FUNCTION.
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3.4.6 Peripheral I/O registers (1/12)
Operable Bit Address FFFFF004H FFFFF004H FFFFF005H FFFFF006H FFFFF008H FFFFF00AH FFFFF00CH FFFFF00EH FFFFF024H FFFFF024H FFFFF025H FFFFF026H FFFFF028H FFFFF02AH FFFFF02CH FFFFF02EH FFFFF044H FFFFF044H FFFFF045H FFFFF046H FFFFF048H FFFFF04AH FFFFF04CH FFFFF066H FFFFF06EH FFFFF100H FFFFF100H FFFFF101H FFFFF102H FFFFF102H FFFFF103H FFFFF104H FFFFF104H FFFFF105H FFFFF110H FFFFF112H FFFFF114H FFFFF116H Port DL register Port DL register L Port DL register H Port DH register Port CS register Port CT register Port CM register Port CD register Port DL mode register Port DL mode register L Port DL mode register H Port DH mode register Port CS mode register Port CT mode register Port CM mode register Port CD mode register Port DL mode control register Port DL mode control register L P ort DL mode control register H Port DH mode control register Port CS mode control register Port CT mode control register Port CM mode control register Bus size configuration register System wait control register Interrupt mask register 0 Interrupt mask register 0L Interrupt mask register 0H Interrupt mask register 1 Interrupt mask register 1L Interrupt mask register 1H Interrupt mask register 2 Interrupt mask register 2L Interrupt mask register 2H Interrupt control register Interrupt control register Interrupt control register Interrupt control register Function Register Name Symbol PDL PDLL PDLH PDH PCS PCT PCM PCD
Note 2 Note 1
R/W 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 16
After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined FFFFH FFH FFH FFH FFH FFH FFH FFH 0000H 00H 00H 00H 00H 00H 00H 5555H 77H FFFFH FFH FFH FFFFH FFH FFH FFFFH FFH FFH 47H 47H 47H 47H
PMDL PMDLL PMDLH PMDH PMCS PMCT PMCM PMCD
Note 2 Note 1
PMCDL PMCDLL PMCDLH PMCDH PMCCS PMCCT PMCCM BSC VSWC IMR0 IMR0L IMR0H IMR1 IMR1L IMR1H IMR2
Note 1 Note 1
IMR2L
Note 1
IMR2HNote 1 WDT1IC PIC0 PIC1 PIC2
Notes 1. Only for the V850ES/KG1 and V850ES/KJ1 2. Only for the V850ES/KJ1
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Operable Bit Address FFFFF118H FFFFF11AH FFFFF11CH FFFFF11EH FFFFF120H FFFFF122H FFFFF124H FFFFF126H FFFFF128H FFFFF12AH FFFFF12CH FFFFF12EH FFFFF130H FFFFF132H FFFFF134H FFFFF136H FFFFF138H FFFFF13AH FFFFF13CH FFFFF13EH FFFFF140H FFFFF142H FFFFF144H FFFFF146H FFFFF148H FFFFF14AH FFFFF14CH FFFFF14EH FFFFF150H FFFFF152H FFFFF154H FFFFF156H FFFFF158H FFFFF15AH FFFFF15CH FFFFF15EH FFFFF160H FFFFF162H FFFFF164H Function Register Name Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register
2
Symbol PIC3 PIC4 PIC5 PIC6 TM0IC00 TM0IC01 TM0IC10 TM0IC11 TM5IC0 TM5IC1 CSI0IC0 CSI0IC1 SREIC0 SRIC0 STIC0 SREIC1 SRIC1 STIC1 TMHIC0 TMHIC1 CSIAIC0 IICIC0 ADIC KRIC WTIIC WTIC BRGIC TM0IC20
Note 2 Note 1
R/W 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 16
After Reset 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H
TM0IC21Note 2 TM0IC30 TM0IC31 CSIAIC1
Note 2
Note 2
Note 2
TM0IC40
Note 3
TM0IC41Note 3 TM0IC50
Note 3
TM0IC51 CSI0IC2 SREIC2
Note 3
Note 3
Note 3
SRIC2Note 3
Notes 1. Only for products with an I C bus 2. Only for the V850ES/KG1 and V850ES/KJ1 3. Only for the V850ES/KJ1
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Operable Bit Address FFFFF166H FFFFF168H FFFFF1FAH FFFFF1FCH FFFFF1FEH FFFFF200H FFFFF201H FFFFF202H FFFFF203H FFFFF204H FFFFF205H FFFFF280H FFFFF282H FFFFF284H FFFFF300H FFFFF400H FFFFF402H FFFFF406H FFFFF406H FFFFF407H FFFFF408H FFFFF40AH FFFFF40CH FFFFF40CH FFFFF40DH FFFFF40EH FFFFF40EH FFFFF40EH FFFFF40FH FFFFF410H FFFFF412H FFFFF412H FFFFF413H FFFFF420H FFFFF422H FFFFF426H FFFFF426H FFFFF427H Function Register Name Interrupt control register Interrupt control register In-service priority register Command register Power save control register A/D converter mode register Analog input channel specification register Power fail comparison mode register Power fail comparison threshold register A/D conversion result register A/D conversion result register H D/A conversion value setting register 0 D/A conversion value setting register 1 D/A converter mode register Key return mode register Port 0 register Port 1 register Port 3 register Port 3 register L Port 3 register H Port 4 register Port 5 register Port 6 register Port 6 register L Port 6 register H Port 7 register Port 7 register Port 7 register L Port 7 register H Port 8 register Port 9 register Port 9 register L Port 9 register H Port 0 mode register Port 1 mode register Port 3 mode register Port 3 mode register L Port 3 mode register H Symbol STIC2Note 1 IICIC1 ISPR PRCMD PSC ADM ADS PFM PFT ADCR ADCRH DACS0 DACS1
Note 3 Note 2
R/W 1 R/W R/W R W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W 8 16
After Reset 47H 47H 00H Undefined 00H 00H 00H 00H 00H Undefined Undefined 00H 00H 00H 00H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined FFH FFH FFFFH FFH FFH
Note 3
DAMNote 3 KRM P0 P1 P3 P3L P3H P4 P5 P6
Note 1 Note 3
R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W
P6LNote 1 P6H P7 P7
Note 1
Note 4
Note 1
P7L
Note 1
P7HNote 1 P8 P9 P9L P9H PM0 PM1Note 3 PM3 PM3L PM3H
Note 1
Notes 1. Only for the V850ES/KJ1 2. Only for the PD703216Y, 703217Y, and 70F3217Y 3. Only for the V850ES/KG1 and V850ES/KJ1 4. Only for the V850ES/KF1 and V850ES/KG1
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Operable Bit Address FFFFF428H FFFFF42AH FFFF42CH FFFFF42CH FFFFF42DH FFFFF430H FFFFF432H FFFFF432H FFFFF433H FFFFF440H FFFFF446H FFFFF446H FFFFF447H FFFFF448H FFFFF44AH FFFFF44CH FFFFF44CH FFFFF44DH FFFFF450H FFFFF452H FFFFF452H FFFFF453H FFFFF466H FFFFF46AH FFFFF46DH FFFFF470H FFFFF472H FFFFF472H FFFFF473H FFFFF484H FFFFF488H FFFFF48AH FFFFF580H FFFFF581H FFFFF582H FFFFF583H FFFFF590H FFFFF591H FFFFF592H FFFFF593H Function Register Name Port 4 mode register Port 5 mode register Port 6 mode register Port 6 mode register L Port 6 mode register H Port 8 mode register Port 9 mode register Port 9 mode register L Port 9 mode register H Port 0 mode control register Port 3 mode control register Port 3 mode control register L Port 3 mode control register H Port 4 mode control register Port 5 mode control register Port 6 mode control register Port 6 mode control register L Port 6 mode control register H Port 8 mode control register Port 9 mode control register Port 9 mode control register L Port 9 mode control register H Port 3 function control register Port 5 function control register Port 6 function control register Port 8 function control register Port 9 function control register Port 9 function control register L Port 9 function control register H Data wait control register 0 Address wait control register Bus cycle control register 8-bit timer H mode register 0 8-bit timer H carrier control register 0 8-bit timer H compare register 00 8-bit timer H compare register 01 8-bit timer H mode register 1 8-bit timer H carrier control register 1 8-bit timer H compare register 10 8-bit timer H compare register 11 Symbol PM4 PM5 PM6
Note
R/W 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 16
After Reset FFH FFH FFFFH FFH FFH FFH FFFFH FFH FFH 00H 0000H 00H 00H 00H 00H 0000H 00H 00H 00H 0000H 00H 00H 00H 00H 00H 00H 0000H 00H 00H 7777H FFFFH AAAAH 00H 00H 00H 00H 00H 00H 00H 00H
PM6LNote PM6H PM8 PM9 PM9L PM9H PMC0 PMC3 PMC3L PMC3H PMC4 PMC5 PMC6
Note Note
Note
R/W R/W R/W R/W R/W R/W R/W R/W R/W
PMC6L
Note
PMC6H
Note
PMC8Note PMC9 PMC9L PMC9H PFC3 PFC5 PFC6H PFC8 PFC9 PFC9L PFC9H DWC0 AWC BCC TMHMD0 TMCYC0 CMP00 CMP01 TMHMD1 TMCYC1 CMP10 CMP11
Note
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note
Note Only for the V850ES/KJ1
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Operable Bit Address FFFFF5C0H FFFFF5C0H FFFFF5C1H FFFFF5C2H FFFFF5C2H FFFFF5C3H FFFFF5C4H FFFFF5C4H FFFFF5C5H FFFFF5C6H FFFFF5C6H FFFFF5C7H FFFFF600H FFFFF602H FFFFF604H FFFFF606H FFFFF607H FFFFF608H FFFFF609H FFFFF610H FFFFF612H FFFFF614H FFFFF616H FFFFF617H FFFFF618H FFFFF619H FFFFF620H FFFFF622H FFFFF624H FFFFF626H FFFFF627H FFFFF628H FFFFF629H FFFFF630H FFFFF632H FFFFF634H FFFFF636H FFFFF637H FFFFF638H FFFFF639H Function Register Name 16-bit timer counter 5 8-bit timer counter 50 8-bit timer counter 51 16-bit timer compare register 5 8-bit timer compare register 50 8-bit timer compare register 51 Timer clock selection register 5 Timer clock selection register 50 Timer clock selection register 51 16-bit timer mode control register 5 8-bit timer mode control register 50 8-bit timer mode control register 51 16-bit timer counter 00 16-bit timer capture/compare register 000 16-bit timer capture/compare register 001 16-bit timer mode control register 00 Prescaler mode register 00 Capture/compare control register 00 16-bit timer output control register 00 16-bit timer counter 01 16-bit timer capture/compare register 010 16-bit timer capture/compare register 011 16-bit timer mode control register 01 Prescaler mode register 01 Capture/compare control register 01 16-bit timer output control register 01 16-bit timer counter 02 16-bit timer capture/compare register 020 16-bit timer capture/compare register 021 16-bit timer mode control register 02 Prescaler mode register 02 Capture/compare control register 02 16-bit timer output control register 02 16-bit timer counter 03 16-bit timer capture/compare register 030 16-bit timer capture/compare register 031 16-bit timer mode control register 03 Prescaler mode register 03 Capture/compare control register 03 16-bit timer output control register 03 Symbol TM5 TM50 TM51 CR5 CR50 CR51 TCL5 TCL50 TCL51 TMC5 TMC50 TMC51 TM00 CR000 CR001 TMC00 PRM00 CRC00 TOC00 TM01 CR010 CR011 TMC01 PRM01 CRC01 TOC01 TM02
Note
R/W 1 R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W 8 16
After Reset 0000H 00H 00H 0000H 00H 00H 0000H 00H 00H 0000H 00H 00H 0000H 0000H 0000H 00H 00H 00H 00H 0000H 0000H 0000H 00H 00H 00H 00H 0000H 0000H 0000H 00H 00H 00H 00H 0000H 0000H 0000H 00H 00H 00H 00H
CR020
Note
CR021Note TMC02
Note
PRM02 CRC02 TOC02
Note
Note
Note
TM03Note CR030 CR031
Note
Note
TMC03
Note
PRM03
Note
CRC03Note TOC03
Note
Note Only for the V850ES/KG1 and V850ES/KJ1
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Operable Bit Address FFFFF640H FFFFF642H FFFFF644H FFFFF646H FFFFF647H FFFFF648H FFFFF649H FFFFF650H FFFFF652H FFFFF654H FFFFF656H FFFFF657H FFFFF658H FFFFF659H FFFFF680H FFFFF6C0H FFFFF6C1H FFFFF6C2H FFFFF6D0H FFFFF6D1H FFFFF6E0H FFFFF6E2H FFFFF6E4H FFFFF6E5H FFFFF6F0H FFFFF6F2H FFFFF6F4H FFFFF6F5H FFFFF802H FFFFF806H FFFFF820H FFFFF828H FFFFF840H FFFFF840H FFFFF842H FFFFF844H FFFFF844H FFFFF846H FFFFF848H FFFFF848H FFFFF84AH Function Register Name 16-bit timer counter 04 16-bit timer capture/compare register 040 16-bit timer capture/compare register 041 16-bit timer mode control register 04 Prescaler mode register 04 Capture/compare control register 04 16-bit timer output control register 04 16-bit timer counter 05 16-bit timer capture/compare register 050 16-bit timer capture/compare register 051 16-bit timer mode control register 05 Prescaler mode register 05 Capture/compare control register 05 16-bit timer output control register 05 Watch timer operation mode register Oscillation stabilization time select register Watchdog timer clock selection register Watchdog timer mode register 1 Watchdog timer mode register 2 Watchdog timer enable register Real-time output buffer register L0 Real-time output buffer register H0 Real-time output port mode register 0 Real-time output port control register 0 Real-time output buffer register L1 Real-time output buffer register H1 Real-time output port mode register 1 Real-time output port control register 1 System status register PLL control register Power save mode register Processor clock control register Correction address register 0 Correction address register 0L Correction address register 0H Correction address register 1 Correction address register 1L Correction address register 1H Correction address register 2 Correction address register 2L Correction address register 2H Symbol TM04Note CR040 CR041
Note
R/W 1 R R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 16 43
After Reset 0000H 0000H 0000H 00H 00H 00H 00H 0000H 0000H 0000H 00H 00H 00H 00H 00H 01H 00H 00H 67H 9AH 00H 00H 00H 00H 00H 00H 00H 00H 00H 01H 00H 03H 00000000H 0000H 0000H 00000000H 0000H 0000H 00000000H 0000H 0000H
Note
TMC04Note PRM04 CRC04 TOC04 TM05
Note
Note
Note
Note
CR050Note CR051
Note
TMC05
Note
PRM05 CRC05
Note
Note
TOC05Note WTM OSTS WDCS WDTM1 WDTM2 WDTE RTBL0 RTBH0 RTPM0 RTPC0 RTBL1
Note
RTBH1
Note
RTPM1 RTPC1 SYS
Note
Note
PLLCTL PSMR PCC CORAD0 CORAD0L CORAD0H CORAD1 CORAD1L CORAD1H CORAD2 CORAD2L CORAD2H
Note Only for the V850ES/KJ1
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Operable Bit Address FFFFF84CH FFFFF84CH FFFFF84EH FFFFF880H FFFFF8B0H FFFFF8B1H FFFFFA00H FFFFFA02H FFFFFA03H FFFFFA04H FFFFFA05H FFFFFA06H FFFFFA07H FFFFFA10H FFFFFA12H FFFFFA13H FFFFFA14H FFFFFA15H FFFFFA16H FFFFFA17H FFFFFA20H FFFFFA22H FFFFFA23H FFFFFA24H FFFFFA25H FFFFFA26H FFFFFA27H FFFFFC00H FFFFFC13H FFFFFC20H FFFFFC33H FFFFFC40H FFFFFC42H FFFFFC46H FFFFFC48H FFFFFC4AH Function Register Name Correction address register 3 Correction address register 3L Correction address register 3H Correction control register Prescaler mode register Prescaler compare register Asynchronous serial interface mode register 0 Receive buffer register 0 Asynchronous serial interface status register 0 Transmit buffer register 9 Asynchronous serial interface transmission status register 0 Clock selection register 0 Baud rate generator control register 0 Asynchronous serial interface mode register 1 Receive buffer register 1 Asynchronous serial interface status register 1 Transmit buffer register 1 Asynchronous serial interface transmission status register 1 Clock selection register 1 Baud rate generator control register 1 Asynchronous serial interface mode register 2 Receive buffer register 2 Asynchronous serial interface status register 2 Transmit buffer register 2 Asynchronous serial interface transmission status register 2 Clock selection register 2 Baud rate generator control register 2 External interrupt falling edge specification register 0 External interrupt falling edge specification register 9H External interrupt rising edge specification register 0 External interrupt rising edge specification register 9H Pull-up resistor option register 0 Pull-up resistor option register 1 Pull-up resistor option register 3 Pull-up resistor option register 4 Pull-up resistor option register 5 Symbol CORAD3 CORAD3L CORAD3H CORCN PRSM PRSCM ASIM0 RXB0 ASIS0 TXB0 ASIF0 CKSR0 BRGC0 ASIM1 RXB1 ASIS1 TXB1 ASIF1 CKSR1 BRGC1 ASIM2 RXB2
Note 1
R/W 1 R/W R/W R/W R/W R/W R/W R/W R R R/W R R/W R/W R/W R R R/W R R/W R/W R/W R R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 16 43
After Reset 00000000H 0000H 0000H 00H 00H 00H 01H FFH 00H FFH 00H 00H FFH 01H FFH 00H FFH 00H 00H FFH 01H FFH 00H FFH 00H 00H FFH 00H 00H 00H 00H 00H 00H 00H 00H 00H
Note 1
ASIS2
Note 1
TXB2Note 1 ASIF2Note 1 CKSR2Note 1 BRGC2 INTF0 INTF9H INTR0 INTR9H PU0 PU1 PU3 PU4 PU5
Note 2 Note 1
Notes 1. Only for the V850ES/KJ1 2. Only for the V850ES/KG1 and V850ES/KJ1
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Operable Bit Address FFFFFC4CH Function Register Name Pull-up resistor option register 6 Symbol PU6Note PU6L
Note
R/W 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R R R/W R/W R/W R/W R/W R/W R R R/W R/W R R R/W R/W R/W R/W R/W R/W 8 16
After Reset 0000H 00H 00H 00H 0000H 00H 00H 00H 00H 00H 0000H 00H 00H 00H 00H 00H 00H 0000H 00H 0000H 00H 0000H 00H 0000H 00H 00H 0000H 00H 00H 0000H 00H 0000H 00H 0000H 00H 0000H 00H 00H 0000H 00H 00H
FFFFFC4CH Pull-up resistor option register 6L FFFFFC4DH Pull-up resistor option register 6H FFFFFC50H FFFFFC52H FFFFFC52H FFFFFC53H FFFFFC67H FFFFFC68H FFFFFC6AH FFFFFC6CH Pull-up resistor option register 8 Pull-up resistor option register 9 Pull-up resistor option register 9L Pull-up resistor option register 9H Port 3 function register H Port 4 function register Port 5 function register Port 6 function register
PU6H
Note
PU8Note PU9 PU9L PU9H PF3H PF4 PF5 PF6
Note
FFFFFC6CH Port 6 function register L FFFFFC6DH Port 6 function register H FFFFFC70H FFFFFC73H FFFFFD00H FFFFFD01H FFFFFD02H FFFFFD02H FFFFFD04H FFFFFD04H FFFFFD06H FFFFFD06H FFFFFD08H FFFFFD08H FFFFFD0AH FFFFFD0AH FFFFFD10H FFFFFD11H FFFFFD12H FFFFFD12H FFFFFD14H FFFFFD14H FFFFFD16H FFFFFD16H FFFFFD18H FFFFFD18H FFFFFD1AH FFFFFD1AH FFFFFD20H FFFFFD21H Port 8 function register Port 9 function register H Clocked serial interface mode register 00 Clocked serial interface clock selection register 0 Clocked serial interface receive buffer register 0 Clocked serial interface receive buffer register 0L Clocked serial interface transmit buffer register 0 Clocked serial interface transmit buffer register 0L Clocked serial interface read-only receive buffer register 0 Clocked serial interface read-only receive buffer register 0L Clocked serial interface first-stage transmit buffer register 0
PF6L
Note
PF6H
Note
PF8Note PF9H CSIM00 CSIC0 SIRB0 SIRB0L SOTB0 SOTB0L SIRBE0 SIRBE0L SOTBF0
Clocked serial interface first-stage transmit buffer register 0L SOTBF0L Serial I/O shift register 0 Serial I/O shift register 0L Clocked serial interface mode register 01 Clocked serial interface clock selection register 1 Clocked serial interface receive buffer register 1 Clocked serial interface receive buffer register 1L Clocked serial interface transmit buffer register 1 Clocked serial interface transmit buffer register 1L Clocked serial interface read-only receive buffer register 1 Clocked serial interface read-only receive buffer register 1L Clocked serial interface first-stage transmit buffer register 1 SIO00 SIO00L CSIM01 CSIC1 SIRB1 SIRB1L SOTB1 SOTB1L SIRBE1 SIRBE1L SOTBF1
Clocked serial interface first-stage transmit buffer register 1L SOTBF1L Serial I/O shift register 1 Serial I/O shift register 1L Clocked serial interface mode register 02 Clocked serial interface clock selection register 2 SIO01 SIO1L CSIM02Note CSIC2Note
Note Only for the V850ES/KJ1
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Operable Bit Address FFFFFD22H FFFFFD22H FFFFFD24H FFFFFD24H FFFFFD26H FFFFFD26H FFFFFD28H FFFFFD28H FFFFFD2AH FFFFFD2AH FFFFFD40H FFFFFD41H FFFFFD42H FFFFFD43H FFFFFD44H FFFFFD45H FFFFFD46H FFFFFD47H FFFFFD50H FFFFFD51H FFFFFD52H FFFFFD53H FFFFFD54H FFFFFD55H FFFFFD56H FFFFFD57H FFFFFD80H FFFFFD82H FFFFFD83H FFFFFD84H FFFFFD85H FFFFFD86H FFFFFD8AH FFFFFD90H FFFFFD92H FFFFFD93H FFFFFD94H FFFFFD95H Function Register Name Clocked serial interface receive buffer register 2 Clocked serial interface receive buffer register 2L Clocked serial interface transmit buffer register 2 Clocked serial interface transmit buffer register 2L Clocked serial interface read-only receive buffer register 2 Clocked serial interface read-only receive buffer register 2L Clocked serial interface first-stage transmit buffer register 2 Symbol SIRB2Note 1 SIRB2L SOTB2
Note 1
R/W 1 R R R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R R/W R/W R/W R/W R R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W 8 16
After Reset 0000H 00H 0000H 00H 0000H 00H 0000H 00H 00H 0000H 00H 00H 00H 03H 00H 00H 00H 00H 00H 00H 00H 03H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H
Note 1
SOTB2LNote 1 SIRBE2Note 1 SIRBE2L SOTBF2
Note 1
Note 1
Clocked serial interface first-stage transmit buffer register 2L SOTBF2L Serial I/O shift register 2 Serial I/O shift register 2L Serial operation mode specification register 0 Serial status register 0 Serial trigger register 0 Division value selection register 0 SIO02Note 1 SIO02L
Note 1
Note 1
CSIMA0 CSIS0 CSIT0 BRGCA0
Automatic data transfer address point specification register 0 ADTP0 Automatic data transfer interval specification register 0 Serial I/O shift register A0 Automatic data transfer address count register 0 Serial operation mode specification register 1 Serial status register 1 Serial trigger register 1 Division value selection register 1 ADTI0 SIOA0 ADTC0 CSIMA1Note 2 CSIS1Note 2 CSIT1
Note 2
BRGCA1
Note 2
Automatic data transfer address point specification register 1 ADTP1 Automatic data transfer interval specification register 1 Serial I/O shift register A1 Automatic data transfer address count register 1 IIC shift register 0 IIC control register 0 Slave address register 0 IIC clock selection register 0 IIC function expansion register 0 IIC status register 0 IIC flag register 0 IIC shift register 1 IIC control register 1 Slave address register 1 IIC clock selection register 1 IIC function expansion register 1
Note 2
ADTI1Note 2 SIOA1
Note 2
ADTC1 IIC0
Note 2
Note 3
IICC0
Note 3
SVA0Note 3 IICCL0 IICX0
Note 3
Note 3
IICS0 IICF0
Note 3
Note 3
IIC1Note 4 IICC01 SVA01
Note 4
Note 4
IICCL01 IICX1
Note 4
Note 4
Notes 1. Only for the V850ES/KJ1 2. Only for the V850ES/KG1 and V850ES/KJ1 3. Only for products with an I C bus 4. Only for the PD703216Y, 703217Y, and 70F3217Y
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Address FFFFFD96H FFFFFD9AH FFFFFE00H FFFFFE00H FFFFFE01H FFFFFE02H FFFFFE02H FFFFFE03H FFFFFE04H FFFFFE04H FFFFFE05H FFFFFE06H FFFFFE06H FFFFFE07H FFFFFE08H FFFFFE08H FFFFFE09H FFFFFE0AH FFFFFE0AH FFFFFE0BH FFFFFE0CH FFFFFE0CH FFFFFE0DH FFFFFE0EH FFFFFE0EH FFFFFE0FH FFFFFE10H FFFFFE10H FFFFFE11H FFFFFE12H FFFFFE12H FFFFFE13H FFFFFE14H FFFFFE14H FFFFFE15H FFFFFE16H FFFFFE16H FFFFFE17H FFFFFE18H FFFFFE18H FFFFFE19H Function Register Name IIC status register 1 IIC flag register 1 CSIA0 buffer RAM 0 CSIA0 buffer RAM 0L CSIA0 buffer RAM 0H CSIA0 buffer RAM 1 CSIA0 buffer RAM 1L CSIA0 buffer RAM 1H CSIA0 buffer RAM 2 CSIA0 buffer RAM 2L CSIA0 buffer RAM2H CSIA0 buffer RAM 3 CSIA0 buffer RAM 3L CSIA0 buffer RAM 3H CSIA0 buffer RAM 4 CSIA0 buffer RAM 4L CSIA0 buffer RAM 4H CSIA0 buffer RAM 5 CSIA0 buffer RAM 5L CSIA0 buffer RAM 5H CSIA0 buffer RAM 6 CSIA0 buffer RAM 6L CSIA0 buffer RAM 6H CSIA0 buffer RAM 7 CSIA0 buffer RAM 7L CSIA0 buffer RAM 7H CSIA0 buffer RAM 8 CSIA0 buffer RAM 8L CSIA0 buffer RAM 8H CSIA0 buffer RAM 9 CSIA0 buffer RAM 9L CSIA0 buffer RAM 9H CSIA0 buffer RAM A CSIA0 buffer RAM AL CSIA0 buffer RAM AH CSIA0 buffer RAM B CSIA0 buffer RAM BL CSIA0 buffer RAM BH CSIA0 buffer RAM C CSIA0 buffer RAM CL CSIA0 buffer RAM CH Symbol IICS01Note IICF1
Note
R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Operable Bit 1 8 16
After Reset 00H 00H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
CSIA0B0 CSIA0B0L CSIA0B0H CSIA0B1 CSIA0B1L CSIA0B1H CSIA0B2 CSIA0B2L CSIA0B2H CSIA0B3 CSIA0B3L CSIA0B3H CSIA0B4 CSIA0B4L CSIA0B4H CSIA0B5 CSIA0B5L CSIA0B5H CSIA0B6 CSIA0B6L CSIA0B6H CSIA0B7 CSIA0B7L CSIA0B7H CSIA0B8 CSIA0B8L CSIA0B8H CSIA0B9 CSIA0B9L CSIA0B9H CSIA0BA CSIA0BAL CSIA0BAH CSIA0BB CSIA0BBL CSIA0BBH CSIA0BC CSIA0BCL CSIA0BCH
Note Only for the PD703216Y, 703217Y, and 70F3217Y
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Address FFFFFE1AH FFFFFE1AH FFFFFE1BH FFFFFE1CH FFFFFE1CH FFFFFE1DH FFFFFE1EH FFFFFE1EH FFFFFE1FH FFFFFE20H FFFFFE20H FFFFFE21H FFFFFE22H FFFFFE22H FFFFFE23H FFFFFE24H FFFFFE24H FFFFFE25H FFFFFE26H FFFFFE26H FFFFFE27H FFFFFE28H FFFFFE28H FFFFFE29H FFFFFE2AH FFFFFE2AH FFFFFE2BH FFFFFE2CH FFFFFE2CH FFFFFE2DH FFFFFE2EH FFFFFE2EH FFFFFE2FH FFFFFE30H FFFFFE30H FFFFFE31H FFFFFE32H FFFFFE32H FFFFFE33H FFFFFE34H FFFFFE34H FFFFFE35H Function Register Name CSIA0 buffer RAM D CSIA0 buffer RAM DL CSIA0 buffer RAM DH CSIA0 buffer RAM E CSIA0 buffer RAM EL CSIA0 buffer RAM EH CSIA0 buffer RAM F CSIA0 buffer RAM FL CSIA0 buffer RAM FH CSIA1 buffer RAM 0 CSIA1 buffer RAM 0L CSIA1 buffer RAM 0H CSIA1 buffer RAM 1 CSIA1 buffer RAM 1L CSIA1 buffer RAM 1H CSIA1 buffer RAM 2 CSIA1 buffer RAM 2L CSIA1 buffer RAM 2H CSIA1 buffer RAM 3 CSIA1 buffer RAM 3L CSIA1 buffer RAM 3H CSIA1 buffer RAM 4 CSIA1 buffer RAM 4L CSIA1 buffer RAM 4H CSIA1 buffer RAM 5 CSIA1 buffer RAM 5L CSIA1 buffer RAM 5H CSIA1 buffer RAM 6 CSIA1 buffer RAM 6L CSIA1 buffer RAM 6H CSIA1 buffer RAM 7 CSIA1 buffer RAM 7L CSIA1 buffer RAM 7H CSIA1 buffer RAM 8 CSIA1 buffer RAM 8L CSIA1 buffer RAM 8H CSIA1 buffer RAM 9 CSIA1 buffer RAM 9L CSIA1 buffer RAM 9H CSIA1 buffer RAM A CSIA1 buffer RAM AL CSIA1 buffer RAM AH Symbol CSIA0BD CSIA0BDL CSIA0BDH CSIA0BE CSIA0BEL CSIA0BEH CSIA0BF CSIA0BFL CSIA0BFH CSIA1B0
Note
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Operable Bit 1 8 16
After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
CSIA1B0LNote R/W CSIA1B0H CSIA1B1
Note
R/W R/W
Note
CSIA1B1LNote R/W CSIA1B1H CSIA1B2
Note
R/W R/W
Note
CSIA1B2LNote R/W CSIA1B2H CSIA1B3
Note
R/W R/W
Note
CSIA1B3LNote R/W CSIA1B3H
Note
R/W R/W R/W R/W R/W R/W R/W R/W R/W
CSIA1B4Note CSIA1B4L
Note
CSIA1B4H
Note
CSIA1B5Note CSIA1B5L
Note
CSIA1B5H
Note
CSIA1B6Note CSIA1B6L
Note
CSIA1B6HNote R/W CSIA1B7
Note
R/W R/W
CSIA1B7L
Note
CSIA1B7HNote R/W CSIA1B8
Note
R/W
CSIA1B8LNote R/W CSIA1B8H CSIA1B9
Note
R/W R/W
Note
CSIA1B9LNote R/W CSIA1B9H CSIA1BA
Note
R/W R/W
Note
CSIA1BALNote R/W CSIA1BAH
Note
R/W
Note Only for the V850ES/KG1 and V850ES/KJ1
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Address FFFFFE36H FFFFFE36H FFFFFE37H FFFFFE38H FFFFFE38H FFFFFE39H FFFFFE3AH FFFFFE3AH FFFFFE3BH FFFFFE3CH FFFFFE3CH FFFFFE3DH FFFFFE3EH FFFFFE3EH FFFFFE3FH FFFFFFBEH Function Register Name CSIA1 buffer RAM B CSIA1 buffer RAM BL CSIA1 buffer RAM BH CSIA1 buffer RAM C CSIA1 buffer RAM CL CSIA1 buffer RAM CH CSIA1 buffer RAM D CSIA1 buffer RAM DL CSIA1 buffer RAM DH CSIA1 buffer RAM E CSIA1 buffer RAM EL CSIA1 buffer RAM EH CSIA1 buffer RAM F CSIA1 buffer RAM FL CSIA1 buffer RAM FH External bus interface mode control register Symbol CSIA1BBNote CSIA1BBL
Note
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Operable Bit 1 8 16
After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 00H
CSIA1BBH
Note
CSIA1BCNote CSIA1BCL
Note
CSIA1BCH
Note
CSIA1BDNote CSIA1BDL
Note
CSIA1BDHNote R/W CSIA1BE
Note
R/W R/W
CSIA1BEL
Note
CSIA1BEHNote R/W CSIA1BF
Note
R/W
CSIA1BFLNote R/W CSIA1BFH EXIMC
Note Note
R/W R/W
Note Only for the V850ES/KG1 and V850ES/KJ1
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3.4.7 Special registers Special registers are registers that prevent invalid data from being written when an inadvertent program loop occurs. The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 have the following three special registers. * Power save control register (PSC) * Processor clock control register (PCC) * Watchdog timer mode register (WDTM1) Moreover, there is also a command register (PRCMD), which is a protection register for write operations to the special registers that prevents the application system from unexpectedly stopping due to an inadvertent program loop. Write access to the special registers is performed with a special sequence and illegal store operations are notified to the system status register (SYS). (1) Setting data to special registers Setting data to a special registers is done in the following sequence. <1> <2> <3> Prepare the data to be set to the special register in a general-purpose register. Write the data prepared in step <1> to the PRCMD register. Write the setting data to the special register (using following instructions). * Store instruction (ST/SST instruction) * Bit manipulation instruction (SET1/CLR1/NOT1 instruction) <4> to <8> Insert NOP instructions (5 instructions)
Note
.
[Description Example] When using PSC register (standby mode setting) ST.B r11,PSMR[r0] ; PSMR register setting (IDLE, STOP mode setting) <1> MOV 0x02,r10 <2> ST.B r10,PRCMD[r0] <3> ST.B r10,PSC[r0] <4> NOP <5> NOP <6> NOP <7> NOP <8> NOP
Note Note Note Note Note
; PRCMD register write ; PSC register setting ; Dummy instruction ; Dummy instruction ; Dummy instruction ; Dummy instruction ; Dummy instruction
(next instruction) No special sequence is required to read special registers. Note When switching to the IDLE mode or the STOP mode (STP bit of PSC register = 1), 5 NOP instructions must be inserted immediately after switching is performed.
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Cautions 1. Interrupts are not acknowledged for the store instruction for the PRCMD register. This is because continuous execution of store instructions by the program in steps <3> and <4> above is assumed. If another instruction is placed between step <3> and <4>, the above sequence may not be realized when an interrupt is acknowledged for that instruction, which may cause malfunction. 2. The data written to the PRCMD register is dummy data, but use the same register as the general-purpose register used for setting data to the special register (step <4>) when writing to the PRCMD register (step <3>). The same applies to when using a generalpurpose register for addressing. (2) Command register (PRCMD) The PRCMD register is an 8-bit register used to prevent data from being written to registers that may have a large influence on the system, possibly causing the application system to unexpectedly stop, when an inadvertent program loop occurs. Only the first write operation to the special register following the execution of a previously executed write operation to the PRCMD register, is valid. As a result, register values can be overwritten only using a preset sequence, preventing invalid write operations. This register can only be written in 8-bit units (if it is read, an undefined value is returned).
After reset: Undefined 7 PRCMD REG7 6
W
Address: FFFFF1FCH 5 REG5 4 REG4 3 REG3 2 REG2 1 REG1 0 REG0
REG6
(3) System status register (SYS) This register is allocated with status flags showing the operating state of the entire system. This register can be read or written in 8-bit or 1-bit units.
After reset: 00H
R/W
Address: FFFFF802H <>
SYS
0
0
0
0
0
0
0
PRERR
PRERR 0 1
Detection of protection error Protection error has not occurred Protection error has occurred
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The operation conditions of the PRERR flag are described below. (a) Set conditions (PRERR = 1) (i) When a write operation to the special register takes place without write operation being performed to the PRCMD register (when step <4> is performed without performing step <3> as described in 3.4.7 (1) Setting data to special registers). (ii) When a write operation (including bit manipulation instruction) to an on-chip peripheral I/O register other than a special register is performed following write to the PRCMD register (when <4> in 3.4.7 (1) Setting data to special registers is not a special register). Remark Regarding the special registers other than the WDTM register (PCC and PSC registers), even if on-chip peripheral I/O register read (except bit manipulation instruction) (internal RAM access, etc.) is performed in between write to the PRCMD register and write to a special register, the PRERR flag is not set and setting data can be written to the special register. (b) Clear conditions (PRERR = 0) (i) When 0 is written to the PRERR flag of the SYS register (ii) When system reset is performed Cautions 1. If 0 is written to the PRERR bit of the SYS register that is not a special register immediately following write to the PRCMD register, the PRERR bit becomes 0 (write priority). 2. If data is written to the PRCMD register that is not a special register immediately following write to the PRCMD register, the PRERR bit becomes 1.
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3.4.8 Cautions Be sure to set the following register before using the V850ES/KF1, V850ES/KG1 and V850ES/KJ1. * System wait control register (VSWC) After setting the VSWC register, set the other registers as required. When using an external bus, set the VSWC register and then set the various pins to the control mode by setting the port-related registers. (1) System wait control register (VSWC) The system wait control register (VSWC) controls the bus access wait time for the on-chip peripheral I/O registers. Access to the on-chip peripheral I/O register lasts 3 clocks (during no wait), but in the V850ES/KF1, V850ES/KG1 and V850ES/KJ1, waits are required according to the operation frequency. Set the values shown below to the VSWC register according to the operation frequency that is used. This register can be read or written in 8-bit units (Address: FFFFF06EH, After reset: 77H).
Operation Conditions REGC = VDD = 5 V10%, In PLL mode (OSC = 2 to 5 MHz) REGC = Capacity, VDD = 4.0 to 5.5 V REGC = VDD = 2.7 to 4.0 V Other than above (REGC = VDD = 4.0 to 5.5 V) Operation Frequency (fCLK) 8 MHz fCLK < 16.6 MHz 16.6 MHz fCLK 20 MHz 2 MHz fCLK < 8.3 MHz 8.3 MHz fCLK 16 MHz fCLK 16 MHz VSWC Setting 00H 01H 00H 01H 00H
(2) Access to special on-chip peripheral I/O register This product has two types of internal system buses. One type is for the CPU bus and the other is for the peripheral bus to interface with low-speed peripheral hardware. Since the CPU bus clock and peripheral bus clock are asynchronous, if a conflict occurs during access between the CPU and peripheral hardware, illegal data may be passed unexpectedly. Therefore, when accessing peripheral hardware that may cause a conflict, the number of access cycles is changed so that the data is received/passed correctly in the CPU. As a result, the CPU does not shift to the next instruction processing and enters the wait status. When this wait status occurs, the number of execution clocks of the instruction is increased by the number of wait clocks. Note this with caution when performing real-time processing. When accessing a special on-chip peripheral I/O register, additional waits may be required further to the waits set by the VSWC register. The access conditions at that time and the method to calculate the number of waits to be inserted (number of CPU clocks) are shown below.
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Peripheral Function Watchdog timer 1 (WDT1)
Register Name WDTM1 Write
Access 2 to 4
k
{(1/fx) x 2/((2 + m)/fCPU)} + 1 fx: Oscillation frequency Watchdog timer 2 (WDT2) 16-bit timer/event counters 00 to 05 (TM00 to TM05)Note 1 Clocked serial interfaces 0 and 1 with automatic transmit/receive function (CSIA0, CSIA1)Note 3 WDTM2 TMC00 to TMC05 CSIA0B0 to CSIA0BF, CSIA1B0 to CSIA1BF Write Read-modify-write WriteNote 2 (when performing continuous write) 3 (fixed) 1 (fixed) A wait occurs during write 0 to 18
{(1/fSCKA) x 5 - (4 + m)/fCPU)}/{((2 + m)/fCPU)} However, 1 wait if fCPU = fxx if the CKSAn1 and CKSAn0 bits of the CSISn register are 0. fSCKA: CSIA selection clock frequency IICS0, IICS1 ASIS0 to ASIS2 Read Read 1 (fixed) 1 (fixed) 1
I2C0Note 4, I2C1Note 5 Asynchronous serial interfaces 0 to 2 (UART0 to UART2)Note 6 Real-time output functions 0 and 1 (RTO0, RTO1)Note 7
RTBL0, RTBL1, RTBH0, RTBH1
Write (when bits RTPOE0 and RTPOE1 of RTPC0 and RTPC1 registers = 0) Write Read
A/D converter
ADM, ADS, PFM, PFT ADCR, ADCRH
1 to 5 1 to 5
{(1/fAD) x 2/(2 + m)/fCPU } + 1 fAD: A/D selection clock frequency
Number of waits to be added = (2 + m) x k [clocks] Notes 1. TM02 and TM03 are available only in the V850ES/KG1 and V850ES/KJ1; TM04 and TM05 are available only in the V850ES/KJ1. 2. If fetched from the on-chip RAM, the number of waits is as shown above. If fetched from the external memory, the number of waits may be fewer than the number shown above. The effect of the external memory access cycle differs depending on the wait settings, etc. However, the number of waits above is the maximum value. 3. CSIA1 is available only in the V850ES/KG1 and V850ES/KJ1. 4. I C0 is available only in the products with I C. 5. I C1 is available only in the V850ES/KJ1 (PD703216Y, 703217Y, and 70F3217Y). 6. UART2 is available only in the V850ES/KJ1. 7. RTO1 is available only in the V850ES/KJ1. Caution When the CPU operates on the subclock and no clock is input to the X1 pin, do not access a register in which a wait occurs using an access method that causes a wait. If a wait occurs, it can only be released by a reset.
2 2 2
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Remark In the calculation for the number of waits:
fCPU: CPU clock frequency
m:
Set value of bits 2 to 0 of the VSWC register
fCLK: Internal system clock When fCLK < 16.6 MHz: 0 When fCLK 16.6 MHz: 1 The digits below the decimal point are truncated if less than (1/fCPU)/(2 + m) or rounded up if larger than (1/fCPU)/(2 + m) when multiplied by (1/fCPU).
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4.1 Features
4.1.1 V850ES/KF1 Input-only ports: 8 pins I/O ports: 59 pins Shared with I/O pins of other peripheral functions Input/output can be specified in 1-bit units 4.1.2 V850ES/KG1 Input-only ports: 8 pins I/O ports: 76 pins Shared with I/O pins of other peripheral functions Input/output can be specified in 1-bit units 4.1.3 V850ES/KJ1 Input-only ports: 16 pins I/O ports: 112 pins Shared with I/O pins of other peripheral functions Input/output can be specified in 1-bit units
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4.2 Basic Port Configuration
4.2.1 V850ES/KF1 The V850ES/KF1 incorporates a total of 67 I/O port pins consisting of ports 0, 3 to 5, 7, 9, CM, CS, CT, and DL (including 8 input-only port pins). The port configuration is shown below.
P00 Port 0 P06 P30 Port 3 P35 P38 P39 P40 Port 4 P42 P50 Port 5 P55 P70 Port 7 P77
P90 P91 P96 P99 P913 P915 PCM0 Port CM PCM3 PCS0 PCS1 PCT0 PCT1 PCT4 PCT6 PDL0 Port DL PDL15 Port CT Port CS Port 9
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4.2.2 V850ES/KG1 The V850ES/KG1 incorporates a total of 84 I/O port pins consisting of ports 0, 1, 3 to 5, 7, 9, CM, CS, CT, DH, and DL (including 8 input-only port pins). The port configuration is shown below.
P00 Port 0 P06 Port 1 P10 P11 P30 Port 3 P39 P40 Port 4 P42 P50 Port 5 P55 P70 Port 7 P77
P90 Port 9 P915 PCM0 Port CM PCM3 PCS0 PCS1 PCT0 PCT1 PCT4 PCT6 PDH0 Port DH PDH5 PDL0 Port DL PDL15 Port CT Port CS
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4.2.3 V850ES/KJ1 The V850ES/KJ1 incorporates a total of 128 I/O port pins consisting of ports 0, 1, 3 to 9, CD, CM, CS, CT, DH, and DL (including 16 input-only port pins). The port configuration is shown below.
P00 Port 0 P06 Port 1 P10 P11 P30 Port 3 P39 P40 Port 4 P42 P50 Port 5 P55 P60 Port 6 P615 P70 Port 7 P715 Port 8 P80 P81
P90 Port 9 P915 PCD0 Port CD PCD3 PCM0 Port CM PCM5 PCS0 Port CS PCS7 PCT0 Port CT PCT7 PDH0 Port DH PDH7 PDL0 Port DL PDL15
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4.3 Port Configuration
Table 4-1. Port Configuration (V850ES/KF1)
Item Control register Ports Pull-up resistors Configuration Port mode registers PMn (n = 0, 3 to 5, 7, 9, CM, CS, CT, DL) Pull-up resistor option registers PUn (n = 0, 3 to 5, 9) I/O: 67 pins Software control: 31
Table 4-2. Port Configuration (V850ES/KG1)
Item Control register Ports Pull-up resistors Configuration Port mode registers PMn (n = 0, 1, 3 to 5, 7, 9, CM, CS, CT, DH, DL) Pull-up resistor option registers PUn (n = 0, 1, 3 to 5, 9) I/O: 84 pins Software control: 40
Table 4-3. Port Configuration (V850ES/KJ1)
Item Control register Ports Pull-up resistors Configuration Port mode registers PMn (n = 0, 1, 3 to 9, CD, CM, CS, CT, DH, DL) Pull-up resistor option registers PUn (n = 0, 1, 3 to 6, 8, 9) I/O: 128 pins Software control: 56
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4.3.1 Port 0 Input/output for port 0 can be controlled in 1-bit units. The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 have the same number of I/O port pins for port 0.
Product V850ES/KF1 V850ES/KG1 V850ES/KJ1 I/O Port Pin Count 7-bit I/O port 7-bit I/O port 7-bit I/O port
(1) Port 0 functions Port input/output data can be specified in 1-bit units. Specification is made by the port 0 register (P0). Port input/output can be specified in 1-bit units. Specification is made by the port 0 mode register (PM0). Port mode/control mode (alternate function) can be specified in 1-bit units. Specification is made by the port 0 mode control register (PMC0). On-chip pull-up resistor connection can be specified in 1-bit units. Specification is made by pull-up resistor option register 0 (PU0). The valid edge of external interrupts (alternate function) can be specified in 1-bit units. The falling edge and the rising edge of the external interrupt are specified by falling edge specification register 0 (INTF0) and rising edge specification register 0 (INTR0), respectively. Port 0 includes the following alternate functions. Table 4-4. Alternate-Function Pins of Port 0
Pin Name Port 0 P00 P01 P02 P03 P04 P05 P06 Alternate Function TOH0 TOH1 NMI INTP0 INTP1 INTP2 INTP3 Analog noise elimination I/O I/O PULLNote Yes Remark -
Note Software pull-up function
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(2) Registers (a) Port 0 register (P0) The port 0 register (P0) is an 8-bit register that controls pin level read and output level write. This register can be read/written in 8-bit or 1-bit units.
After Reset: Undefined
R/W
Address: FFFFF400H
P0
0
P06
P05
P04
P03
P02
P01
P00
P0n 0 1 Output 0 Output 1
Control of output data (in output mode) (n = 0 to 6)
Remark In input mode:
When read, port 0 (P0) returns the current pin level. When written to, the data written to P0 is written. This has no influence on the input pins.
In output mode: When read, port 0 (P0) returns the P0 value. When written to, the value is written to P0 and the written value is immediately output.
(b) Port 0 mode register (PM0) This is an 8-bit register that specifies the input mode/output mode. This register can be read/written in 8-bit or 1-bit units.
After Reset: FFH
R/W
Address: FFFFF420H
PM0
1
PM06
PM05
PM04
PM03
PM02
PM01
PM00
PM0n 0 1 Output mode Input mode
Control of I/O mode
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(c) Port 0 mode control register (PMC0) This is an 8-bit register that specifies the port mode or control mode. This register can be read/written in 8-bit or 1-bit units.
After Reset: 00H
R/W
Address: FFFFF440H
PMC0
0
PMC06
PMC05
PMC04
PMC03
PMC02
PMC01
PMC00
PMC06 0 1 PMC05 0 1 PMC04 0 1 PMC03 0 1 PMC02 0 1 PMC01 0 1 PMC00 0 1 I/O port TOH0 output I/O port TOH1 output I/O port NMI input I/O port INTP0 input I/O port INTP1 input I/O port INTP2 input I/O port INTP3 input
Specification of P06 pin operation mode
Specification of P05 pin operation mode
Specification of P04 pin operation mode
Specification of P03 pin operation mode
Specification of P02 pin operation mode
Specification of P01 pin operation mode
Specification of P00 pin operation mode
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(d) Pull-up resistor option register 0 (PU0) This is an 8-bit register that specifies the connection of an on-chip pull-up resistor. This register can be read/written in 8-bit or 1-bit units.
After Reset: 00H
R/W
Address: FFFFFC40H
PU0
0
PU06
PU05
PU04
PU03
PU02
PU01
PU00
PU0n 0 1
Control of on-chip pull-up resistor connection (n = 0 to 6) Not connected Connected
(e) External interrupt falling edge specification register 0 (INTF0) This is an 8-bit register that specifies the falling edge as the detection edge for the external interrupt pin. This register can be read/written in 8-bit or 1-bit units. Caution When switching from the external interrupt function (alternate function) to the port function, edge detection may be performed. Therefore, set the port mode after setting INTF0n bit = INTR0n bit = 0.
After Reset: 00H
R/W
Address: FFFFFC00H
INTF0
0
INTF06
INTF05
INTF04
INTF03
INTF02
0
0
Remark
For specification of the valid edge, refer to Table 4-5.
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(f)
External interrupt rising edge specification register 0 (INTR0) This is an 8-bit register that specifies the rising edge as the detection edge for the external interrupt pin. This register can be read/written in 8-bit or 1-bit units. Caution When switching from the external interrupt function (alternate function) to the port function, edge detection may be performed. Therefore, set the port mode after setting INTF0n bit = INTR0n bit = 0.
After Reset: 00H
R/W
Address: FFFFFC20H
INTR0
0
INTR06
INTR05
INTR04
INTR03
INTR02
0
0
Remark
For specification of the valid edge, refer to Table 4-5.
Table 4-5. Valid Edge Specification
INTF0n 0 0 1 1 INTR0n 0 1 0 1 No edge detection Rising edge Falling edge Both edges Valid edge specification (n = 2 to 6)
Remark n = 2: Control of NMI pin n = 3 to 6: Control of INTP0 to INTP3 pins
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(3) Block diagram (port 0) Figure 4-1. Block Diagram of P00 and P01
EVDD WRPU PU0 PU0n WRPMC PMC0 PMC0n WRPM PM0
Internal bus
P-ch
PM0n
Selector
WRPORT
TOHn output Output latch (P0n)
P00/TOH0, P01/TOH1
Selector
Address
RD
Remarks 1. PU0: PM0: RD: WR: 2. n = 0, 1
Pull-up resistor option register 0 Port 0 mode register Port 0 read signal Port 0 write signal
PMC0: Port 0 mode control register
Selector
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Figure 4-2. Block Diagram of P02 to P06
EVDD WRPU PU0 PU0n WRINTR INTR0 INTR0n WRINTF INTF0 INTF0n WRPMC PMC0
Internal bus
P-ch
PMC0n WRPM PM0 PM0n
WRPORT Output latch (P0n) P02/NMI, P03/INTP0, P04/INTP1, P05/INTP2, P06/INTP3
Selector
Address
RD NMI, INTP0 to INTP3 input Noise eliminator Edge detector
Remarks 1. PU0: PM0:
Pull-up resistor option register 0 Port 0 mode register
PMC0: Port 0 mode control register INTF0: External interrupt falling edge specification register 0 INTR0: External interrupt rising edge specification register 0 RD: WR: Port 0 read signal Port 0 write signal
2. n = 2 to 6
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4.3.2 Port 1 Port 1 can control input/output in 1-bit units. The number of I/O port pins for port 1 differs according to the product.
Product V850ES/KF1 V850ES/KG1 V850ES/KJ1 2-bit I/O port 2-bit I/O port I/O Port Pin Count -
(1) Port 1 functions (V850ES/KG1, V850ES/KJ1) Port input/output data can be specified in 1-bit units. Specification is made by the port 1 register (P1). Port input/output can be specified in 1-bit units. Specification is made by the port 1 mode register (PM1). On-chip pull-up resistor connection can be specified in 1-bit units. Specification is made by pull-up resistor option register 1 (PU1). Port 1 includes the following alternate functions. Table 4-6. Alternate-Function Pins of Port 1 (V850ES/KG1, V850ES/KJ1)
Pin Name Port 1 P10 P11 Alternate Function ANO0 ANO1 I/O I/O PULLNote Yes Remark -
Note Software pull-up function
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(2) Registers (a) Port 1 register (P1) Port 1 register (P1) is an 8-bit register that controls pin level read and output level write. This register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KG1, V850ES/KJ1
After Reset: Undefined R/W Address: FFFFF402H
P1
0
0
0
0
0
0
P11
P10
P1n 0 1 Outputs 0 Outputs 1
Control of output data (in output mode) (n = 0, 1)
Remark In input mode:
When read, port 1 (P1) returns the current pin level. When written to, the data written to P1 is written. This has no influence on the input pins.
In output mode: When read, port 1 (P1) returns the P1 value. When written to, the value is written to P1 and the written value is immediately output.
(b) Port 1 mode register (PM1) This is an 8-bit register that specifies the input mode/output mode. This register can be read/written in 8-bit or 1-bit units. Caution When used as the ANO0 and ANO1 pins, set PM1 = FFH at one time.
(i) V850ES/KG1, V850ES/KJ1
After Reset: FFH R/W Address: FFFFF422H
PM1
1
1
1
1
1
1
PM11
PM10
PM1n 0 1 Output mode Input mode
Control of I/O mode (n = 0, 1)
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(c) Pull-up resistor option register 1 (PU1) This is an 8-bit register that specifies the connection of an on-chip pull-up resistor. This register can be read/written in 8-bit or 1-bit units.
(i) 850ES/KG1, V850ES/KJ1
After Reset: 00H R/W Address: FFFFFC42H
PU1
0
0
0
0
0
0
PU11
PU10
PU1n 0 1
Control of on-chip pull-up resistor connection (n = 0, 1) Not connected Connected
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(3) Block diagram (port 1) Figure 4-3. Block Diagram of P10 and P11
EVDD WRPU PU1 PU1n WRPM PM1 PM1n WRPORT P-ch
Internal bus
Output latch (P1n)
P10/ANO0, P11/ANO1
Selector
Address
RD ANOn output
Selector
P-ch N-ch
Remarks 1. PM1: Port 1 mode register RD: Port 1 read signal WR: Port 1 write register 2. n = 0, 1
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4.3.3 Port 3 Port 3 can control input/output in 1-bit units. The number of I/O port pins differs according to the product.
Product V850ES/KF1 V850ES/KG1 V850ES/KJ1 I/O Port Pin Count 8-bit I/O port 10-bit I/O port 10-bit I/O port
(1) Port 3 functions (V850ES/KF1, V850ES/KG1, V850ES/KJ1) Port input/output data can be specified in 1-bit units. Specification is made by the port 3 register (P3). Port input/output can be specified in 1-bit units. Specification is made by the port 3 mode register (PM3). Port mode/control mode (alternate functions) can be specified in 1-bit units. Specification is made by the port 3 mode control register (PMC3). N-ch open-drain specification can be done in 1-bit units. Specification is made by the port 3 function register H (PF3H). Control mode 1/control mode 2 specification can be done in 1-bit units. Specification is made by the port 3 function control register (PFC3). On-chip pull-up resistor connection can be specified in 1-bit units. Specification is made by pull-up resistor option register 3 (PU3).
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Port 3 includes the following alternate functions. Table 4-7. Alternate-Function Pins of Port 3 (V850ES/KF1)
Pin Name Port 3 P30 P31 P32 P33 P34 P35 P38 P39 Alternate Function TXD0 RXD0 ASCK0 TI000/TO00 TI001 TI010/TO01 SDA0Note 2 SCL0
Note 2
I/O I/O
PULLNote 1 Yes
Remark -
NoNote 3
N-ch open-drain output
Notes 1. Software pull-up function 2. Only for products with an I C bus 3. An on-chip pull-up resistor can be provided by a mask option (only for the mask ROM version of the V850ES/KF1). Table 4-8. Alternate-Function Pins of Port 3 (V850ES/KG1, V850ES/KJ1)
Pin Name Port 3 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 SDA0
Note 3
2
Alternate Function TXD0 RXD0 ASCK0 TI000/TO00 TI001 TI010/TO01 - - I/O
I/O
PULLNote Yes
Remark -
NoNote 2
N-ch open-drain output
SCL0 Note 3
Notes 1. Software pull-up function 2. An on-chip pull-up resistor can be provided by a mask option (only for the mask ROM versions of the V850ES/KG1 and V850ES/KJ1). 3. Only for products with an I C bus
2
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(2) Registers (a) Port 3 register (P3) The port 3 register (P3) is a 16-bit register that controls pin level read and output level write. This register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the P3 register are used as the P3H register and as the P3L register, respectively, this register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KF1
After Reset: Undefined
15 14
R/W
Address: FFFFF406H (P3, P3L), FFFFF407H (P3H)
13 12 11 10 9 8
P3 (P3HNote)
0
0
0
0
0
0
P39
P38
(P3L)
0
0
P35
P34
P33
P32
P31
P30
P3n 0 1
Control of output data (in output mode) (n = 0 to 5, 8, 9) Outputs 0 Outputs 1
(ii) V850ES/KG1, V850ES/KJ1
After Reset: Undefined
15 14
R/W
Address: FFFFF406H (P3, P3L), FFFFF407H (P3H)
13 12 11 10 9 8
P3 (P3H
Note
)
0
0
0
0
0
0
P39
P38
(P3L)
P37
P36
P35
P34
P33
P32
P31
P30
P3n 0 1 Outputs 0 Outputs 1
Control of output data (in output mode) (n = 0 to 9)
Note When reading from or writing to bits 8 to 15 of the P3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the P3H register. Remark In input mode: When read, port 3 (P3) returns the current pin level. When written to, the data written to P3 is written. This has no influence on the input pins. In output mode: When read, port 3 (P3) returns the P3 value. When written to, the value is written to P3 and the written value is immediately output.
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(b) Port 3 mode register (PM3) This is a 16-bit register that specifies the input mode/output mode. This register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the PM3 register are used as the PM3H register and as the PM3L register, respectively, this register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KF1
After Reset: FFFFH
15
R/W
14
Address: FFFFF426H (PM3, PM3L), FFFFF427 (PM3H)
13 12 11 10 9 8
PM3 (PM3HNote)
1
1
1
1
1
1
PM39
PM38
(PM3L)
1
1
PM35
PM34
PM33
PM32
PM31
PM30
PM3n 0 1 Output mode Input mode
Control of I/O mode (n = 0 to 5, 8, 9)
(ii) V850ES/KG1, V850ES/KJ1
After Reset: FFFFH
15
R/W
14
Address: FFFFF426H (PM3, PM3L), FFFFF427 (PM3H)
13 12 11 10 9 8
PM3 (PM3H
Note
)
1
1
1
1
1
1
PM39
PM38
(PM3L)
PM37
PM36
PM35
PM34
PM33
PM32
PM31
PM30
PM3n 0 1 Output mode Input mode
Control of I/O mode (n = 0 to 9)
Note When reading from or writing to bits 8 to 15 of the PM3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PM3H register.
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(c) Port 3 mode control register (PMC3) This is a 16-bit register that specifies the port mode/control mode. This register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the PMC3 register are used as the PMC3H register and as the PMC3L register, respectively, this register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KF1, V850ES/KG1, V850ES/KJ1
After Reset: 0000H
15
R/W
14
Address: FFFFF446H (PMC3, PMC3L), FFFFF447H (PMC3H)
13 12 11 10 9 8
PMC3 (PMC3HNote 1)
0
0
0
0
0
0
PMC39Note PMC38Note
(PMC3L)
0
0
PMC35
PMC34
PMC33
PMC32
PMC31
PMC30
PMC39 0 1 PMC38 0 1 PMC35 0 1 PMC34 0 1 PMC33 0 1 PMC32 0 1 PMC31 0 1 PMC30 0 1 I/O port TXD0 output I/O port RXD0 input I/O port ASCK0 input I/O port TI000/TO00 I/O I/O port TI001 input I/O port TI010/TO01 I/O I/O port SDA0 I/O I/O port SCL0 I/O
Specification of P39 pin operation mode
Specification of P38 pin operation mode
Specification of P35 pin operation mode
Specification of P34 pin operation mode
Specification of P33 pin operation mode
Specification of P32 pin operation mode
Specification of P31 pin operation mode
Specification of P30 pin operation mode
Notes 1. When reading from or writing to bits 8 to 15 of the PMC3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PMC3H register. 2. Only for products with an I C bus. For all other products, set this bit to 0.
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(d) Port 3 function register H (PF3H) This is an 8-bit register that specifies N-ch open-drain output. This register can be read/written in 8-bit or 1-bit units.
After Reset: 00H
R/W
Address: FFFFFC67H
PF3H
0
0
0
0
0
0
PF39
PF38
PF3n 0 1
Control of N-ch open-drain output (n = 8, 9) N-ch open-drain output (when used as normal port) N-ch open-drain output (when used as alternate-function)
Caution When using P38 and P39 as N-ch open-drain-output alternate-function pins, set in the following sequence. Be sure to set the port latch to 1 before setting the pin to N-ch open-drain output. P3n bit = 1 PF3n bit = 1 PMC3n bit = 1
(e) Port 3 function control register (PFC3) This is an 8-bit register that specifies control mode 1/control mode 2. This register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KF1, V850ES/KG1, V850ES/KJ1
After Reset: 00H R/W Address: FFFFF466H
PFC3
0
0
PFC35
0
PFC33
0
0
0
PFC35 0 1 PFC33 0 1
Specification of P35 pin operation mode in control mode TI010 input TO01 output Specification of P33 pin operation mode in control mode TI000 input TO00 output
Caution Always set PFC3 register bits 0 to 2, 4, 6, and 7 to 0.
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(f)
Pull-up resistor option register 3 (PU3) This is an 8-bit register that specifies the connection of an on-chip pull-up resistor. This register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KF1, V850ES/KG1, V850ES/KJ1
After Reset: 00H R/W Address: FFFFFC46H
PU3
0
0
PU35
PU34
PU33
PU32
PU31
PU30
PU3n 0 1
Control of on-chip pull-up resistor connection (n = 0 to 5) Not connected Connected
Caution An on-chip pull-up resistor can be provided for P3n by a mask option. n = 8, 9: For the mask ROM version of the V850ES/KF1 n = 6 to 9: For the mask ROM versions of the V850ES/KG1 and V850ES/KJ1
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(3) Block diagram (port 3) Figure 4-4. Block Diagram of P30
EVDD WRPU PU3 PU30 WRPMC PMC3 PMC30 WRPM PM3 P-ch
Internal bus
PM30
WRPORT
Selector
TXD0 output Output latch (P30)
P30/TXD0
Selector
Address
RD
Remark
PU3: PM3: RD: WR:
Pull-up resistor option register 3 Port 3 mode register Port 3 read signal Port 3 write signal
PMC3: Port 3 mode control register
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Figure 4-5. Block Diagram of P31, P32, and P34
EVDD WRPU PU3 PU3n WRPMC PMC3 PMC3n WRPM PM3 P-ch
Internal bus
PM3n
WRPORT Output latch (P3n) P31/RXD0, P32/ASCK0, P34/TI001
Selector
Address
RD
RXD0, ASCK0, TI001 input
Remarks 1. PU3: PM3: RD: WR:
Pull-up resistor option register 3 Port 3 mode register Port 3 read signal Port 3 write signal
PMC3: Port 3 mode control register
2. n = 1, 2, 4
Selector
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Figure 4-6. Block Diagram of P33 and P35
EVDD WRPU PU3 PU3n WRPF PFC3 PFC3n WRPMC PMC3 PMC3n P-ch
Internal bus
WRPM PM3 PM3n
WRPORT
Selector
TO00, TO01 output Output latch (P3n)
P33/TI000/TO00 P35/TI010/TO01
Selector
Address
RD TI000, TI010 input
Remarks 1. PU3: PM3: RD: WR: 2. n = 3, 5
Pull-up resistor option register 3 Port 3 mode register Port 3 read signal Port 3 write signal
PFC3: Port 3 function control register PMC3: Port 3 mode control register
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Figure 4-7. Block Diagram of P36 and P37
WRPM PM3 PM3n WRPORT Output latch (P3n) N-ch Mask option
EVDD
P36, P37
Internal bus
EVSS EVDD
Selector
Selector
P-ch
Address
Medium-voltage input buffer
RD
Remarks 1. PM3: Port 3 mode register RD: Port 3 read signal WR: Port 3 write signal 2. n = 6, 7
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Figure 4-8. Block Diagram of P38 and P39
WRPF PF3H PF3n WRPMC PMC3 PMC3n WRPM PM3
Internal bus
EVDD Mask option P38/SDA0, P39/SCL0
Selector
PM3n
WRPORT
SDA0, SCL0 output
N-ch
Output latch (P3n)
EVSS
Selector
Address
RD
SDA0, SCL0 input
Remarks 1. PF3H: Port 3 function register H PM3: RD: WR: 2. n = 8, 9 Port 3 mode register Port 3 read signal Port 3 write signal PMC3: Port 3 mode control register
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4.3.4 Port 4 Port 4 can control input/output in 1-bit units. The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 have the same number of I/O port pins for port 4.
Product V850ES/KF1 V850ES/KG1 V850ES/KJ1 I/O Port Pin Count 3-bit I/O port 3-bit I/O port 3-bit I/O port
(1) Port 4 functions Port input/output data can be specified in 1-bit units. Specification is made by the port 4 register (P4). Port input/output can be specified in 1-bit units. Specification is made by the port 4 mode register (PM4). Port mode/control mode (alternate function) can be specified in 1-bit units. Specification is made by the port 4 mode control register (PMC4). N-ch open-drain can be specified in 1-bit units. Specification is made by the port 4 function register (PF4). On-chip pull-up resistor connection can be specified in 1-bit units. Specification is made by pull-up resistor option register 4 (PU4). Port 4 includes the following alternate functions. Table 4-9. Alternate-Function Pins of Port 4
Pin Name Port 4 P40 P41 P42 Alternate Function SI00 SO00 SCK00 I/O I/O PULLNote Yes Remark - N-ch open-drain output can be selected.
Note Software pull-up function
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(2) Registers (a) Port 4 register (P4) The port 4 register (P4) is an 8-bit register that controls pin level read and output level write. This register can be read/written in 8-bit or 1-bit units.
After Reset: Undefined
R/W
Address: FFFFF408H
P4
0
0
0
0
0
P42
P41
P40
P4n 0 1 Output 0 Output 1
Control of output data (in output mode) (n = 0 to 2)
Remark
In input mode:
When read, port 4 (P4) returns the current pin level. When written to, the data written to P4 is written. This has no influence on the input pins.
In output mode:
When read, port 4 (P4) returns the P4 value. When written to, the value is written to P4 and the written value is immediately output.
(b) Port 4 mode register (PM4) This is an 8-bit register that specifies the input mode/output mode. This register can be read/written in 8-bit or 1-bit units.
After Reset: FFH
R/W
Address: FFFFF428H
PM4
1
1
1
1
1
PM42
PM41
PM40
PM4n 0 1 Output mode Input mode
Control of I/O mode (n = 0 to 2)
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(c) Port 4 mode control register (PMC4) This is an 8-bit register that specifies the port mode/control mode. This register can be read/written in 8-bit or 1-bit units.
After Reset: 00H
R/W
Address: FFFFF448H
PMC4
0
0
0
0
0
PMC42
PMC41
PMC40
PMC42 0 1 PMC41 0 1 PMC40 0 1 I/O port SI00 input I/O port SO00 output I/O port SCK00 I/O
Specification of P42 pin operation mode
Specification of P41 pin operation mode
Specification of P40 pin operation mode
(d) Port 4 function register (PF4) This is an 8-bit register that specifies normal output/N-ch open-drain output. This register can be written in 8-bit or 1-bit units.
After Reset: 00H
R/W
Address: FFFFFC68H
PF4
0
0
0
0
0
PF42
PF41
0
PF4n 0 1
Control of normal output/N-ch open-drain output Normal output N-ch open-drain output
Caution When using P41 and P42 as N-ch open-drain-output alternate-function pins, set in the following sequence. Be sure to set the port latch to 1 before setting the pin to N-ch open-drain output. P4n bit = 1 PF4n bit = 1 PMC4n bit = 1
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(e) Pull-up resistor option register 4 (PU4) This is an 8-bit register that specifies the connection of an on-chip pull-up resistor. This register can be read/written in 8-bit or 1-bit units.
After Reset: 00H
R/W
Address: FFFFFC48H
PU4
0
0
0
0
0
PU42
PU41
PU40
PU4n 0 1
Control of on-chip pull-up resistor connection (n = 0 to 2) Not connected Connected
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(3) Block diagram (port 4) Figure 4-9. Block Diagram of P40
EVDD WRPU PU4 PU40 WRPMC PMC4 PMC40 WRPM PM4 P-ch
Internal bus
PM40
WRPORT Output latch (P40)
P40/SI00
Selector
Address
RD
SI00 input
Remark
PU4: PM4: RD: WR:
Pull-up resistor option register 4 Port 4 mode register Port 4 read signal Port 4 write signal
PMC4: Port 4 mode control register
Selector
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Figure 4-10. Block Diagram of P41
EVDD WRPU PU4 PU41 WRPF PF4 PF41 WRPMC PMC4 PMC41 P-ch
Internal bus
WRPM PM4 PM41 EVDD
WRPORT
Selector
SO00 output Output latch (P41)
P-ch P41/SO00 N-ch
Selector
Selector
EVSS
Address
RD
Remark
PU4: PF4: PM4: RD: WR:
Pull-up resistor option register 4 Port 4 function register Port 4 mode register Port 4 read signal Port 4 write signal
PMC4: Port 4 mode control register
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Figure 4-11. Block Diagram of P42
EVDD WRPU PU4 PU42 WRPF PF4 PF42 WRPMC PMC4 PMC42
Internal bus
P-ch
CSI00 output enable signal
WRPM PM4 PM42 EVDD
WRPORT
Selector
SCK00 output Output latch (P42)
P-ch P42/SCK00 N-ch
Selector
Selector
EVSS
Address
CSI00 input enable signal
SCK00 input RD
Remark
PU4: PF4: PM4: RD: WR:
Pull-up resistor option register 0 Port 4 function register Port 4 mode register Port 4 read signal Port 4 write signal
PMC4: Port 4 mode control register
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4.3.5 Port 5 Port 5 can control input/output in 1-bit units. The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 have the same number of I/O port pins for port 5.
Product V850ES/KF1 V850ES/KG1 V850ES/KJ1 I/O Port Pin Count 6-bit I/O port 6-bit I/O port 6-bit I/O port
(1) Port 5 functions Port input/output data can be specified in 1-bit units. Specification is made by the port 5 register (P5). Port input/output can be specified in 1-bit units. Specification is made by the port 5 mode register (PM5). Port mode/control mode (alternate function) can be specified in 1-bit units. Specification is made by the port 5 mode control register (PMC5). N-ch open-drain can be specified in 1-bit units. Specification is made by the port 5 function register (PF5). Control mode 1/control mode 2 can be specified in 1-bit units. Specification is made by the port 5 function control register (PFC5). On-chip pull-up resistor connection can be specified in 1-bit units. Specification is made by pull-up resistor option register 5 (PU5). Port 5 includes the following alternate functions. Table 4-10. Alternate-Function Pins of Port 5
Pin Name Port 5 P50 P51 P52 P53 P54 P55 Alternate Function TI011/RTP00/KR0 TI50/RTP01/KR1 TO50/RTP02/KR2 SIA0/RTP03/KR3 SOA0/RTP04/KR4 SCKA0/RTP05/KR5 N-ch open-drain output can be selected. I/O I/O PULLNote Yes Remark -
Note Software pull-up function
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(2) Registers (a) Port 5 register (P5) The port 5 register (P5) is an 8-bit register that controls pin level read and output level write. This register can be read/written in 8-bit or 1-bit units.
After Reset: Undefined
R/W
Address: FFFFF40AH
P5
0
0
P55
P54
P53
P52
P51
P50
P5n 0 1 Output 0 Output 1
Control of output data (in output mode) (n = 0 to 5)
Remark In input mode:
When read, port 5 (P5) returns the current pin level. When written to, the data written to P5 is written. This has no influence on the input pins.
In output mode: When read, port 5 (P5) returns the P5 value. When written to, the value is written to P5 and the written value is immediately output.
(b) Port 5 mode register (PM5) This is an 8-bit register that specifies the input mode/output mode. This register can be read in 8-bit or 1-bit units.
After Reset: FFH
R/W
Address: FFFFF42AH
PM5
1
1
PM55
PM54
PM53
PM52
PM51
PM50
PM5n 0 1 Output mode Input mode
Control of I/O mode (n = 0 to 5)
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(c) Port 5 mode control register (PMC5) This is an 8-bit register that specifies the port mode/control mode. This register can be read/written in 8-bit or 1-bit units.
After Reset: 00H
R/W
Address: FFFFF44AH
PMC5
0
0
PMC55
PMC54
PMC53
PMC52
PMC51
PMC50
PMC55 0 1 PMC54 0 1 PMC53 0 1 PMC52 0 1 PMC51 0 1 PMC50 0 1
Specification of P55 pin operation mode I/O port/KR5 input SCKA0/RTP05 I/O Specification of P54 pin operation mode I/O port/KR4 input SOA0/RTP04 output Specification of P53 pin operation mode I/O port/KR3 input SIA0/RTP03 I/O Specification of P52 pin operation mode I/O port/KR2 input TO50/RTP0 output Specification of P51 pin operation mode I/O port/KR1 input TI50/RTP01 I/O Specification of P50 pin operation mode I/O port/KR0 input TI011/RTP00 I/O
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(d) Port 5 function register 5 (PF5) This is an 8-bit register that specifies normal output/N-ch open-drain output. This register can be read/written in 8-bit or 1-bit units.
After Reset: 00H
R/W
Address: FFFFFC6AH
PF5
0
0
PF55
PF54
0
0
0
0
PF5n 0 1
Control of normal output/N-ch open-drain output (n = 4, 5) Normal output N-ch open-drain output
Cautions 1. Always set PF5 register bits 0 to 3, 6, and 7 to 0. 2. When using P54 and P55 as N-ch open-drain-output alternate-function pins, set in the following sequence. Be sure to set the port latch to 1 before setting the pin to N-ch open-drain output. P5n bit = 1 PF5n bit = 1 PMC5n bit = 1
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(e) Port 5 function control register (PFC5) This is an 8-bit register that specifies control mode 1/control mode 2. This register can be read/written in 8-bit or 1-bit units.
After Reset: 00H
R/W
Address: FFFFF46AH
PFC5
0
0
PFC55
PFC54
PFC53
PFC52
PFC51
PFC50
PFC55 0 1 PFC54 0 1 PFC53 0 1 PFC52 0 1 PFC51 0 1 PFC50 0 1
Specification of P55 pin operation mode in control mode SCKA0 I/O RTP05 output Specification of P54 pin operation mode in control mode SOA0 output RTP04 output Specification of P53 pin operation mode in control mode SIA0 input RTP03 output Specification of P52 pin operation mode in control mode TO50 output RTP02 output Specification of P51 pin operation mode in control mode TI50 input RTP01 output Specification of P50 pin operation mode in control mode TI011 input RTP00 output
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(f)
Pull-up resistor option register 5 (PU5) This is an 8-bit register that specifies the connection of an on-chip pull-up resistor. This register can be read/written in 8-bit or 1-bit units.
After Reset: 00H
R/W
Address: FFFFFC4AH
PU5
0
0
PU55
PU54
PU53
PU52
PU51
PU50
PU5n 0 1
Control of on-chip pull-up resistor connection (n = 0 to 5) Not connected Connected
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(3) Block diagram (port 5) Figure 4-12. Block Diagram of P50, P51, and P53
EVDD WRPU PU5 PU5n WRPFC PFC5 PFC5n WRPMC PMC5 PMC5n WRPM
Internal bus
P-ch
PM5 PM5n
WRPORT
Output latch (P5n)
Selector
RTP0n output
P50/TI011/RTP00/KR0, P51/TI50/RTP01/KR1, P53/SIA0/RTP03/KR3
Selector
RD Address
TI011, TI50, SIA0 input KRn input
Remarks 1. PU5: PM5: RD: WR:
Pull-up resistor option register 5 Port 5 mode register Port 5 read signal Port 5 write signal
PFC5: Port 5 function control register PMC5: Port 5 mode control register
2. n = 0, 1, 3
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Figure 4-13. Block Diagram of P52
EVDD WRPU PU5 PU52 WRPFC PFC5 PFC52 WRPMC PMC5 PMC52 WRPM
Internal bus
P-ch
PM5 PM52
TO50 output RTP02 output WRPORT Output latch (P52)
Selector
Selector
P52/TO50/RTP02/KR2
Selector
RD Address
Selector
KR2 input
Remark
PU5: PM5: RD: WR:
Pull-up resistor option register 5 Port 5 mode register Port 5 read signal Port 5 write signal
PFC5: Port 5 function control register PMC5: Port 5 mode control register
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Figure 4-14. Block Diagram of P54
EVDD WRPU PU5 PU54 WRPF PF5 PF54 WRPFC PFC5 PFC54 WRPMC PMC5 PMC54
Internal bus
P-ch
WRPM PM5 PM54 EVDD SOA0 output RTP04 output
Selector
Selector
WRPORT
P-ch
Output latch (P54)
P54/SOA0/RTP04/KR4 N-ch
Selector
Selector
EVSS
RD Address
KR4 input
Remark
PU5: PF5: PM5: RD: WR:
Pull-up resistor option register 5 Port 5 function register Port 5 mode register Port 5 read signal Port 5 write signal
PFC5: Port 5 function control register PMC5: Port 5 mode control register
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Figure 4-15. Block Diagram of P55
EVDD WRPU PU5 PU55 WRPF PF5 PF55 WRPFC PFC5 PFC55 WRPMC PMC5
Internal bus
P-ch
CSIA0 output enable signal
PMC55 WRPM PM5 PM55 EVDD SCKA0 output RTP05 output
Selector
Selector
WRPORT
P-ch
Output latch (P55)
N-ch
P55/SCKA0/RTP05/KR5
Selector
Selector
EVSS
RD Address
SCKA0 input KR5 input
Remark
PU5: PF5: PM5: RD: WR:
Pull-up resistor option register 5 Port 5 function register Port 5 mode register Port 5 read signal Port 5 write signal
PFC5: Port 5 function control register PMC5: Port 5 mode control register
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4.3.6 Port 6 Port 6 can control input/output in 1-bit units. The number of I/O port pins for port 6 differs according to the product.
Product V850ES/KF1 V850ES/KG1 V850ES/KJ1 16-bit I/O port I/O Port Pin Count - -
(1) Port 6 functions (V850ES/KJ1) Port input/output data can be specified in 1-bit units. Specification is made by the port 6 register (P6). Port input/output can be specified in 1-bit units. Specification is made by the port 6 mode register (PM6). Port mode/control mode (alternate functions) can be specified in 1-bit units. Specification is made by the port 6 mode control register (PMC6). N-ch open-drain can be specified in 1-bit units. Specification is made by the port 6 function register (PF6). Control mode 1/control mode 2 can be specified in 1-bit units. Specification is made by the port 6 function control register (PFC6H). On-chip pull-up resistor connection can be specified in 1-bit units. Specification is made by pull-up resistor option register 6 (PU6). Port 6 includes the following alternate functions. Table 4-11. Alternate-Function Pins of Port 6 (V850ES/KJ1)
Pin Name Port 6 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P610 P611 P612 P613 P614 P615 Alternate Function RTP10 RTP11 RTP12 RTP13 RTP14 RTP15 SI02 SO02 SCK02 TI040 TI041 TO04 TI050 TI051/TO05 - - No - N-ch open-drain output I/O I/O PULLNote Yes Remark -
Note Software pull-up function
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(2) Registers (a) Port 6 register (P6) The port 6 register (P6) is a 16-bit register that controls pin level read and output level write. This register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the P6 register are used as the P6H register and as the P6L register, respectively, this register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KJ1
After Reset: Undefined
15 14
R/W
Address: FFFFF40CH (P6, P6L), FFFFF40DH (P6H)
13 12 11 10 9 8
P6 (P6HNote)
P615
P614
P613
P612
P611
P610
P69
P68
(P6L)
P67
P66
P65
P64
P63
P62
P61
P60
P6n 0 1 Output 0 Output 1
Control of output data (in output mode) (n = 0 to 15)
Note When reading from or writing to bits 8 to 15 of the P6 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the P6H register. Remark In input mode: When read, port 6 (P6) returns the current pin level. When written to, the data written to P6 is written. This has no influence on the input pins. In output mode: When read, port 6 (P6) returns the P6 value. When written to, the value is written to P6 and the written value is immediately output.
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(b) Port 6 mode register (PM6) This is a 16-bit register that specifies the input mode/output mode. This register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the PM6 register are used as the PM6H register and as the PM6L register, respectively, this register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KJ1
After Reset: FFFFH
15
R/W
14
Address: FFFFF42CH (PM6, PM6L), FFFFF42D (PM6H)
13 12 11 10 9 8
PM6 (PM6HNote)
PM615
PM614
PM613
PM612
PM611
PM610
PM69
PM68
(PM6L)
PM67
PM66
PM65
PM64
PM63
PM62
PM61
PM60
PM6n 0 1 Output mode Input mode
Control of I/O mode (n = 0 to 15)
Note When reading from or writing to bits 8 to 15 of the PM6 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PM6H register.
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(c) Port 6 mode control register (PMC6) This is a 16-bit register that specifies the port mode/control mode. This register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the PMC6 register are used as the PMC6H register and as the PMC6L register, respectively, this register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KJ1
After Reset: 0000H
15
R/W
14
Address: FFFFF44CH (PMC6, PMC6L), FFFFF44DH (PMC6H)
13 12 11 10 9 8
PMC6 (PMC6H
Note
)
0
0
PMC613 PMC612 PMC611 PMC610
PMC69
PMC68
(PMC6L)
PMC67
PMC66
PMC65
PMC64
PMC63
PMC62
PMC61
PMC60
PMC613 0 1 PMC612 0 1 PMC611 0 1 PMC610 0 1 PMC69 0 1 PMC68 0 1 PMC67 0 1 PMC66 0 1 PMC6n 0 1 I/O port RTP1n output I/O port SI02 input I/O port SO02 output I/O port SCK02 I/O I/O port TI040 input I/O port TI041 input I/O port TO04 output I/O port TI050 input I/O port TI051/TO05 I/O
Specification of P613 pin operation mode
Specification of P612 pin operation mode
Specification of P611 pin operation mode
Specification of P610 pin operation mode
Specification of P69 pin operation mode
Specification of P68 pin operation mode
Specification of P67 pin operation mode
Specification of P66 pin operation mode
Specification of P6n pin operation mode (n = 0 to 5)
Note When reading from or writing to bits 8 to 15 of the PMC6 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PMC6H register.
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(d) Port 6 function register (PF6) This is a 16-bit register that specifies normal output/N-ch open-drain output. The PF6 register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the PF6 register are used as the PF6H register and as the PF6L register, respectively, this register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KJ1
After Reset: 0000H
15
R/W
14
Address: FFFFFC6CH (PF6, PH6L), FFFFFC6DH (PF6H)
13 12 11 10 9 8
PF6 (PF6HNote)
0
0
0
0
0
0
0
PF68
(PF6L)
PF67
0
0
0
0
0
0
0
PF6n 0 1
Control of normal output/N-ch open-drain output (n = 7, 8) Normal output N-ch open-drain output
Note When reading from or writing to bits 8 to 15 of the PF6 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PF6H register. Caution Always set PF6 register bits 0 to 6 and 9 to 15 to 0.
(e) Port 6 function control register (PFC6H) This is an 8-bit register that specifies control mode 1/control mode 2. This register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KJ1
After Reset: 00H R/W Address: FFFFF46DH
PFC6H
0
0
PFC613
0
0
0
0
0
PFC613 0 1
Specification of P613 pin operation mode in control mode TI051 input TO05 output
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(f)
Pull-up resistor option register 6 (PU6) This is a 16-bit register that specifies the connection of an on-chip pull-up resistor. This register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the PU6 register are used as the PU6H register and as the PU6L register, respectively, this register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KJ1
After Reset: 0000H
15
R/W
14
Address: FFFFFC4CH (PU6, PU6L), FFFFFC4DH (PU6H)
13 12 11 10 9 8
PU6 (PU6HNote)
0
0
PU613
PU612
PU611
PU610
PU69
PU68
(PU6L)
PU67
PU66
PU65
PU64
PU63
PU62
PU61
PU60
PU6n 0 1
Control of on-chip pull-up resistor connection (n = 0 to 13) Not connected Connected
Note When reading from or writing to bits 8 to 15 of the PU6 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PU6H register. Caution An on-chip pull-up resistor can be provided for P614 and P615 (only for the mask ROM version of the V850ES/KJ1).
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(3) Block diagram (Port 6) Figure 4-16. Block Diagram of P60 to P65, and P611
EVDD WRPU PU6 PU6n, PU611 WRPMC PMC6 PMC6n, PMC611 WRPM PM6 P-ch
Internal bus
PM6n, PM611
Output latch (P6n, P611)
Selector
Address
RD
Remarks 1. PU6: PM6: RD: WR:
Pull-up resistor option register 6 Port 6 mode register Port 6 read signal Port 6 write signal
PMC6: Port 6 mode control register
2. n = 0 to 5
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Selector
Selector
WRPORT
RTP1n, TO04 output
P60/RTP10, P61/RTP11, P62/RTP12, P63/RTP13, P64/RTP14, P65/RTP15, P611/TO04
CHAPTER 4 PORT FUNCTIONS
Figure 4-17. Block Diagram of P66, P69, P610, and P612
EVDD WRPU PU6 PU6n WRPMC PMC6 PMC6n WRPM PM6 P-ch
Internal bus
PM6n
WRPORT Output latch (P6n) P66/SI02, P69/TI040, P610/TI041, P612/TI050
Selector
Address
RD
SI02, TI040, TI041, TI050 input
Remarks 1. PU6: PM6: RD: WR:
Pull-up resistor option register 6 Port 6 mode register Port 6 read signal Port 6 write signal
PMC6: Port 6 mode control register
2. n = 6, 9, 10, 12
Selector
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Figure 4-18. Block Diagram of P67
EVDD WRPU PU6 PU67 WRPF PF6 PF67 WRPMC PMC6 PMC67 P-ch
Internal bus
WRPM PM6 PM67 EVDD
WRPORT
Selector
SO02 output Output latch (P67)
P-ch P67/SO02 N-ch
Selector
Selector
EVSS
Address
RD
Remark
PU6: PF6: PM6: RD: WR:
Pull-up resistor option register 6 Port 6 function register Port 6 mode register Port 6 read signal Port 6 write signal
PMC6: Port 6 mode control register
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Figure 4-19. Block Diagram of P68
EVDD WRPU PU6 PU68 WRPF PF6 PF68 WRPMC PMC6 PMC68
Internal bus
P-ch
CSI02 output enable signal
WRPM PM6 PM68 EVDD
WRPORT
Selector
SCK02 output Output latch (P68)
P-ch P68/SCK02 N-ch
Selector
Selector
EVSS
Address
CSI02 input enable signal
SCK02 input RD
Remark
PU6: PF6:
Pull-up resistor option register 6 Port 6 function register
PM6: Port 6 mode register PMC6: Port 6 mode control register RD: WR: Port 6 read signal Port 6 write signal
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Figure 4-20. Block Diagram of P613
EVDD WRPU PU6 PU613 WRPFC PFC6 PFC613 WRPMC PMC6 PMC613
Internal bus
P-ch
WRPM PM6 PM613
WRPORT
Selector
TO05 output Output latch (P613)
P613/TI051/TO05
Selector
Address
RD TI051 input
Remark
PU6: PM6: RD: WR:
Pull-up resistor option register 6 Port 6 mode register Port 6 read signal Port 6 write signal
PFC6: Port 6 function control register PMC6: Port 6 mode control register
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Figure 4-21. Block Diagram of P614 and P615
WRPM PM6 PM61n WRPORT Output latch (P61n) N-ch Mask option
EVDD
P614, P615
Internal bus
EVSS EVDD
Selector
Selector
P-ch
Address
Medium-voltage input buffer
RD
Remarks 1. PM6: Port 6 mode register RD: Port 6 read signal WR: Port 6 write signal 2. n = 4, 5
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4.3.7 Port 7 All the pins of port 7 are fixed to input. The number of input port pins for port 7 differs according to the product.
Product V850ES/KF1 V850ES/KG1 V850ES/KJ1 Input Port Pin Count 8-bit input port 8-bit input port 16-bit input port
(1) Port 7 functions Port input data read is possible in 1-bit units. Specification is made by the port 7 register (P7). Port 7 includes the following alternate functions. Table 4-12. Alternate-Function Pins of Port 7 (V850ES/KF1, V850ES/KG1)
Pin Name Port 7 P70 P71 P72 P73 P74 P77 P76 P77 Alternate Function ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 I/O Input PULLNote No Remark -
Note Software pull-up function
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Table 4-13. Alternate-Function Pins of Port 7 (V850ES/KJ1)
Pin Name Port 7 P70 P71 P72 P73 P74 P77 P76 P77 P78 P79 P710 P711 P712 P713 P714 P715 Alternate Function ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANI12 ANI13 ANI14 ANI15 I/O Input PULLNote No Remark -
Note Software pull-up function
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(2) Registers (a) Port 7 register (P7) The port 7 register (P7) of the V850ES/KF1 and V850ES/KG1 is an 8-bit register that reads the pin level. This register can be read in 8-bit units. The port 7 register (P7) of the V850ES/KJ1 is a 16-bit register that reads the pin level. This register can be read only in 16-bit units. However, when the higher 8 bits of the P7 register are used as the P7H register and the lower 8 bits as the P7L register, they can be read in 8-bit units.
(i) V850ES/KF1, V850ES/KG1
After Reset: Undefined R Address: FFFFF40EH
P7
P77
P76
P75
P74
P73
P72
P71
P70
P7n 0 1 Input low level Input high level
Input data read (n = 0 to 7)
(ii) V850ES/KJ1
After Reset: Undefined
15 14
R
Address: FFFFF40EH (P7, P7L), FFFFF40FH (P7H)
13 12 11 10 9 8
P7 (P7H
Note
)
P715
P714
P713
P712
P711
P710
P79
P78
(P7L)
P77
P76
P75
P74
P73
P72
P71
P70
P7n 0 1 Input low level Input high level
Input data read (n = 0 to 12)
Note When reading from or writing to bits 8 to 15 of the P7 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the P7H register. Remark When port 7 (P7) is read, the current pin level is returned.
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(3) Block diagram (Port 7) Figure 4-22. Block Diagram of P70 to P715
Internal bus
P7n/ANIn
RD ANIn input
Remark
n = 0 to 15 RD: Port 7 read signal
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4.3.8 Port 8 Port 8 controls input/output in 1-bit units. The number of I/O port pins differs according to the product.
Product V850ES/KF1 V850ES/KG1 V850ES/KJ1 2-bit I/O port I/O Port Pin Count - -
(1) Port 8 function (V850ES/KJ1) Port input/output data can be specified in 1-bit units. Specification is made by the port 8 register (P8). Port input/output can be specified in 1-bit units. Specification is made by the port 8 mode register (PM8). Port mode/control mode (alternate function) can be specified in 1-bit units. Specification is made by the port 8 mode control register (PMC8). N-ch open-drain can be specified in 1-bit units. Specification is made by the port 8 function register (PF8). Control mode 1/control mode 2 can be specified in 1-bit units. Specification is made by the port 8 function control register (PFC8). On-chip pull-up resistor connection can be specified in 1-bit units. Specification is made by pull-up resistor option register 8 (PU8). Port 8 includes the following alternate functions. Table 4-14. Alternate-Function Pins of Port 8 (V850ES/KJ1)
Pin Name Port 8 P80 P81 Alternate Function RXD2/SDA1 TXD2/SCL1
Note 2
I/O Input
PULLNote Yes
Remark N-ch open-drain output can be selected.
Note 2
Notes 1. Software pull-up function 2. Only for the PD703216Y, 703217Y, and 70F3217Y
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(2) Registers (a) Port 8 register (P8) The port 8 register (PM8) is an 8-bit register that controls pin level read and output level write. This register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KJ1
After Reset: Undefined R/W Address: FFFFF410H
P8
0
0
0
0
0
0
P81
P80
P8n 0 1 Output 0 Output 1
Control of output data (in output mode) (n = 0, 1)
Remark In input mode:
When read, port 8 (P8) returns the current pin level. When written to, the data written to P8 is written. This has no influence on the input pins.
In output mode: When read, port 8 (P8) returns the P8 value. When written to, the value is written to P8 and the written value is immediately output.
(b) Port 8 mode register (PM8) This is an 8-bit register that specifies the input mode/output mode. This register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KJ1
After Reset: FFH R/W Address: FFFFF430H
PM8
1
1
1
1
1
1
PM81
PM80
PM8n 0 1 Output mode Input mode
Control of I/O mode (n = 0, 1)
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(c) Port 8 mode control register (PMC8) This is an 8-bit register that specifies the port mode/control mode. This register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KJ1
After Reset: 00H R/W Address: FFFFF450H
PMC8
0 PMC81 0 1 PMC80 0 1
0
0
0
0
0
PMC81
PMC80
Specification of P81 pin operation mode I/O port TXD2/SCL1Note I/O Specification of P80 pin operation mode I/O port RXD2/SDA1Note I/O
Note Only for the PD703216Y, 703217Y, and 70F3217Y.
(d) Port 8 function register (PF8) This is an 8-bit register that specifies normal output/N-ch open-drain output. This register can be read/written in 8-bit or 1-bit units.
(i) 850ES/KJ1
After Reset: 00H R/W Address: FFFFFC70H
PF8
0
0
0
0
0
0
PF81
PF80
PF8n 0 1
Control of normal output/N-ch open-drain output (n = 0, 1) Normal output N-ch open-drain output
Caution When using P80 and P81 as N-ch open-drain-output alternate-function pins, set in the following sequence. Be sure to set the port latch to 1 before setting the pin to N-ch open-drain output. P8n bit = 1 PFC8n bit = 0/1 PF8n bit = 1 PMC8n bit = 1
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(e) Port 8 function control register (PFC8) This is an 8-bit register that specifies control mode 1/control mode 2. This register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KJ1
After Reset: 00H R/W Address: FFFFF470H
PFC8
0
0
0
0
0
0
PFC81
PFC80
PFC81 0 1 PFC80 0 1
Specification of P81 pin operation mode in control mode TXD2 output SCL1Note I/O Specification of P80 pin operation mode in control mode RXD2 input SDA1Note I/O
Note Only for the PD703216Y, 703217Y, and 70F3217Y. Set to 0 for all other products.
(f)
Pull-up resistor option register 8 (PU8) This is an 8-bit register that specifies the connection of an on-chip pull-up resistor. This register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KJ1
After Reset: 00H R/W Address: FFFFFC50H
PU8
0
0
0
0
0
0
PU81
PU80
PU8n 0 1
Control of on-chip pull-up resistor connection (n = 0, 1) Not connected Connected
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(3) Block diagram (Port 8) Figure 4-23. Block Diagram of P80
EVDD WRPU PU8 PU80 WRPF PF8 PF80 WRPFC PFC8 PFC80 WRPMC PMC8
Internal bus
P-ch
PMC80 WRPM PM8 PM80 EVDD
Selector
WRPORT
SDA1 output P-ch
Output latch (P80)
P80/RXD2/SDA1 N-ch
Selector
Selector
EVSS
Address
RD RXD2 input
Selector
SDA1 input
Remark
PU8: PF8: PM8: RD: WR:
Pull-up resistor option register 8 Port 8 function register Port 8 mode register Port 8 read signal Port 8 write signal
PFC8: Port 8 function control register PMC8: Port 8 mode control register
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Figure 4-24. Block Diagram of P81
EVDD WRPU PU8 PU81 WRPF PF8 PF81 WRPFC PFC8 PFC81 WRPMC
Internal bus
P-ch
PMC8 PMC81 WRPM PM8 PM81 TXD2 output SCL1 output WRPORT Output latch (P81) EVDD
Selector
Selector
P-ch
N-ch
P81/TXD2/SCL1
Selector
Selector
EVSS
Address
RD
SCL1 input
Remark
PU8: PF8: PM8: RD: WR:
Pull-up resistor option register 8 Port 8 function register Port 8 mode register Port 8 read signal Port 8 write signal
PFC8: Port 8 function control register PMC8: Port 8 mode control register
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4.3.9 Port 9 Port 9 controls input/output in 1-bit units. The number of I/O port pins for port 9 differs according to the product.
Product V850ES/KF1 V850ES/KG1 V850ES/KJ1 I/O Port Pin Count 9-bit I/O port 16-bit I/O port 16-bit I/O port
(1) Port 9 functions Port input/output data can be specified in 1-bit units. Specification is made by the port 9 register (P9). Port input/output can be specified in 1-bit units. Specification is made by the port 9 mode register (PM9). Port mode/control mode (alternate functions) can be specified in 1-bit units. Specification is made by the port 9 mode control register (PMC9). N-ch open-drain can be specified in 1-bit units. Specification is made by the port 9 function register (PF9H). Control mode 1/control mode 2 can be specified in 1-bit units. Specification is made by the port 9 function control register (PFC9). On-chip pull-up resistor connection can be specified in 1-bit units. Specification is made by pull-up resistor option register 9 (PU9). The valid edge of external interrupts (alternate function) can be specified in 1-bit units. The falling edge and the rising edge of the external interrupt are specified by falling edge specification register 9H (INTF9H) and rising edge specification register 9H (INTR9H), respectively.
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Port 9 includes the following alternate functions. Table 4-15. Alternate-Function Pins of Port 9 (V850ES/KF1)
Pin Name Port 9 P90 P91 P96 P97 P98 P99 P913 P914 P915 Alternate Function TXD1/KR6 RXD1/KR7 TI51/TO51 SI01 SO01 SCK01 INTP4 INTP5 INTP6 Analog noise elimination N-ch open-drain output can be specified. I/O I/O PULLNote No Remark -
Note Software pull-up function Caution When port 9 is used as alternate-function, be sure to set the PFC9 register in addition to the PMC9 register. When the control mode is set by the PMC9n bit of the PMC9 register with the PFC9n bit of the PFC9 register maintaining the initial value (0), output becomes undefined. control mode 2 of port 9, follow the sequence below (n = 0, 1, 6 to 9, 13 to 15). <1> Set the PFC9 register first (OFC9n bit = 1) <2> Then set the PMC register (PMC9n bit = 1) Table 4-16. Alternate-Function Pins of Port 9 (V850ES/KG1, V850ES/KJ1)
Pin Name Port 9 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P910 P911 P912 P913 P914 P915 Alternate Function A0/TXD1/KR6 A1/RXD1/KR7 A2/TI020/TO02 A3/TI021 A4/TI030/TO03 A5/TI031 A6/TI51/TO51 A7/SI01 A8/SO01 A9/SCK01 A10/SIA1 A11/SOA1 A12/SCKA1 A13/INTP4 A14/INTP5 A15/INTP6 Analog noise elimination - N-ch open-drain output can be specified. N-ch open-drain output can be specified. I/O I/O PULLNote No Remark -
Therefore, to set
Note Software pull-up function
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(2) Registers (a) Port 9 register (P9) The port 9 register (P9) is a 16-bit register that controls pin level read and output level write. This register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the P9 register are used as the P9H register and as the P9L register, respectively, these registers can be read/written in 8-bit or 1-bit units.
(i) V850ES/KF1
After Reset: Undefined
15 14
R/W
Address: FFFFF412H (P9, P9L), FFFFF413H (P9H)
13 12 11 10 9 8
P9 (P9HNote)
P915
P914
P913
0
0
0
P99
P98
(P9L)
P97
P96
0
0
0
0
P91
P90
P9n 0 1
Control of output data (in output mode) (n = 0, 1, 6 to 9, 13 to 15) Output 0 Output 1
(ii) V850ES/KG1, V850ES/KJ1
After Reset: Undefined
15 14
R/W
Address: FFFFF412H (P9, P9L), FFFFF413H (P9H)
13 12 11 10 9 8
P9 (P9HNote)
P915
P914
P913
P912
P911
P910
P99
P98
(P9L)
P97
P96
P95
P94
P93
P92
P91
P90
P9n 0 1 Output 0 Output 1
Control of output data (in output mode) (n = 0 to 15)
Note When reading from or writing to bits 8 to 15 of the P9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the P9H register. Remark In input mode: When read, port 9 (P9) returns the current pin level. When written to, the data written to P9 is written. This has no influence on the input pins. In output mode: When read, port 9 (P9) returns the P9 value. When written to, the value is written to P9 and the written value is immediately output.
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(b) Port 9 mode register (PM9) This is a 16-bit register that specifies the input mode/output mode. This register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the PM9 register are used as the PM9H register and as the PM9L register, respectively, this register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KF1
After Reset: FFFFH
15
R/W
14
Address: FFFFF432H (PM9, PM9L), FFFFF433H (PM9H)
13 12 11 10 9 8
PM9 (PM9HNote)
PM915
PM914
PM913
1
1
1
PM99
PM98
(PM9L)
PM97
PM96
1
1
1
1
PM91
PM90
PM9n 0 1 Output mode Input mode
Control of I/O mode (n = 0, 1, 6 to 9, 13 to 15)
(ii) V850ES/KG1, V850ES/KJ1
After Reset: FFFFH
15
R/W
14
Address: FFFFF432H (PM9, PM9L), FFFFF433H (PM9H)
13 12 11 10 9 8
PM9 (PM9H
Note
)
PM915
PM914
PM913
PM912
PM911
PM910
PM99
PM98
(PM9L)
PM97
PM96
PM95
PM94
PM93
PM92
PM91
PM90
PM9n 0 1 Output mode Input mode
Control of I/O mode (n = 0 to 5)
Note When reading from or writing to bits 8 to 15 of the PM9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PM9H register.
(c) Port 9 mode control register (PMC9) This is a 16-bit register that specifies the port mode/control mode. This register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the PMC9 register are used as the PMC9H register and as the PMC9L register, respectively, these registers can be read/written in 8-bit or 1-bit units. Caution When used as the A0 to A15 pins, perform 16-bit setting of PMC9 register = FFFFH at one time (only for V850ES/KG1, V850ES/KJ1).
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(i) V850ES/KJ1
After Reset: 0000H
15
R/W
14
Address: FFFFF452H (PMC9, PMC9L), FFFFF453H (PML9H)
13 12 11 10 9 8
PMC9 (PMC9H
Note
)
PMC915 PMC914 PMC913
0
0
0
PMC99
PMC98
(PMC9L)
PMC97
PMC96
0
0
0
0
PMC91
PMC90
PMC915 0 1 PMC914 0 1 PMC913 0 1 PMC99 0 1 PMC98 0 1 PMC97 0 1 PMC96 0 1 PMC91 0 1 PMC90 0 1 I/O port SI01 input I/O port SO01 output I/O port SCK01 I/O I/O port INTP4 input I/O port INTP5 input I/O port INTP6 input
Specification of P915 pin operation mode
Specification of P914 pin operation mode
Specification of P612 pin operation mode
Specification of P99 pin operation mode
Specification of P98 pin operation mode
Specification of P97 pin operation mode
Specification of P96 pin operation mode I/O port/TI51 input TO51 output Specification of P91 pin operation mode I/O port/KR7 input RXD1 input Specification of P90 pin operation mode I/O port/KR6 input TXD1 output
Note When reading from or writing to bits 8 to 15 of the PMC9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PMC9H register.
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(1/2) (ii) V850ES/KG1, V850ES/KJ1
After Reset: 0000H
15
R/W
14
Address: FFFFFF452H (PMC9, PMC9L), FFFFF453H (PMC9H)
13 12 11 10 9 8
PMC9 (PMC9HNote)
PMC915 PMC914 PMC913 PMC912 PMC911 PMC910
PMC99
PMC98
(PMC9L)
PMC97
PMC96
PMC95
PMC94
PMC93
PMC92
PMC91
PMC90
PMC915 0 1 PMC914 0 1 PMC913 0 1 PMC912 0 1 PMC911 0 1 PMC910 0 1 PMC99 0 1 PMC98 0 1 I/O port A8/SO01 output I/O port A9/SCK01 I/O I/O port A10/SIA1 I/O I/O port I/O port A12/SCKA1 I/O I/O port A13/INTP4 I/O I/O port A14/INTP5 I/O I/O port A15/INTP6 I/O
Specification of P915 pin operation mode
Specification of P914 pin operation mode
Specification of P913 pin operation mode
Specification of P912 pin operation mode
Specification of P911 pin operation mode
A11/SOA1 output Specification of P910 pin operation mode
Specification of P99 pin operation mode
Specification of P98 pin operation mode
Note When reading from or writing to bits 8 to 15 of the PMC9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PMC9H register.
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PMC97 0 1 PMC96 0 1 PMC95 0 1 PMC94 0 1 PMC93 0 1 PMC92 0 1 PMC91 0 1 PMC90 0 1 I/O port A3/TI021 I/O Specification of P92 pin operation mode I/O port/TI020 input A2/TO02 output Specification of P91 pin operation mode I/O port/KR7 input A1/RXD1 I/O Specification of P90 pin operation mode I/O port/KR6 input A0/TXD1 output I/O port A5/TI031 I/O Specification of P94 pin operation mode I/O port/TI030 input A4/TO03 output Specification of P93 pin operation mode I/O port/TI51 A6/TO51 output Specification of P95 pin operation mode I/O port A7/SI01 I/O Specification of P96 pin operation mode Specification of P97 pin operation mode
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(d) Port 9 function register H (PF9H) This is an 8-bit register that specifies normal output/N-ch open-drain output. This register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KF1
After Reset: 00H R/W Address: FFFFFC73H
PF9H
0
0
0
0
0
0
PF99
PF98
PF9n 0 1
Control of normal output/N-ch open-drain output (n = 0, 1) Normal output N-ch open-drain output
(ii) V850ES/KG1, V850ES/KJ1
After Reset: 00H R/W Address: FFFFFC73H
PF9H
0
0
0
PF912
PF911
0
PF99
PF98
PF9n 0 1
Control of normal output/N-ch open-drain output (n = 0, 1, 4, 5) Normal output N-ch open-drain output
Caution When using P98, P99, P911, and P912 as N-ch open-drain-output alternatefunction pins, set in the following sequence. Be sure to set the port latch to 1 before setting the pin to N-ch open-drain output. P9n bit = 1 PFC9n bit = 0/1 PF9n bit = 1 PMC9n bit = 1
(e) Port 9 function control register (PFC9) This is a 16-bit register that specifies control mode 1/control mode 2. This register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the PFC9 register are used as the PFC9H register and as the PFC9L register, respectively, these registers can be read/written in 8-bit or 1-bit units. Cautions 1. When used as the A0 to A15 pins, perform 16-bit setting of PFC9 register = 0000H at one time (only for V850ES/KG1, V850ES/KJ1). 2. When the control mode is set by the PMC9n bit of the PMC9 register with the PFC9n bit of the PFC9 register maintaining the initial value (0), output becomes undefined. Therefore, to set control mode 2 of port 9, set the PFC9n bit to 1 first and then set the PMC9n bit to 1 (n = 0, 1, 6 to 9, 13 to 15) (V850ES/KF1 only).
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(i) V850ES/KF1
After Reset: 0000H
15
R/W
14
Address: FFFFF472H (PFC9, PFC9L), FFFFF473H (PFC9H)
13 12 11 10 9 8
PFC9 (PFC9HNote)
PFC910
PFC910
PFC910
0
0
0
PFC99
PFC98
(PFC9L)
PFC97
PFC96
0
0
0
0
PFC91
PFC90
PFC915 1 PFC914 1 PFC913 1 PFC99 1 PFC98 1 PFC97 1 PFC96 1 PFC91 1 PFC90 1
Specification of P915 pin operation mode in control mode INTP6 input Specification of P914 pin operation mode in control mode INTP5 input Specification of P913 pin operation mode in control mode INTP4 input Specification of P99 pin operation mode in control mode SCK01 I/O Specification of P98 pin operation mode in control mode SO01 output Specification of P97 pin operation mode in control mode SI01 input Specification of P96 pin operation mode in control mode TO51 output Specification of P91 pin operation mode in control mode RXD1 input Specification of P90 pin operation mode in control mode TXD1 output
Note When reading from or writing to bits 8 to 15 of the PFC9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PFC9H register.
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(1/2) (ii) V850ES/KG1, V850ES/KJ1
After Reset: 0000H
15
R/W
14
Address: FFFFF472H (PFC9, PFC9L), FFFFF473H (PFC9H)
13 12 11 10 9 8
PFC9 (PFC9H
Note
)
PFC915
PFC914
PFC913 PFC912
PFC911 PFC910
PFC99
PFC98
(PFC9L)
PFC97
PFC96
PFC95
PFC94
PFC93
PFC92
PFC91
PFC90
PFC915 0 1 PFC914 0 1 PFC913 0 1 PFC912 0 1 PFC911 0 1 PFC910 0 1 PFC99 0 1 PFC98 0 1
Specification of P915 pin operation mode in control mode A15 output INTP6 input Specification of P914 pin operation mode in control mode A14 output INTP5 input Specification of P913 pin operation mode in control mode A13 output INTP4 input Specification of P912 pin operation mode in control mode A12 output SCKA1 I/O Specification of P911 pin operation mode in control mode A11 output SOA1 output Specification of P910 pin operation mode in control mode A10 output SIA1 input Specification of P99 pin operation mode in control mode A9 output SCK01 I/O Specification of P98 pin operation mode in control mode A8 output SO01 output
Note When reading from or writing to bits 8 to 15 of the PFC9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PFC9H register.
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(2/2)
PFC97 0 1 PFC96 0 1 PFC95 0 1 PFC94 0 1 PFC93 0 1 PFC92 0 1 PFC91 0 1 PFC90 0 1 Specification of P97 pin operation mode in control mode A7 output SI01 input Specification of P96 pin operation mode in control mode A6 output TO51 output Specification of P95 pin operation mode in control mode A5 output TI031 input Specification of P94 pin operation mode in control mode A4 output TO03 output Specification of P93 pin operation mode in control mode A3 output TI021 input Specification of P92 pin operation mode in control mode A2 output TO02 output Specification of P91 pin operation mode in control mode A1 output RXD1 input Specification of P90 pin operation mode in control mode A0 output TXD1 output
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(f)
Pull-up resistor option register 9 (PU9) This is a 16-bit register that specifies the connection of an on-chip pull-up resistor. This register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the PU9 register are used as the PU9H register and as the PU9L register, respectively, these registers can be read/written in 8-bit or 1-bit units.
(i) V850ES/KF1, V850ES/KG1
After Reset: 0000H
15
R/W
14
Address: FFFFFC52H (PU9, PU9L), FFFFFC53H (PU9H)
13 12 11 10 9 8
PU9 (PU9HNote)
PU915
PU914
PU913
0
0
0
PU99
PU98
(PU9L)
PU97
PU96
0
0
0
0
PU91
PU90
PU9n 0 1
Control of on-chip pull-up resistor connection (n = 0, 1, 6 to 9, 13 to 15) Not connected Connected
(ii) V850ES/KJ1
After Reset: 0000H
15
R/W
14
Address: FFFFFC52H (PU9, PU9L), FFFFFC53H (PU9H)
13 12 11 10 9 8
PU9 (PU9HNote)
PU915
PU914
PU913
PU912
PU911
PU910
PU99
PU98
(PU9L)
PU97
PU96
PU95
PU94
PU93
PU92
PU91
PU90
PU9n 0 1
Control of on-chip pull-up resistor connection (n = 0 to 15) Not connected Connected
Note When reading from or writing to bits 8 to 15 of the PU9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PU9H register.
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(g) External interrupt falling edge specification register 9H (INTF9H) This is an 8-bit register that specifies the falling edge as the detection edge for the external interrupt pin. This register can be read/written in 8-bit or 1-bit units. Caution When switching from the external interrupt function (alternate function) to the port function, edge detection may be performed. Therefore, set the port mode after setting INTF9n bit = INTR9n bit = 0.
(i) V850ES/KF1, V850ES/KG1, V850ES/KJ1
After Reset: 00H R/W Address: FFFFFC13H
INTF9H
INTF915 INTF914 INTF913
0
0
0
0
0
Remark
For specification of the valid edge, refer to Table 4-17.
(h) External interrupt rising edge specification register 9H (INTR9H) This is an 8-bit register that specifies the rising edge as the detection edge for the external interrupt pin. This register can be read/written in 8-bit or 1-bit units. Caution When switching from the external interrupt function (alternate function) to the port function, edge detection may be performed. Therefore, set the port mode after setting INTF9n bit = INTR9n bit = 0.
(i) V850ES/KF1, V850ES/KG1, V850ES/KJ1
After Reset: 00H R/W Address: FFFFFC33H
INTR9H
INTR915 INTR914 INTR913
0
0
0
0
0
Remark
For specification of the valid edge, refer to Table 4-17.
Table 4-17. Valid Edge Specification
INTF9n 0 0 1 1 INTR9n 0 1 0 1 Specification of valid edge (n = 13 to 15) No edge detection Rising edge Falling edge Both edges
Remark n = 13 to 15: Control of INTP4 to INTP6 pins
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(3) Block diagram (port 9) Figure 4-25. Block Diagram of P90, P92, P94, and P96
EVDD WRPU PU9 PU9n WRPFC PFC9 PFC9n WRPMC PMC9 PMC9n Output buffer OFF signal WRPM PM9 PM9n An output TXD1, TO02,TO03, TO51 input WRPORT Output latch (P9n) P-ch
Internal bus
Selector
Selector
Selector
P90/A0/TXD1/KR6, P92/A2/TI020/TO02, P94/A4/TI030/TO03, P96/A6/TI51/TO51
Selector
RD Address
KR6, TI020, TI030, TI51 input
Remarks 1. PU9: PM9: RD: WR:
Pull-up resistor option register 9 Port 9 mode register Port 9 read signal Port 9 write signal
PFC9: Port 9 function control register PMC9: Port 9 mode control register
2. n = 0, 2, 4, 6
Selector
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Figure 4-26. Block Diagram of P91
EVDD WRPU PU9 PU91 WRPFC PFC9 PFC91 WRPMC PMC9 PMC91
Internal bus
P-ch
PM9 PM91 WRPORT
Selector
A1 output Output latch (P91)
Selector
WRPM
Output buffer OFF signal
P91/A1/RXD1/KR7
Selector
RD Address
RXD1 input KR7 input
Remark
PU9: PM9: RD: WR:
Pull-up resistor option register 9 Port 9 mode register Port 9 read signal Port 9 write signal
PFC9: Port 9 function control register PMC9: Port 9 mode control register
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Figure 4-27. Block Diagram of P93, P95, P97, and P910
EVDD WRPU PU9 PU9n WRPFC PFC9 PFC9n WRPMC PMC9 PMC9n P-ch
Internal bus
PM9n WRPORT
Output latch (P9n)
Selector
Address
RD
TI021, TI031, SI01, SIA1 input
Remarks 1. PU9: PM9: RD: WR:
Pull-up resistor option register 9 Port 9 mode register Port 9 read signal Port 9 write signal
PFC9: Port 9 function control register PMC9: Port 9 mode control register
2. n = 3, 5, 7, 10
Selector
Selector
An output
Selector
WRPM
Output buffer OFF signal PM9
P93/A3/TI021, P95/A5/TI031, P97/A7/SI01, P910/A10/SIA1
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Figure 4-28. Block Diagram of P98 and P911
EVDD WRPU PU9 PU9n WRPF PF9H PF9n WRPFC PFC9 PFC9n WRPMC PMC9 PMC9n P-ch
Internal bus
PM9n An output SO01, SOA1 output WRPORT Output latch (P9n)
Selector
WRPM Output buffer OFF signal PM9
EVDD
Selector
Selector
P-ch
N-ch
P98/A8/SO01, P911/A11/SOA1
Selector
Selector
EVSS
Address
RD
Remarks 1. PU9:
Pull-up resistor option register 9
PF9H: Port 9 function register H PFC9: Port 9 function control register PM9: RD: WR: Port 9 mode register Port 9 read signal Port 9 write signal PMC9: Port 9 mode control register
2. n = 8, 11
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Figure 4-29. Block Diagram of P99 and P912
EVDD WRPU PU9 PU9n WRPF PF9H PF9n WRPFC PFC9 PFC9n WRPMC PMC9 PMC9n
Internal bus
P-ch
CSI01, CSIA1 output enable signal WRPM PM9 PM9n
Selector
A9 output
Selector
EVDD An output SCK01, SCKA1 output WRPORT Output latch (P9n)
Selector
Selector
P-ch
N-ch
P99/A9/SCK01, P912/A12/SCKA1
Selector
Selector
EVSS
Address
RD
SCK01, SCKA1 input
Remarks 1. PU9:
Pull-up resistor option register 9
PF9H: Port 9 function register H PFC9: Port 9 function control register PM9: RD: WR: Port 9 mode register Port 9 read signal Port 9 write signal PMC9: Port 9 mode control register
2. n = 9, 12
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Figure 4-30. Block Diagram of P913 to P915
EVDD WRPU PU9 PU9n WRINTR INTR9H INTR9n WRINTF INTF9H INTF9n WRPFC PFC9 PFC9n WRPMC
Internal bus
P-ch
PMC9 PMC9n
PM9 PM9n
Selector
WRPORT
An output
Selector
WRPM
Output buffer OFF signal
Output latch (P9n)
P913/A13/INTP4, P914/A14/INTP5, P915/A15/INTP6
Selector
Address
RD
INTP4 to INTP6 input
Noise eliminator Noise detector
Remarks 1. PU9: PFC9:
Pull-up resistor option register 9 Port 9 function control register
INTF9H: External interrupt falling edge specification register 9H INTR9H: External interrupt rising edge specification register 9H PM9: PMC9: RD: WR: Port 9 mode register Port 9 mode control register Port 9 read signal Port 9 write signal
2. n = 13 to 15
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4.3.10 Port CD Port CD can control input/output in 1-bit units. The number of I/O port pins for port CD differs according to the product.
Product V850ES/KF1 V850ES/KG1 V850ES/KJ1 4-bit I/O port I/O Port Pin Count - -
(1) Port CD functions (V850ES/KJ1) Port input/output data can be specified in 1-bit units. Specification is made by the port CD register (PCD). Port input/output can be specified in 1-bit units. Specification is made by the port CD mode register (PMCD). Port CD does not have alternate-function pins. Table 4-18. Alternate-Function Pins of Port CD (V850ES/KJ1)
Pin Name Port CD PCD0 PCD1 PCD2 PCD3 Alternate Function - - - - I/O I/O PULLNote No Remark -
Note Software pull-up function
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(2) Registers (a) Port CD register (PCD) The port CD register (PCD) is an 8-bit register that controls pin level read and output level write. This register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KJ1
After Reset: Undefined R/W Address: FFFFF00EH
PCD
0
0
0
0
PCD3
PCD2
PCD1
PCD0
PCDn 0 1 Output 0 Output 1
Control of output data (in output mode) (n = 0 to 3)
Remark In input mode:
When read, port CD (PCD) returns the current pin level. When written to, the data written to PCD is written. This has no influence on the input pins.
In output mode: When read, port CD (PCD) returns the PCD value. When written to, the value is written to PCD and the written value is immediately output.
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(b) Port CD mode register (PMCD) This is an 8-bit register that specifies the input mode/output mode. This register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KJ1
After Reset: FFH R/W Address: FFFFF02EH
PMCD
1
1
1
1
PMCD3
PMCD2
PMCD1
PMCD0
PMCDn 0 1 Output mode Input mode
Control of I/O mode (n = 0 to 3)
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(3) Block diagram (Port CD) Figure 4-31. Block Diagram of PCD0 to PCD3
WRPM PMCD PMCDn WRPORT Output latch (PCDn) PCD0, PCD1, PCD2, PCD3
Internal bus
Selector
Address
RD
Remarks 1. PMCD: Port CD mode register RD: WR: Port CD read signal Port CD write signal
2. n = 0 to 3
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4.3.11 Port CM Port CM can control input/output in 1-bit units. The number of I/O port pins for port CM differs according to the product.
Product V850ES/KF1 V850ES/KG1 V850ES/KJ1 I/O Port Pin Count 4-bit I/O port 4-bit I/O port 6-bit I/O port
(1) Port CM functions Port input/output data can be specified in 1-bit units. Specification is made by the port CM register (PCM). Port input/output can be specified in 1-bit units. Specification is made by the port CM mode register (PMCM). Port mode/control mode (alternate functions) can be specified 1-bit units. Specification is made by the port CM mode control register (PMCCM). Port CM includes the following alternate functions. Table 4-19. Alternate-Function Pins of Port CM (V850ES/KF1, V850ES/KG1)
Pin Name Port CM PCM0 PCM1 PCM2 PCM3 Alternate Function WAIT CLKOUT HLDAK HLDQR I/O I/O PULLNote No Remark -
Note Software pull-up function Table 4-20. Alternate-Function Pins of Port CM (V850ES/KJ1)
Pin Name Port CM PCM0 PCM1 PCM2 PCM3 PCM4 PCM5 Alternate Function WAIT CLKOUT HLDAK HLDQR - - I/O I/O PULLNote No Remark -
Note Software pull-up function
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(2) Registers (a) Port CM register (PCM) The port CM register (PCM) is an 8-bit register that controls pin level read and output level write. This register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KF1, v850ES/KG1
After Reset: Undefined R/W Address: FFFFF00CH
PCM
0
0
0
0
PCM3
PCM2
PCM1
PCM0
PCMn 0 1 Output 0 Output 1
Control of output data (in output mode) (n = 0 to 3)
(ii) V850ES/KJ1
After Reset: Undefined R/W Address: FFFFF00CH
PCM
0
0
PCM5
PCM4
PCM3
PCM2
PCM1
PCM0
PCMn 0 1 Output 0 Output 1
Control of output data (in output mode) (n = 0 to 5)
Remark In input mode:
When read, port CM (PCM) returns the current pin level. When written to, the data written to PCM is written. This has no influence on the input pins.
In output mode: When read, port CM (PCM) returns the PCM value. When written to, the value is written to PCM and the written value is immediately output.
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(b) Port CM mode register (PMCM) This is an 8-bit register that specifies the input mode/output mode. This register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KF1, V850ES/KG1
After Reset: FFH R/W Address: FFFFF02CH
PMCM
1
1
1
1
PMCM3
PMCM2
PMCM1
PMCM0
PMCMn 0 1 Output mode Input mode
Control of I/O mode (n = 0 to 3)
(ii) V850ES/KJ1
After Reset: FFH R/W Address: FFFFF02CH
PMCM
1
1
PMCM5
PMCM4
PMCM3
PMCM2
PMCM1
PMCM0
PMCMn 0 1 Output mode Input mode
Control of I/O mode (n = 0 to 5)
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(c) Port CM mode control register (PMCCM) This is an 8-bit register that specifies the port mode/control mode. This register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KF1, V850ES/KG1, V850ES/KJ1
After Reset: 00H R/W Address: FFFFF04CH
PMCCM
0
0
0
0
PMCCM3 PMCCM2 PMCCM1 PMCCM0
PMCCM3 0 1 PMCCM2 0 1 PMCCM1 0 1 PMCCM0 0 1 I/O port WAIT input I/O port CLKOUT output I/O port HLDAK output I/O port HLDQR input
Specification of PCM3 pin operation mode
Specification of PCM2 pin operation mode
Specification of PCM1 pin operation mode
Specification of PCM0 pin operation mode
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(3) Block diagram (Port CM) Figure 4-32. Block Diagram of PCM0 and PCM3
WRPMC PMCCM PMCCMn
WRPM PMCM PMCMn
Internal bus
WRPORT Output latch (PCMn)
PCM0/WAIT, PCM3/HLDRQ
Selector
Address
RD
WAIT, HLDRQ input
Remarks 1. PMCM: RD: WR: 2. n = 0, 3
Port CM mode register Port CM read signal Port CM write signal
PMCCM: Port CM mode control register
Selector
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Figure 4-33. Block Diagram of PCM1 and PCM2
WRPMC PMCCM PMCCMn WRPM PMCM PMCMn
Internal bus
CLKOUT, HLDAK output signal
Selector
WRPORT Output latch (PCMn)
PCM1/CLKOUT, PCM2/HLDAK
Selector
Address
RD
Remarks 1. PMCM: RD: WR: 2. n = 1, 2
Port CM mode register Port CM read signal Port CM write signal
PMCCM: Port CM mode control register
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Figure 4-34. Block Diagram of PCM4 and PCM5
WRPM PMCM PMCMn WRPORT Output latch (PCMn)
Internal bus
PCM4, PCM5
Selector
Address
RD
Remarks 1. PMCM: Port CM mode register RD: WR: 2. n = 4, 5 Port CM read signal Port CM write signal
Selector
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4.3.12 Port CS Port CS can control input/output in 1-bit units. The number of I/O port pins for port CS differs according to the product.
Product V850ES/KF1 V850ES/KG1 V850ES/KJ1 I/O Port Pin Count 2-bit I/O port 2-bit I/O port 8-bit I/O port
(1) Port CS functions Port input/output data can be specified in 1-bit units. Specification is made by the port CS register (PCS). Port input/output can be specified in 1-bit units. Specification is made by the port CS mode register (PMCS). Port mode/control mode (alternate functions) can be specified 1-bit units. Specification is made by the port CS mode control register (PMCCS). Port CS includes the following alternate functions. Table 4-21. Alternate-Function Pins of Port CS (V850ES/KF1, V850ES/KG1)
Pin Name Port CS PCS0 PCS1 Alternate Function CS0 CS1 I/O I/O PULLNote No Remark -
Note Software pull-up function Table 4-22. Alternate-Function Pins of Port CS (V850ES/KJ1)
Pin Name Port CS PCS0 PCS1 PCS2 PCS3 PCS4 PCS5 PCS6 PCS7 Alternate Function CS0 CS1 CS2 CS3 - - - - I/O I/O PULLNote No Remark -
Note Software pull-up function
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(2) Registers (a) Port CS register (PCS) The port CS register (PCS) is an 8-bit register that controls pin level read and output level write. This register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KF1, V850ES/KG1
After Reset: Undefined R/W Address: FFFFF008H
PCS
0
0
0
0
0
0
PCS1
PCS0
PCSn 0 1 Output 0 Output 1
Control of output data (in output mode) (n = 0, 1)
(ii) V850ES/KJ1
After Reset: Undefined R/W Address: FFFFF008H
PCS
PCS7
PCS6
PCS5
PCS4
PCS3
PCS2
PCS1
PCS0
PCSn 0 1 Output 0 Output 1
Control of output data (in output mode) (n = 0 to 7)
Remark In input mode:
When read, port CS (PCS) returns the current pin level. When written to, the data written to PCS is written. This has no influence on the input pins.
In output mode: When read, port CS (PCS) returns the PCS value. When written to, the value is written to PCS and the written value is immediately output.
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(b) Port CS mode register (PMCS) This is an 8-bit register that specifies the input mode/output mode. This register can be written in 8-bit or 1-bit units.
(i) V850ES/KF1, V850ES/KG1
After Reset: FFH R/W Address: FFFFF028H
PMCS
1
1
1
1
1
1
PMCS1
PMCS0
PMCSn 0 1 Output mode Input mode
Control of I/O mode (n = 0, 1)
(ii) V850ES/KJ1
After Reset: FFH R/W Address: FFFFF028H
PMCS
PMCS7
PMCS6
PMCS5
PMCS4
PMCS3
PMCS2
PMCS1
PMCS0
PMCSn 0 1 Output mode Input mode
Control of I/O mode (n = 0 to 7)
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(c) Port CS mode control register (PMCCS) This is an 8-bit register that specifies the port mode/control mode. This register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KF1, V850ES/KG1
After Reset: 00H R/W Address: FFFFF048H
PMCCS
0
0
0
0
0
0
PMCCS1 PMCCS0
PMCCSn 0 1 I/O port CSn output
Specification of PCSn pin operation mode (n = 0, 1)
(ii) V850ES/KJ1
After Reset: 00H R/W Address: FFFFF048H
PMCCS
0
0
0
0
PMCCS3 PMCCS2 PMCCS1 PMCCS0
PMCCSn 0 1 I/O port
Specification of PCSn pin operation mode (n = 0 to 3)
CSn output
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(3) Block diagram (port CS) Figure 4-35. Block Diagram of PCS0 to PCS3
WRPMC PMCCS PMCCSn
PMCS PMCSn
Internal bus
Output latch (PCSn)
Selector
Address
RD
Remarks 1. PMCS: RD: WR:
Port CS mode register Port CS read signal Port CS write signal
PMCCS: Port CS mode control register
2. n = 0 to 3
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Selector
WRPORT
CSn output
Selector
WRPM
Output buffer OFF signal
PCS0/CS0, PCS1/CS1, PCS2/CS2, PCS3/CS3
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Figure 4-36. Block Diagram of PCS4 to PCS7
WRPM PMCS PMCSn WRPORT PCS4, PCS5, PCS6, PCS7
Output latch (PCSn)
Internal bus
Selector
Address
RD
Remarks 1. PMCS: Port CS mode register 2. n = 4 to 7
Selector
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4.3.13 Port CT Port CT can control input/output in 1-bit units. The number of I/O port pins for port CT differs according to the product.
Product V850ES/KF1 V850ES/KG1 V850ES/KJ1 I/O Port Pin Count 4-bit I/O port 4-bit I/O port 8-bit I/O port
(1) Port CT functions Port input/output data can be specified in 1-bit units. Specification is made by the port CT register (PCT). Port input/output can be specified in 1-bit units. Specification is made by the port CT mode register (PMCT). Port mode/control mode (alternate functions) can be specified 1-bit units. Specification is made by the port CT mode control register (PMCCT). Port CT includes the following alternate functions. Table 4-23. Alternate-Function Pins of Port CT (V850ES/KF1, V850ES/KG1)
Pin Name Port CT PCT0 PCT1 PCT4 PCT6 Alternate Function WR0 WR1 RD ASTB I/O I/O PULLNote No Remark -
Note Software pull-up function Table 4-24. Alternate-Function Pins of Port CT (V850ES/KJ1)
Pin Name Port CT PCT0 PCT1 PCT2 PCT3 PCT4 PCT5 PCT6 PCT7 ASTB - RD - Alternate Function WR0 WR1 - - I/O I/O PULLNote No Remark -
Note Software pull-up function
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(2) Registers (a) Port CT register (PCT) The port CT register (PCT) is an 8-bit register that controls pin level read and output level write. This register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KF1, V850ES/KG1
After Reset: Undefined R/W Address: FFFFF00AH
PCT
0
PCT6
0
PCT4
0
0
PCT1
PCT0
PCTn 0 1 Output 0 Output 1
Control of output data (in output mode) (n = 0, 1, 4, 6)
(ii) V850ES/KJ1
After Reset: Undefined R/W Address: FFFFF00AH
PCT
PCT7
PCT6
PCT5
PCT4
PCT3
PCT2
PCT1
PCT0
PCTn 0 1 Output 0 Output 1
Control of output data (in output mode) (n = 0 to 7)
Remark In input mode:
When read, port CT (PCT) returns the current pin level. When written to, the data written to PCT is written. This has no influence on the input pins.
In output mode: When read, port CT (PCT) returns the PCT value. When written to, the value is written to PCT and the written value is immediately output.
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(b) Port CT mode register (PMCT) This is an 8-bit register that specifies the input mode/output mode. This register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KF1, V850ES/KG1
After Reset: FFH R/W Address: FFFFF02AH
PMCT
1
PMCT6
1
PMCT4
1
1
PMCT1
PMCT0
PMCTn 0 1 Output mode Input mode
Control of I/O mode (n = 0, 1, 4, 6)
(ii) V850ES/KJ1
After Reset: FFH R/W Address: FFFFF02AH
PMCT
PMCT7
PMCT6
PMCT5
PMCT4
PMCT3
PMCT2
PMCT1
PMCT0
PMCTn 0 1 Output mode Input mode
Control of I/O mode (n = 0 to 7)
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(c) Port CT mode control register (PMCCT) This is an 8-bit register that specifies the port mode/control mode. This register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KF1, V850ES/KG1, V850ES/KJ1
After Reset: 00H R/W Address: FFFFF04AH
PMCCT
0
PMCCT6
0
PMCCT4
0
0
PMCCT1 PMCCT0
PMCCT6 0 1 PMCCT4 0 1 PMCCT1 0 1 PMCCT0 0 1 I/O port WR0 output I/O port WR1 output I/O port RD output I/O port ASTB output
Specification of PCT6 pin operation mode
Specification of PCT4 pin operation mode
Specification of PCT1 pin operation mode
Specification of PCT0 pin operation mode
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(3) Block diagram (port CT) Figure 4-37. Block Diagram of PCT0, PCT1, PCT4, and PCT6
WRPMC PMCCT PMCCTn
PMCT PMCTn
Internal bus
Output latch (PCTn)
Selector
Address
RD
Remarks 1. PMCT: RD: WR:
Port CT mode register Port CT read signal Port CT write signal
PMCCT: Port CT mode control register
2. n = 0, 1, 4, 6
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Selector
Selector
WRPORT
WR0, WR1, RD, ASTB output
Selector
WRPM
Output buffer OFF signal
PCT0/WR0, PCT1/WR1, PCT4/RD, PCT6/ASTB
CHAPTER 4 PORT FUNCTIONS
Figure 4-38. Block Diagram of PCT2, PCT3, PCT5, and PCT7
WRPM PMCT PMCTn WRPORT PCT2, PCT3, PCT5, PCT7
Output latch (PCTn)
Internal bus
Selector
Address
RD
Remarks 1. PMCT: Port CT mode register RD: WR: Port CM read signal Port CM write signal
2. n = 2, 3, 5, 7
Selector
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CHAPTER 4 PORT FUNCTIONS
4.3.14 Port DH Port DH can control input/output in 1-bit units. The number of I/O port pins for port DH differs according to the product.
Product V850ES/KF1 V850ES/KG1 V850ES/KJ1 6-bit I/O port 8-bit I/O port I/O Port Pin Count -
(1) Port DH functions (V850ES/KG1, V850ES/KJ1) Port input/output data can be specified in 1-bit units. Specification is made by the port DH register (PDH). Port input/output can be specified in 1-bit units. Specification is made by the port DH mode register (PMDH). Port mode/control mode (alternate functions) can be specified 1-bit units. Specification is made by the port DH mode control register (PMCDH). Port DH includes the following alternate functions. Table 4-25. Alternate-Function Pins of Port DH (V850ES/KG1)
Pin Name Port DH PDH0 PDH1 PDH2 PDH3 PDH4 PDH5 Alternate Function A16 A17 A18 A19 A20 A21 I/O I/O PULLNote No Remark -
Note Software pull-up function Table 4-26. Alternate-Function Pins of Port DH (V850ES/KJ1)
Pin Name Port DH PDH0 PDH1 PDH2 PDH3 PDH4 PDH5 PDH6 PDH7 Alternate Function A16 A17 A18 A19 A20 A21 A22 A23 I/O I/O PULLNote No Remark -
Note Software pull-up function
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CHAPTER 4 PORT FUNCTIONS
(2) Registers (a) Port DH register (PDH) The port DH register (PDH) is an 8-bit register that controls pin level read and output level write. This register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KG1
After Reset: Undefined R/W Address: FFFFF006H
PDH
0
0
PDH5
PDH4
PDH3
PDH2
PDH1
PDH0
PDHn 0 1 Output 0 Output 1
Control of output data (in output mode) (n = 0 to 5)
(ii) V850ES/KJ1
After Reset: Undefined R/W Address: FFFFF006H
PDH
PDH7
PDH6
PDH5
PDH4
PDH3
PDH2
PDH1
PDH0
PDHn 0 1 Output 0 Output 1
Control of output data (in output mode) (n = 0 to 7)
Remark In input mode:
When read, port DH (PDH) returns the current pin level. When written to, the data written to PDH is written. This has no influence on the input pins.
In output mode: When read, port DH (PDH) returns the PDH value. When written to, the value is written to PDH and the written value is immediately output.
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CHAPTER 4 PORT FUNCTIONS
(b) Port DH mode register (PMDH) This is an 8-bit register that specifies the input mode/output mode. This register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KG1
After Reset: FFH R/W Address: FFFFF026H
PMDH
1
1
PMDH5
PMDH4
PMDH3
PMDH2
PMDH1
PMDH0
PMDHn 0 1 Output mode Input mode
Control of I/O mode (n = 0 to 5)
(ii) V850ES/KJ1
After Reset: FFH R/W Address: FFFFF026H
PMDH
PMDH7
PMDH6
PMDH5
PMDH4
PMDH3
PMDH2
PMDH1
PMDH0
PMDHn 0 1 Output mode Input mode
Control of I/O mode (n = 0 to 7)
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CHAPTER 4 PORT FUNCTIONS
(c) Port DH mode control register (PMCDH) This is an 8-bit register that specifies the port mode/control mode. This register can be read/written in 8-bit or 1-bit units.
(i) V850ES/KG1
After Reset: 00H R/W Address: FFFFF046H
PMCDH
0
0
PMCDH5 PMCDH4 PMCDH3 PMCDH2 PMCDH1 PMCDH0
PMCDHn 0 1 I/O port
Specification of PDHn pin operation mode (n = 0 to 5)
Am output (address bus output) (m = 16 to 21)
Caution When specifying the port mode/control mode (alternate function) for each bit, pay careful attention to the operation of the alternate functions. (ii) V850ES/KJ1
After Reset: 00H R/W Address: FFFFF046H
PMCDH
PMCDH7 PMCDH6 PMCDH5 PMCDH4 PMCDH3 PMCDH2 PMCDH1 PMCDH0
PMCDHn 0 1 I/O port
Specification of PDHn pin operation mode (n = 0 to 7)
Am output (address bus output) (m = 16 to 23)
Caution When specifying the port mode/control mode (alternate function) for each bit, pay careful attention to the operation of the alternate functions.
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CHAPTER 4 PORT FUNCTIONS
(3) Block diagram (Port DH) Figure 4-39. Block Diagram of PDH0 to PDH7
WRPMC PMCDH PMCDHn
PMDH PMDHn
Internal bus
Selector
WRPM
Output buffer OFF signal
Output latch (PCHn)
Selector
Address
RD
Remarks 1. PMDH: RD: WR: 2. n = 0 to 7
Port DH mode register Port DH read signal Port DH write signal
PMCDH: Port DH mode control register
m = 16 to 23
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Selector
Selector
WRPORT
Am output
PDH0/A16, PDH1/A17, PDH2/A18, PDH3/A19, PDH4/A20, PDH5/A21, PDH6/A22, PDH7/A23
CHAPTER 4 PORT FUNCTIONS
4.3.15 Port DL Port DL can control input/output in 1-bit units. The number of I/O port pins for port 1 differs according to the product.
Product V850ES/KF1 V850ES/KG1 V850ES/KJ1 I/O Port Pin Count 16-bit I/O port 16-bit I/O port 16-bit I/O port
(1) Port DL functions Port input/output data can be specified in 1-bit units. Specification is made by the port DL register (PDL). Port input/output can be specified in 1-bit units. Specification is made by the port DL mode register (PMDL). Port mode/control mode (alternate function) can be specified in 1-bit units. Specification is made by the port DL mode control register (PMCDL). Port DL includes the following alternate functions. Table 4-27. Alternate-Function Pins of Port DL
Pin Name Port DL PDL0 PDL1 PDL2 PDL3 PDL4 PDL5 PDL6 PDL7 PDL8 PDLDL PDL10 PDL11 PDL12 PDL13 PDL14 PDL15 Alternate Function AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 I/O I/O PULLNote No Remark -
Note Software pull-up function
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CHAPTER 4 PORT FUNCTIONS
(2) Registers (a) Port DL register (PDL) The port DL register (PDL) is an 16-bit register that controls pin level read and output level write. This register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the PDL register are used as the PDLH register and as the PDLL register, respectively, these registers can be read/written in 8-bit or 1-bit units.
After Reset: Undefined
15 14
R/W
Address: FFFFF004H (PDL, PDLL), FFFFF005H (PDLH)
13 12 11 10 9 8
PDL (PDLHNote)
PDL15
PDL14
PDL13
PDL12
PDL11
PDL10
PDL9
PDL8
(PDLL)
PDL7
PDL6
PDL5
PDL4
PDL3
PDL2
PDL1
PDL0
PDLn 0 1 Outputs 0 Outputs 1
Control of output data (in output mode) (n = 0 to 15)
Note When reading from or writing to bits 8 to 15 of the PDL register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PDLH register. Remark In input mode: When read, port DL (PDL) returns the current pin level. When written to, the data written to PDL is written. This has no influence on the input pins. In output mode: When read, port DL (PDL) returns the PDL value. When written to, the value is written to PDL and the written value is immediately output.
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(b) Port DL mode register (PMDL) This is a 16-bit register that specifies the input mode/output mode. This register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the PMDL register are used as the PMDLH register and as the PMDLL register, respectively, these registers can be read/written in 8-bit or 1-bit units.
After Reset: FFFFH
15
R/W
14
Address: FFFFF024H (PMDL, PMDLL), FFFFF025H (PMDLH)
13 12 11 10 9 8
PMDL (PMDLH
Note
)
PMDL15 PMDL14 PMDL13 PMDL12 PMDL11 PMDL10
PMDL9
PMDL8
(PMDLL)
PMDL7
PMDL6
PMDL5
PMDL4
PMDL3
PMDL2
PMDL1
PMDL0
PMDLn 0 1 Output mode Input mode
Control of I/O mode (n = 0 to 15)
Note When reading from or writing to bits 8 to 15 of the PMDL register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PMDLH register.
(c) Port DL mode control register (PMCDL) This is a 16-bit register that specifies the port mode/control mode. This register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the PMCDL register are used as the PMCDLH register and as the PMCDLL register, respectively, these registers can be read/written in 8-bit or 1-bit units.
After Reset: 0000H
15
R/W
14
Address: FFFFF044H (PMCDL, PMCDLL), FFFFF045H (PMCDLH)
13 12 11 10 9 8
PMCDL (PMCDLH
Note
)
PMCDL15 PMCDL14 PMCDL13 PMCDL12 PMCDL11PMCDL10 PMCDL9 PMCDL8
(PMCDLL)
PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0
PMCDLn 0 1 I/O port
Specification of PDLn pin operation mode (n = 0 to 15)
ADn I/O (address/data bus I/O)
Note When reading from or writing to bits 8 to 15 of the PMCDL register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PMCDLH register. Caution When specifying the port mode/control mode (alternate function) for each bit, pay careful attention to the operation of the alternate functions.
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CHAPTER 4 PORT FUNCTIONS
(3) Block diagram (Port DL) Figure 4-40. Block Diagram of PDL0 to PDL15
WRPMC PMCDL PMCDLn Output enable signal for address/data bus
Selector
WRPM
Output buffer OFF signal PMDL PMDLn
Output latch (PDLn)
Selector
Address Input enable signal for address/data bus
RD
ADn input
Remarks 1. PMDL: Port DL mode register PMCDL: Port DL mode control register RD: WR: Port DL read signal Port DL write signal
2. n = 0 to 15
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Selector
Selector
WRPORT
ADn output
PDL0/AD0, PDL1/AD1, PDL2/AD2, PDL3/AD3, PDL4/AD4, PDL5/AD5, PDL6/AD6, PDL7/AD7, PDL8/AD8, PDL9/AD9, PDL10/AD10, PDL11/AD11, PDL12/AD12, PDL13/AD13, PDL14/AD14, PDL15/AD15
Internal bus
Table 4-28. Settings When Port Pins Are Used for Alternate Functions (1/7)
Pin Name Alternate Function Function Name P00 P01 P02 P03 P04 P05 P06 P10 P11 P30 P31 P32 P33
User's Manual U15862EJ3V0UD
Pnx Bit of Pn Register
PMnx Bit of PMn Register
PMCnx Bit of
PFCnx Bit of
Other Bits (Registers)
I/O Output Output Input Input Input Input Input Output Output Output Input Input Input Output Input Input Output P00 = Setting not required P01 = Setting not required P02 = Setting not required P03 = Setting not required P04 = Setting not required P05 = Setting not required P06 = Setting not required P10 = Setting not required P11 = Setting not required P30 = Setting not required P31 = Setting not required P32 = Setting not required P33 = Setting not required P33 = Setting not required P34 = Setting not required P35 = Setting not required P35 = Setting not required P38 = Setting not required P39 = Setting not required P40 = Setting not required P41 = Setting not required P42 = Setting not required PM00 = Setting not required PM01 = Setting not required PM02 = Setting not required PM03 = Setting not required PM04 = Setting not required PM05 = Setting not required PM06 = Setting not required PM10 = 1
Note 1
PMCn Register PFCn Register PMC00 = 1 PMC01 = 1 PMC02 = 1 PMC03 = 1 PMC04 = 1 PMC05 = 1 PMC06 = 1 - - PMC30 = 1 PMC31 = 1 PMC32 = 1 PMC33 = 1 PMC33 = 1 PMC34 = 1 PMC35 = 1 PMC35 = 1 PMC38 = 1 PMC39 = 1 PMC40 = 1 PMC41 = 1 PMC42 = 1 - - - - - - - - - - - - PFC33 = 0 PFC33 = 1 - PFC35 = 0 PFC35 = 1 - - - - - - - INTR02 (INTR0), INTF02 (INTF0) INTR03 (INTR0), INTF03 (INTF0) INTR04 (INTR0), INTF04 (INTF0) INTR05 (INTR0) ,INTF05 (INTF0) INTR06 (INTR0), INTF06 (INTF0) - - - - - - - - - - PF38 (PF3) = 1 PF39 (PF3) = 1 - PF41 (PF4) = Don't care PF42 (PF4) = Don't care CHAPTER 4 PORT FUNCTIONS
TOH0 TOH1 NMI INTP0 INTP1 INTP2 INTP3 ANO0 ANO1 TXD0 RXD0 ASCK0 TI000 TO00
PM11 = 1
Note 1
PM30 = Setting not required PM31 = Setting not required PM32 = Setting not required PM33 = Setting not required PM33 = Setting not required PM34 = Setting not required PM35 = Setting not required PM35 = Setting not required PM38 = Setting not required PM39 = Setting not required PM40 = Setting not required PM41 = Setting not required PM42 = Setting not required
P34 P35
TI001 TI010 TO01
P38 P39 P40 P41 P42
SDA0 SCL0 SI00 SO00
Note 2
I/O I/O Input Output I/O
Note 2
SCK00
Notes 1. When setting the ANO0 and ANO1 pins, set PM1 register = FFH at one time. 2. Only for products with an I C bus
2
255
256
Pin Name Alternate Function Function Name P50 TI011 RTP00 KR0 P51 TI50 RTP01 KR1 P52 TO50 RTP02 KR2 P53 SIA0 RTP03 KR3 P54 SOA0 RTP04 KR4 P55 SCKA0 RTP05 KR5
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Table 4-28. Settings When Port Pins Are Used for Alternate Functions (2/7)
Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers)
I/O Input Output Input Input Output Input Output Output Input Input Output Input Output Output Input I/O Output Input P50 = Setting not required P50 = Setting not required P50 = Setting not required P51 = Setting not required P51 = Setting not required P51 = Setting not required P52 = Setting not required P52 = Setting not required P52 = Setting not required P53 = Setting not required P53 = Setting not required P53 = Setting not required P54 = Setting not required P54 = Setting not required P54 = Setting not required P55 = Setting not required P55 = Setting not required P55 = Setting not required PM50 = Setting not required PM50 = Setting not required PM50 = 1 PM51 = Setting not required PM51 = Setting not required PM51 = 1 PM52 = Setting not required PM52 = Setting not required PM52 = 1 PM53 = Setting not required PM53 = Setting not required PM53 = 1 PM54 = Setting not required PM54 = Setting not required PM54 = 1 PM55 = Setting not required PM55 = Setting not required PM55 = 1
PMCn Register PFCn Register PMC50 = 1 PMC50 = 1 PMC50 = 0 PMC51 = 1 PMC51 = 1 PMC51 = 0 PMC52 = 1 PMC52 = 1 PMC52 = 0 PMC53 = 1 PMC53 = 1 PMC53 = 0 PMC54 = 1 PMC54 = 1 PMC54 = 0 PMC55 = 1 PMC55 = 1 PMC55 = 0 PFC50 = 0 PFC50 = 1 PFC50 = 0 PFC51 = 0 PFC51 = 1 PFC51 = 0 PFC52 = 0 PFC52 = 1 PFC52 = 0 PFC53 = 0 PFC53 = 1 PFC53 = 0 PFC54 = 0 PFC54 = 1 PFC54 = 0 PFC55 = 0 PFC55 = 1 PFC55 = 0 - - KRM0 (KRM) = 1 - - KRM1 (KRM) = 1 - - KRM2 (KRM) = 1 - - KRM3 (KRM) = 1 PF54 (PF5) = Don't care PF54 (PF5) = 0 PF54 (PF5) = 0, KRM4 (KRM) = 1 PF55 (PF5) = Don't care PF55 (PF5) = 0 PF55 (PF5) = 0, KRM5 (KRM) = 1 CHAPTER 4 PORT FUNCTIONS
Table 4-28. Settings When Port Pins Are Used for Alternate Functions (3/7)
Pin Name Alternate Function Function Name P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P610 P611 P612 P613
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Pnx Bit of Pn Register
PMnx Bit of PMn Register
PMCnx Bit of
PFCnx Bit of
Other Bits (Registers)
I/O Output Output Output Output Output Output Input Output I/O Input Input Output Input Input Output P60 = Setting not required P61 = Setting not required P62 = Setting not required P63 = Setting not required P64 = Setting not required P65 = Setting not required P66 = Setting not required P67 = Setting not required P68 = Setting not required P69 = Setting not required P610 = Setting not required P611 = Setting not required P612 = Setting not required P613 = Setting not required P613 = Setting not required PM60 = Setting not required PM61 = Setting not required PM62 = Setting not required PM63 = Setting not required PM64 = Setting not required PM65 = Setting not required PM66 = Setting not required PM67 = Setting not required PM68 = Setting not required PM69 = Setting not required PM610 = Setting not required PM611 = Setting not required PM612 = Setting not required PM613 = Setting not required PM613 = Setting not required
PMCn Register PFCn Register PMC60 = 1 PMC61 = 1 PMC62 = 1 PMC63 = 1 PMC64 = 1 PMC65 = 1 PMC66 = 1 PMC67 = 1 PMC68 = 1 PMC69 = 1 PMC610 = 1 PMC611 = 1 PMC612 = 1 PMC613 = 1 PMC613 = 1 - - - - - - - - - - - - - PFC613 = 0 PFC613 = 1 - - - - - - - PF67 (PF6) = Don't care PF68 (PF6) = Don't care - - - - - - CHAPTER 4 PORT FUNCTIONS
RTP10 RTP11 RTP12 RTP13 RTP14 RTP15 SI02 SO02 SCK02 TI040 TI041 TO04 TI050 TI051 TO05
257
258
Pin Name Alternate Function Function Name P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P710 P711 P712 P713 P714 P715 P80
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Table 4-28. Settings When Port Pins Are Used for Alternate Functions (4/7)
Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers)
I/O Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input I/O Output I/O P70 = Setting not required P71 = Setting not required P72 = Setting not required P73 = Setting not required P74 = Setting not required P75 = Setting not required P76 = Setting not required P77 = Setting not required P78 = Setting not required P79 = Setting not required P710 = Setting not required P711 = Setting not required P712 = Setting not required P713 = Setting not required P714 = Setting not required P715 = Setting not required P80 = Setting not required P80 = Setting not required P81 = Setting not required P81 = Setting not required - - - - - - - - - - - - - - - - PM80 = Setting not required PM80 = Setting not required PM81 = Setting not required PM81 = Setting not required
PMCn Register PFCn Register - - - - - - - - - - - - - - - - PMC80 = 1 PMC80 = 1 PMC81 = 1 PMC81 = 1 - - - - - - - - - - - - - - - - PFC80 = 0 PFC80 = 1 PFC81 = 0 PFC81 = 1 - - - - - - - - - - - - - - - - PF80 (PF8) = 0 PF80 (PF8) = 1 PF80 (PF8) = 0 PF81 (PF8) = 1 CHAPTER 4 PORT FUNCTIONS
ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANI12 ANI13 ANI14 ANI15 RXD2 SDA1
Note 1
P81
TXD2 SCL1
Note 1
Note Only for the PD703216Y, 703217Y, and 70F3217Y
Table 4-28. Settings When Port Pins Are Used for Alternate Functions (5/7)
Pin Name Alternate Function Function Name P90 A0 TXD1 KR6 P91 A1 RXD1 KR7 P92 A2 TI020 TO02 P93 A3 TI021 P94 A4 TI030 TO03 P95 A5 TI031 P96 A6 TI51 TO51 P97 A7 SI01 P98 A8 SO01 P99 A9 SCK01
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Pnx Bit of Pn Register
PMnx Bit of PMn Register
PMCnx Bit of
PFCnx Bit of
Other Bits (Registers)
I/O Output Output Input Output Input Input Output Input Output Output Input Output Input Output Output Input Output Input Output Output Input Output Output Output I/O P90 = Setting not required P90 = Setting not required P90 = Setting not required P91 = Setting not required P91 = Setting not required P91 = Setting not required P92 = Setting not required P92 = Setting not required P92 = Setting not required P93 = Setting not required P93 = Setting not required P94 = Setting not required P94 = Setting not required P94 = Setting not required P95 = Setting not required P95 = Setting not required P96 = Setting not required P96 = Setting not required P96 = Setting not required P97 = Setting not required P97 = Setting not required P98 = Setting not required P98 = Setting not required P99 = Setting not required P99 = Setting not required PM90 = Setting not required PM90 = Setting not required PM90 = 1 PM91 = Setting not required PM91 = Setting not required PM91 = 1 PM92 = Setting not required PM92 = Setting not required PM92 = Setting not required PM93 = Setting not required PM93 = Setting not required PM94 = Setting not required PM94 = 1 PM94 = Setting not required PM95 = Setting not required PM95 = Setting not required PM96 = Setting not required PM96 = 1 PM96 = Setting not required PM97 = Setting not required PM97 = Setting not required PM98 = Setting not required PM98 = Setting not required PM99 = Setting not required PM99 = Setting not required
PMCn Register PFCn Register PMC90 = 1 PMC90 = 1 PMC90 = 0 PMC91 = 1 PMC91 = 1 PMC91 = 0 PMC92 = 1 PMC92 = 0 PMC92 = 1 PMC93 = 1 PMC93 = 1 PMC94 = 1 PMC94 = 0 PMC94 = 1 PMC95 = 1 PMC95 = 1 PMC96 = 1 PMC96 = 0 PMC96 = 1 PMC97 = 1 PMC97 = 1 PMC98 = 1 PMC98 = 1 PMC99 = 1 PMC99 = 1 PFC90 = 0 PFC90 = 1 PFC90 = 0 PFC91 = 0 PFC91 = 1 PFC91 = 0 PFC92 = 0 PFC92 = 0 PFC92 = 1 PFC93 = 0 PFC93 = 1 PFC94 = 0 PFC94 = 0 PFC94 = 1 PFC95 = 0 PFC95 = 1 PFC96 = 0 PFC96 = 0 PFC96 = 1 PFC97 = 0 PFC97 = 1 PFC98 = 0 PFC98 = 1 PFC99 = 0 PFC99 = 1 Note, PF98 (PF9) = 0 PF98 (PF9) = Don't care Note, PF98 (PF9) = 0 PF98 (PF9) = Don't care Note - KRM6 (KRM) = 1 Note - KRM7 (KRM) = 1 Note - - Note - Note - - Note - Note - - Note CHAPTER 4 PORT FUNCTIONS
Note When setting the A0 to A15 pins, perform 16-bit setting of PFC9 register = 0000H and PMC9 register = FFFFH at one time.
259
260
Pin Name Alternate Function Function Name P910 A10 SIA1 P911 A11 SOA1 P912 A12 SCKA1 P913 A13 INTP4 P914 A14 INTP5 P915 A15 INTP6 PCM0 PCM1 PCM2 PCM3 PCS0 PCS1 PCS2 PCS3 PCT0 PCT1 PCT4 PCT6 WAIT CLKOUT HLDAK HLDQR CS0 CS1 CS2 CS3 WR0 WR1 RD ASTB
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Table 4-28. Settings When Port Pins Are Used for Alternate Functions (6/7)
Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers)
I/O Output Input Output Output Output I/O Output Input Output Input Output Input Input Output Output Input Output Output Output Output Output Output Output Output P910 = Setting not required P910 = Setting not required P911 = Setting not required P911 = Setting not required P912 = Setting not required P912 = Setting not required P913 = Setting not required P913 = Setting not required P914 = Setting not required P914 = Setting not required P915 = Setting not required P915 = Setting not required PCM0 = Setting not required PCM1 = Setting not required PCM2 = Setting not required PCM3 = Setting not required PCS0 = Setting not required PCS1 = Setting not required PCS2 = Setting not required PCS3 = Setting not required PCT0 = Setting not required PCT1 = Setting not required PCT4 = Setting not required PCT6 = Setting not required PM910 = Setting not required PM910 = Setting not required PM911 = Setting not required PM911 = Setting not required PM912 = Setting not required PM912 = Setting not required PM913 = Setting not required PM913 = Setting not required PM914 = Setting not required PM914 = Setting not required PM915 = Setting not required PM915 = Setting not required PMCM0 = Setting not required PMCM1 = Setting not required PMCM2 = Setting not required PMCM3 = Setting not required PMCS0 = Setting not required PMCS1 = Setting not required PMCS2 = Setting not required PMCS3 = Setting not required PMCT0 = Setting not required PMCT1 = Setting not required PMCT4 = Setting not required PMCT6 = Setting not required
PMCn Register PFCn Register PMC910 = 1 PMC910 = 1 PMC911 = 1 PMC911 = 1 PMC912 = 1 PMC912 = 1 PMC913 = 1 PMC913 = 1 PMC914 = 1 PMC914 = 1 PMC915 = 1 PMC915 = 1 PMCCM0 = 1 PMCCM1 = 1 PMCCM2 = 1 PMCCM3 = 1 PMCCS0 = 1 PMCCS1 = 1 PMCCS2 = 1 PMCCS3 = 1 PMCCT0 = 1 PMCCT1 = 1 PMCCT4 = 1 PMCCT6 = 1 PFC910 = 0 PFC910 = 1 PFC911 = 0 PFC911 = 1 PFC912 = 0 PFC912 = 1 PFC913 = 0 PFC913 = 1 PFC914 = 0 PFC914 = 1 PFC915 = 0 PFC915 = 1 - - - - - - - - - - - - Note - Note, PF911 (PF9) = 0 PF911 (PF9) = Don't care Note, PF912 (PF9) = 0 PF912 (PF9) = Don't care Note INTR913 (INTR9), INTF913 (INTF9) Note INTR914 (INTR9), INTF914 (INTF9) Note INTR915 (INTR9), INTF915 (INTF9) - - - - - - - - - - - - CHAPTER 4 PORT FUNCTIONS
Note When setting the A0 to A15 pins, perform 16-bit setting of PFC9 register = 0000H and PMC9 register = FFFFH at one time.
Table 4-28. Settings When Port Pins Are Used for Alternate Functions (7/7)
Pin Name Alternate Function Function Name PDH0 PDH1 PDH2 PDH3 PDH4 PDH5 PDH6 PDH7 PDL0 PDL1 PDL2 PDL3 PDL4 PDL5 PDL6 PDL7 PDL8 PDL9 PDL10 PDL11 PDL12 PDL13 PDL14 PDL15
User's Manual U15862EJ3V0UD
Pnx Bit of Pn Register
PMnx Bit of PMn Register
PMCnx Bit of
PFCnx Bit of
Other Bits (Registers)
I/O Output Output Output Output Output Output Output Output I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PDH0 = Setting not required PDH1 = Setting not required PDH2 = Setting not required PDH3 = Setting not required PDH4 = Setting not required PDH5 = Setting not required PDH6 = Setting not required PDH7 = Setting not required PDL0 = Setting not required PDL1 = Setting not required PDL2 = Setting not required PDL3 = Setting not required PDL4 = Setting not required PDL5 = Setting not required PDL6 = Setting not required PDL7 = Setting not required PDL8 = Setting not required PDL9 = Setting not required PDL10 = Setting not required PDL11 = Setting not required PDL12 = Setting not required PDL13 = Setting not required PDL14 = Setting not required PDL15 = Setting not required PMDH0 = Setting not required PMDH1 = Setting not required PMDH2 = Setting not required PMDH3 = Setting not required PMDH4 = Setting not required PMDH5 = Setting not required PMDH6 = Setting not required PMDH7 = Setting not required PMDL0 = Setting not required PMDL1 = Setting not required PMDL2 = Setting not required PMDL3 = Setting not required PMDL4 = Setting not required PMDL5 = Setting not required PMDL6 = Setting not required PMDL7 = Setting not required PMDL8 = Setting not required PMDL9 = Setting not required
PMCn Register PFCn Register PMCDH0 = 1 PMCDH1 = 1 PMCDH2 = 1 PMCDH3 = 1 PMCDH4 = 1 PMCDH5 = 1 PMCDH6 = 1 PMCDH7 = 1 PMCDL0 = 1 PMCDL1 = 1 PMCDL2 = 1 PMCDL3 = 1 PMCDL4 = 1 PMCDL5 = 1 PMCDL6 = 1 PMCDL7 = 1 PMCDL8 = 1 PMCDL9 = 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CHAPTER 4 PORT FUNCTIONS
A16 A17 A18 A19 A20 A21 A22 A23 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15
PMDL10 = Setting not required PMCDL10 = 1 PMDL11 = Setting not required PMCDL11 = 1 PMDL12 = Setting not required PMCDL12 = 1 PMDL13 = Setting not required PMCDL13 = 1 PMDL14 = Setting not required PMCDL14 = 1 PMDL15 = Setting not required PMCDL15 = 1
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4.4 Port Function Operation
Port operation differs according to the input/output mode setting, as follows. 4.4.1 Write operation to I/O port (1) In output mode A value is written to the output latch using the transfer instruction, and the contents of the output latch are output from the pin. Data that has been written once to the output latch is held until the next data is written to the output latch. (2) In input mode A value is written to the output latch using the transfer instruction. However, since the output buffer is OFF, the pin status does not change. Data that has been written once to the output latch is held until the next data is written to the output latch. Caution In the case of 1-bit memory manipulation instructions, the manipulation target is just one bit, but the port is accessed in 8-bit units. Therefore, in the case of ports for which a mixture of input/output is used, the output latch contents of pins specified as input other than the target bit also become undefined. 4.4.2 Read operation from I/O port (1) In output mode The output latch contents are read using the transfer instruction. The output latch contents remain unchanged. (2) In input mode The pin status is read using the transfer instruction. The output latch contents remain unchanged. 4.4.3 Arithmetic operation with I/O ports (1) In output mode An arithmetic operation on the output latch contents is performed, the result is written to the output latch, and the output latch contents are output from the pin. Data that has been written once to the output latch is held until the next data is written to the output latch. (2) In input mode The output latch contents become undefined. However, since the output buffer is OFF, the pin status does not change. Caution In the case of 1-bit memory manipulation instructions, the manipulation target is just one bit, but the port is accessed in 8-bit units. Therefore, in the case of ports for which input/output is used in mix, the output latch contents of pins specified for input other than the target bit also become undefined.
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The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 are provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected.
5.1 Features
Output is selectable from a multiplex bus with a minimum of 3 bus cycles and a separate bus with a minimum of 2 bus cycles (separate bus output is only available in the V850ES/KG1 and V850ES/KJ1) Chip select function for up to 4 spaces (V850ES/KF1, V850ES/KG1: 2 spaces, V850ES/KJ1: 4 spaces) 8-bit/16-bit data bus selectable (for each area selected by chip select function) Wait function * Programmable wait function of up to 7 states (selectable for each area selected by chip select function) * External wait function using WAIT pin Idle state function Bus hold function The bus can be controlled using a different voltage from the operating voltage by setting BVDD VDD = EVDD (however, only in multiplex bus mode).
5.2 Bus Control Pins
The pins used to connect an external device are listed in the table below. (1) Multiplex bus mode Table 5-1. V850ES/KF1 Bus Control Pins
Bus Control Pin AD0 to AD15 WAIT CLKOUT CS0, CS1 WR0, WR1 RD ASTB HLDRQ HLDAK Alternate-Function Pin PDL0 to PDL15 PCM0 PCM1 PCS0, PCS1 PCT0, PCT1 PCT4 PCT6 PCM3 PCM2 I/O I/O Input Output Output Output Output Output Input Output Address/data bus External wait control Internal system clock output Chip select Write strobe signal Read strobe signal Address strobe signal Bus hold control Function
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Table 5-2. V850ES/KG1 Bus Control Pins
Bus Control Pin AD0 to AD15 A16 to A21 WAIT CLKOUT CS0, CS1 WR0, WR1 RD ASTB HLDRQ HLDAK Alternate-Function Pin PDL0 to PDL15 PDH0 to PDH5 PCM0 PCM1 PCS0 to PCS1 PCT0, PCT1 PCT4 PCT6 PCM3 PCM2 I/O I/O Output Input Output Output Output Output Output Input Output Address/data bus Address bus External wait control Internal system clock output Chip select Write strobe signal Read strobe signal Address strobe signal Bus hold control Function
Table 5-3. V850ES/KJ1 Bus Control Pins
Bus Control Pin AD0 to AD15 A16 to A23 WAIT CLKOUT CS0 to CS3 WR0, WR1 RD ASTB HLDRQ HLDAK Alternate-Function Pin PDL0 to PDL15 PDH0 to PDH7 PCM0 PCM1 PCS0 to PCS3 PCT0, PCT1 PCT4 PCT6 PCM3 PCM2 I/O I/O Output Input Output Output Output Output Output Input Output Address/data bus Address bus External wait control Internal system clock output Chip select Write strobe signal Read strobe signal Address strobe signal Bus hold control Function
(2) Separate bus mode Note that the separate bus mode is not available in the V850ES/KF1. Table 5-4. V850ES/KG1 Bus Control Pins
Bus Control Pin AD0 to AD15 A0 to A15 A16 to A21 WAIT CLKOUT CS0, CS1 WR0, WR1 RD HLDRQ HLDAK Alternate-Function Pin PDL0 to PDL15 P90 to P915 PDH0 to PDH5 PCM0 PCM1 PCS0, PCS1 PCT0, PCT1 PCT4 PCM3 PCM2 I/O I/O Output Output Input Output Output Output Output Input Output Data bus Address bus Address bus External wait control Internal system clock output Chip select Write strobe signal Read strobe signal Bus hold control Function
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Table 5-5. V850ES/KJ1 Bus Control Pins
Bus Control Pin AD0 to AD15 A0 to A15 A16 to A23 WAIT CLKOUT CS0 to CS3 WR0, WR1 RD HLDRQ HLDAK Alternate-Function Pin PDL0 to PDL15 P90 to P915 PDH0 to PDH7 PCM0 PCM1 PCS0 to PCS3 PCT0, PCT1 PCT4 PCM3 PCM2 I/O I/O Output Output Input Output Output Output Output Input Output Data bus Address bus Address bus External wait control Internal system clock output Chip select Write strobe signal Read strobe signal Bus hold control Function
5.2.1 Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed Table 5-6. Pin Status When Internal ROM, Internal RAM, or On-Chip Peripheral I/O Is Accessed
Access Destination Internal ROM Internal RAM On-chip peripheral I/O Address Bus Undefined Undefined Note Data Bus Hi-Z Hi-Z Hi-Z Control Signal Inactive Inactive Inactive
Note When an on-chip peripheral I/O is accessed, the address bus outputs the address of the on-chip peripheral I/O that is accessed. 5.2.2 Pin status in each operation mode For the pin status of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 in each operation mode, refer to 2.2 Pin Status.
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5.3 Memory Block Function
(1) V850ES/KF1 The 64 MB memory space is divided into memory blocks of (lower) 2 MB and 64 KB. The programmable wait function and bus cycle operation mode for each of these blocks can be independently controlled in one-block units. Figure 5-1. Data Memory Map (V850ES/KF1)
3FFFFFFH (80 KB) 3FEC000H 3FEBFFFH
On-chip peripheral I/O area (4 KB)
3FFFFFFH 3FFF000H 3FFEFFFH
Internal RAM areaNote 1 (6 KB)
3FFD800H 3FFD7FFH Access-prohibited area 3FEC000H
Access-prohibited area
01FFFFFH
Access-prohibited area 0110000H 010FFFFH 0100000H 00FFFFFH
External memory area (64 KB) 0210000H 020FFFFH 0200000H 01FFFFFH 0000000H
External memory area (64 KB)
CS1 Internal ROM areaNote 2 (1 MB) CS0 0000000H
(2 MB)
Notes 1. This area is the 4 KB space of 3FFE000H to 3FFEFFFH in the PD703208, 703208Y, 703209, and 703209Y. 2. This area is an external memory area in the case of a data write access. Caution A write access to addresses 0000000H to 000FFFFH is the same operations as a write access to addresses 0100000H to 010FFFFH.
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(2) V850ES/KG1 The 64 MB memory space is divided into memory blocks of (lower) 2 MB and 2 MB. The programmable wait function and bus cycle operation mode for each of these blocks can be independently controlled in one-block units. Figure 5-2. Data Memory Map (V850ES/KG1)
3FFFFFFH (80 KB) 3FEC000H 3FEBFFFH
On-chip peripheral I/O area (4 KB)
3FFFFFFH 3FFF000H 3FFEFFFH
Internal RAM areaNote 1 (6 KB)
3FFD800H 3FFD7FFH Access-prohibited area 3FEC000H
Access-prohibited area
0400000H 03FFFFFH 0200000H 01FFFFFH 0000000H External memory area (2 MB) CS1 External memory area (1 MB) Internal ROM areaNote 2 (1 MB)
01FFFFFH
0100000H 00FFFFFH 0000000H
(2 MB)
CS0
Notes 1. This area is the 4 KB space of 3FFE000H to 3FFEFFFH in the PD703212, 703212Y, 703213, and 703213Y. 2. This area is an external memory area in the case of a data write access.
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(3) V850ES/KJ1 The 64 MB memory space is divided into memory blocks of (lower) 2 MB, 2 MB, 4 MB, and 8 MB. The programmable wait function and bus cycle operation mode for each of these blocks can be independently controlled in one-block units. Figure 5-3. Data Memory Map (V850ES/KJ1)
3FFFFFFH (80 KB) 3FEC000H 3FEBFFFH
On-chip peripheral I/O area (4 KB)
3FFFFFFH 3FFF000H 3FFEFFFH
Internal RAM area (6 KB)
Access-prohibited area
3FFD800H 3FFD7FFH Access-prohibited area
1000000H 0FFFFFFH
3FEC000H
External memory area (8 MB)
CS3
0800000H 07FFFFFH
External memory area (4 MB) 0400000H 03FFFFFH 0200000H 01FFFFFH 0000000H External memory area (2 MB)
CS2
01FFFFFH CS1 External memory area (1 MB) Internal ROM areaNote (1 MB) 0000000H
0100000H 00FFFFFH
(2 MB)
CS0
Note This area is an external memory area in the case of a data write access.
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5.3.1 Chip select control function Of the 64 MB (linear) address space, the lower 16 MB (0000000H to 0FFFFFFH) include four chip select control functions, CS0 to CS3. The areas that can be selected by CS0 to CS3 are fixed. By using these chip select control functions, the memory block can be divided to enable effective use of the memory space. The allocation of the memory blocks is shown in the table below.
V850ES/KF1 CS0 CS1 CS2 CS3 V850ES/KG1 V850ES/KJ1 0000000H to 01FFFFFH (2 MB) 0200000H to 03FFFFFH (2 MB) 0400000H to 07FFFFFH (4 MB) 0800000H to 0FFFFFFH (8 MB)
0000000H to 010FFFFH (1088 KB) 0000000H to 01FFFFFH (2 MB) 0200000H to 020FFFFH (64 KB) - - 0200000H to 03FFFFFH (2 MB) - -
5.4 External Bus Interface Mode Control Function
The V850ES/KG1 and V850ES/KJ1 include the following two external bus interface modes. * Multiplex bus mode * Separate bus mode These two modes can be selected by using the external bus interface mode control register (EXIMC). Remark Only the multiplex bus mode is available in the V850ES/KF1. (1) External bus interface mode control register (EXIMC) This register can be read or written in 8-bit or 1-bit units. RESET input clears this register to 00H. Caution The EXIMC register is only available in the V850ES/KG1 and V850ES/KJ1.
After reset: 00H
R/W
Address: FFFFFFBEH
EXIMC
0
0
0
0
0
0
0
SMSEL
SMSEL 0 1 Multiplex bus mode Separate bus mode
Mode selection
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5.5 Bus Access
5.5.1 Number of clocks for access The following table shows the number of basic clocks required for accessing each resource.
Area (Bus Width) Bus Cycle Type Instruction fetch (normal access) Instruction fetch (branch) Operand data access 1 2 3 1 or 2 1 or 2 1 3 + nNote 3+ nNote 3 +nNote Internal ROM (32 Bits) Internal RAM (32 Bits) External Memory (16 Bits)
Note 2 + n clocks (n: Number of wait states) when the separate bus mode is selected (V850ES/KG1 and V850ES/KJ1). Remark Unit: Clocks/access 5.5.2 Bus size setting function The bus size of each external memory area selected by CSn can be set (to 8 bits or 16 bits) by using the BSC register. The external memory area of the V850ES/KJ1 (0100000H to 0FFFFFFH) is selected by CS0 to CS3. The external memory area of the V850ES/KG1 (0100000H to 03FFFFFH) is selected by CS0 and CS1. The external memory area of the V850ES/KF1 (0100000H to 010FFFFH and 0200000H to 020FFFFH) is selected by CS0 and CS1. (1) Bus size configuration register (BSC) This register can be read or written in 16-bit units. Caution Write to the BSC register after reset, and then do not change the set values. Also, do not access an external memory area other than the one for this initialization routine until the initial settings of the BSC register are complete. However, external memory areas whose initial settings are complete may be accessed.
After reset: 5555H
15
R/W
14
Address: FFFFF066H
13 12 11 10 9 8
BSC
0
7
1
6
0
5
Note
1
4
0
3
Note
1
2
0
1
1
0
0 CSn signal BSn0 0 1
BS30
0
BS20
0
BS10 CS1
0
BS00 CS0
CS3
CS2
Data bus width of CSn space (n = 0 to 3) 8 bits 16 bits
Note The BS30 and BS20 bits are only valid in the V850ES/KJ1. Changing these bits has no effect on the operation in the V850ES/KF1 and V850ES/KG1. Caution Be sure to set bits 14, 12, 10, and 8 to 1, and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to 0.
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5.5.3 Access by bus size The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 access the on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The bus size is as follows. * The bus size of the on-chip peripheral I/O is fixed to 16 bits. * The bus size of the external memory is selectable from 8 bits or 16 bits (by using the BSC register). The operation when each of the above is accessed is described below. All data is accessed starting from the lower side. The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 support only the little endian format. Figure 5-4. Little Endian Address in Word
31 000BH 0007H 0003H
24 23 000AH 0006H 0002H
16 15 0009H 0005H 0001H
87 0008H 0004H 0000H
0
(1) Byte access (8 bits) (a) 16-bit data bus width <1> Access to even address (2n)
Address 15 15 2n + 1 7 8 7 2n 0 Byte data 0 External data bus 0 Byte data 0 External data bus 7 8 7
<2> Access to odd address (2n + 1)
Address
(b) 8-bit data bus width <1> Access to even address (2n)
Address 7 7 2n 0 Byte data 0 External data bus
0 Byte data 0 External data bus 7 7 2n + 1
<2> Access to odd address (2n + 1)
Address
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(2) Halfword access (16 bits) (a) With 16-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) First access
Address 15 15 2n + 1 8 7 8 7 2n 0 Halfword data 0 External data bus
Second access
Address Address 15 2n + 1 15
15
15
8 7
8 7 2n
8 7
8 7 2n + 2
0 Halfword data
0 External data bus
0 Halfword data
0 External data bus
(b) 8-bit data bus width <1> Access to even address (2n) First access
15 8 7 0 Halfword data Address 7 2n 0 External data bus 0 Halfword data 0 External data bus 15 8 7 Address 7 2n + 1
0 Halfword data 0 External data bus
<2> Access to odd address (2n + 1) First access
15 8 7 Address 7 2n + 1 0 Halfword data 0 External data bus 15 8 7 Address 7 2n + 2
Second access
Second access
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(3) Word access (32 bits) (a) 16-bit data bus width (1/2) <1> Access to address (4n) First access
31 31
Second access
24 23 Address 15 4n + 1 8 7 8 7 4n 0 Word data 0 External data bus
24 23 Address 15 4n + 3 8 7 8 7 4n + 2 0 Word data 0 External data bus
16 15
16 15
<2> Access to address (4n + 1) First access
31 31
Second access
31
Third access
24 23 Address 15 4n + 1 8 7 8 7
24 23 Address 15 4n + 3 8 7 8 7 4n + 2
24 23 Address 15
16 15
16 15
16 15
8 7
8 7 4n + 4
0 Word data
0 External data bus
0 Word data
0 External data bus
0 Word data
0 External data bus
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(a) 16-bit data bus width (2/2) <3> Access to address (4n + 2) First access
31 31
Second access
24 23 Address 15 4n + 3 8 7 8 7 4n + 2 0 Word data 0 External data bus
24 23 Address 15 4n + 5 8 7 8 7 4n + 4 0 Word data 0 External data bus
16 15
16 15
<4> Access to address (4n + 3) First access
31 31
Second access
31
Third access
24 23 Address 15 4n + 3 8 7 8 7
24 23 Address 15 4n + 5 8 7 8 7 4n + 4
24 23 Address 15
16 15
16 15
16 15
8 7
8 7 4n + 6
0 Word data
0 External data bus
0 Word data
0 External data bus
0 Word data
0 External data bus
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(b) 8-bit data bus width (1/2) <1> Access to address (4n) First access
31 24 23 16 15 8 7 0 Word data Address 7 4n 0 External data bus 0 Word data 0 External data bus 31 24 23 16 15 8 7 Address 7 4n + 1 0 Word data 0 External data bus
Second access
31 24 23 16 15 8 7
Third access
31 24 23 16 15 Address 7 4n + 2 8 7
Fourth access
Address 7 4n + 3 0 External data bus
0 Word data
<2> Access to address (4n + 1) First access
31 24 23 16 15 8 7 0 Word data Address 4n + 1 0 External data bus 0 Word data 0 External data bus 31 24 23 16 15 8 7 Address 4n + 2 0 Word data 0 External data bus
Second access
31 24 23 16 15 8 7
Third access
31 24 23 16 15 Address 4n + 3 0 8 7
Fourth access
7
7
7
7 0
Address 4n + 4
Word data
External data bus
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(b) 8-bit data bus width (2/2) <3> Access to address (4n + 2) First access
31 24 23 16 15 8 7 0 Word data Address 7 4n + 2 0 External data bus 0 Word data 0 External data bus 31 24 23 16 15 8 7 Address 7 4n + 3 0 Word data 0 External data bus
Second access
31 24 23 16 15 8 7
Third access
31 24 23 16 15 Address 7 4n + 4 8 7
Fourth access
Address 7 4n + 5 0 External data bus
0 Word data
<4> Access to address (4n + 3) First access
31 24 23 16 15 8 7 0 Word data Address 7 4n + 3 0 External data bus 0 Word data 0 External data bus 31 24 23 16 15 8 7 Address 7 4n + 4 0 Word data 0 External data bus
Second access
31 24 23 16 15 8 7
Third access
31 24 23 16 15 Address 7 4n + 5 0 8 7
Fourth access
Address 7 4n + 6 0 External data bus
Word data
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5.6 Wait Function
5.6.1 Programmable wait function (1) Data wait control register 0 (DWC0) To realize interfacing with a low-speed memory or I/O, up to seven data wait states can be inserted in the bus cycle that is executed for each CS space. The number of wait states can be programmed by using data wait control register 0 (DWC0). Immediately after system reset, 7 data wait states are inserted for all the blocks. The DWC0 register can be read or written in 16-bit units. Cautions 1. The internal ROM and internal RAM areas are not subject to programmable wait, and are always accessed without a wait state. The on-chip peripheral I/O area is also not subject to programmable wait, and only wait control from each peripheral function is performed. 2. Write to the DWC0 register after reset, and then do not change the set values. Also, do not access an external memory area other than the one for this initialization routine until the initial settings of the DWC0 register are complete. However, external memory areas whose initial settings are complete may be accessed.
After reset: 7777H
15
R/W
14
Address: FFFFF484H
13 12
Note
11
Note
10
9
Note
8
Note
DWC0
0
DW32
Note
DW31
DW30
0
DW22
DW21
DW20Note
CSn signal
7 6
CS3
5 4 3 2
CS2
1 0
0 CSn signal DWn2 0 0 0 0 1 1 1 1
DW12
DW11 CS1
DW10
0
DW02
DW01 CS0
DW00
DWn1 0 0 1 1 0 0 1 1
DWn0 0 1 0 1 0 1 0 1
Number of wait states inserted in CSn space (n = 0 to 3) None 1 2 3 4 5 6 7
Note The DW32 to DW30 and DW22 to DW20 bits are only valid in the V850ES/KJ1. Changing these bits has no effect on the operation in the V850ES/KF1 and V850ES/KG1. Caution Be sure to clear bits 15, 11, 7, and 3 to 0.
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5.6.2 External wait function To synchronize an extremely slow external device, I/O, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (WAIT). Access to each area of the internal ROM, internal RAM, and on-chip peripheral I/O is not subject to control by the external wait function, in the same manner as the programmable wait function. The WAIT signal can be input asynchronously to CLKOUT, and is sampled at the falling edge of the clock in the T2 and TW states of the bus cycle in the multiplex bus mode. In the separate bus mode, it is sampled at the rising edge of the clock immediately after the T1 and TW states of the bus cycle. If the setup/hold time of the sampling timing is not satisfied, a wait state is inserted in the next state, or not inserted at all.
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5.6.3 Relationship between programmable wait and external wait Wait cycles are inserted as the result of an OR operation between the wait cycles specified by the set value of the programmable wait and the wait cycles controlled by the WAIT pin. The number of wait cycles is determined by the side with the greatest number of cycles.
Programmable wait Wait control Wait via WAIT pin
For example, if the timing of the programmable wait and the WAIT pin signal is as illustrated below, three wait states will be inserted in the bus cycle. Figure 5-5. Example of Inserting Wait States
(a) In separate bus mode
T1 TW TW TW T2
CLKOUT WAIT pin
Wait via WAIT pin
Programmable wait
Wait control
Remark The circles indicate the sampling timing. (b) In multiplex bus mode
T1 CLKOUT WAIT pin Wait by WAIT pin Programmable wait Wait control
T2
TW
TW
TW
T3
Remark
: Valid sampling timing
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5.6.4 Programmable address wait function Address-setup or address-hold waits to be inserted in each bus cycle can be set by using the address wait control register (AWC). Address wait insertion is set for each chip select area (CS0 to CS3). If an address setup wait is inserted, it seems that the high-clock period of T1 state is extended by 1 clock. If an address hold wait is inserted, it seems that the low-clock period of T1 state is extended by 1 clock. (1) Address wait control register (AWC) This register can be read or written in 16-bit units.
After reset: FFFFH
15
R/W
14
Address: FFFFF488H
13 12 11 10 9 8
AWC
1
7
1
6
Note
1
5
Note
1
4
Note
1
3
Note
1
2
1
1
1
0
AHW3 CSn signal
ASW3
AHW2
ASW2
AHW1
ASW1 CS1
AHW0
ASW0 CS0
CS3
CS2
AHWn 0 1
Specifies insertion of address hold wait (n = 0 to 3) Not inserted Inserted
ASWn 0 1
Specifies insertion of address setup wait (n = 0 to 3) Not inserted Inserted
Note The AHW3, AHW2, ASW3, and ASW2 bits are only valid in the V850ES/KJ1. Changing these bits has no effect on the operation in the V850ES/KF1 and V850ES/KG1. Caution Be sure to set bits 15 to 8 to 1.
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5.7 Idle State Insertion Function
To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus cycle that is executed for each space selected by the chip select function in the multiplex address/data bus mode. In the separate bus mode, one idle state (TI) can be inserted after the T2 state. By inserting idle states, the data output float delay time of the memory can be secured during read access (an idle state cannot be inserted during write access). Whether the idle state is to be inserted can be programmed by using the bus cycle control register (BCC). An idle state is inserted for all the areas immediately after system reset. (1) Bus cycle control register (BCC) This register can be read or written in 16-bit units. Cautions 1. The internal ROM, internal RAM, and on-chip peripheral I/O areas are not subject to idle state insertion. 2. Write to the BCC register after reset, and then do not change the set values. Also, do not access an external memory area other than the one for this initialization routine until the initial settings of the BCC register are complete. However, external memory areas whose initial settings are complete may be accessed.
After reset: AAAAH
15 14
R/W
Address: FFFFF48AH
13 12 11 10 9 8
BCC
1
7
0
6
Note
1
5
0
4
Note
1
3
0
2
1
1
0
0
BC31
0
BC21
0
BC11 CS1
0
BC01 CS0
0
CSn signal CS3 BCn1 0 1
CS2
Specifies insertion of idle state (n = 0 to 3) Not inserted Inserted
Note The BC31 and BC21 bits are only valid in the V850ES/KJ1. Changing these bits has no effect on the operation in the V850ES/KF1 and V850ES/KG1. Caution Be sure to set bits 15, 13, 11, and 9 to 1, and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to 0.
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5.8 Bus Hold Function
5.8.1 Functional outline The HLDAK and HLDRQ functions are valid if the PCM2 and PCM3 pins are set in the control mode. When the HLDRQ pin is asserted (low level), indicating that another bus master has requested bus mastership, the external address/data bus goes into a high-impedance state and is released (bus hold status). If the request for the bus mastership is cleared and the HLDRQ pin is deasserted (high level), driving these pins is started again. During the bus hold period, execution of the program in the internal ROM and internal RAM is continued until a peripheral I/O register or the external memory is accessed. The bus hold status is indicated by assertion (low level) of the HLDAK pin. The bus hold function enables the configuration of multi-processor type systems in which two or more bus masters exist. Note that the bus hold request is not acknowledged during a multiple-access cycle initiated by the bus sizing function or a bit manipulation instruction.
Status Data Bus Width 16 bits Access Type Timing in Which Bus Hold Request Not Acknowledged Between first and second access Between first and second access Between second and third access Halfword access to odd address 8 bits Word access Between first and second access Between first and second access Between second and third access Between third and fourth access Halfword access Read-modify-write access of bit manipulation instruction - - Between first and second access Between read access and write access
CPU bus lock
Word access to even address Word access to odd address
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5.8.2 Bus hold procedure The bus hold status transition procedure is shown below.
<1> HLDRQ = 0 acknowledged <2> All bus cycle start requests inhibited <3> End of current bus cycle <4> Shift to bus idle status. <5> HLDAK = 0
Normal status
Bus hold status
<6> HLDRQ = 1 acknowledged <7> HLDAK = 1 <8> Bus cycle start request inhibition released <9> Bus cycle starts
Normal status
HLDRQ (input)
HLDAK (output)
<1> <2>
<3><4> <5>
<6> <7><8><9>
5.8.3 Operation in power save mode Because the internal system clock is stopped in the STOP and IDLE modes, the bus hold status is not entered even if the HLDRQ pin is asserted. In the HALT mode, the HLDAK pin is asserted as soon as the HLDRQ pin has been asserted, and the bus hold status is entered. When the HLDRQ pin is later deasserted, the HLDAK pin is also deasserted, and the bus hold status is cleared.
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5.9 Bus Priority
Bus hold, instruction fetch (branch), instruction fetch (successive), and operand data accesses are executed in the external bus cycle. Bus hold has the highest priority, followed by operand data access, instruction fetch (branch), and instruction fetch (successive). An instruction fetch may be inserted between the read access and write access in a read-modify-write access. If an instruction is executed for two or more accesses, an instruction fetch and bus hold are not inserted between accesses due to bus size limitations. Table 5-7. Bus Priority
Priority High Bus hold Operand data access Instruction fetch (branch) Low Instruction fetch (successive) External Bus Cycle Bus Master External device CPU CPU CPU
5.10 Boundary Operation Conditions
5.10.1 Program space (1) If a branch instruction exists at the upper limit of the internal RAM area, a prefetch operation straddling over the on-chip peripheral I/O area (invalid fetch) does not occur. (2) Instruction execution to the external memory area cannot be continued without a branch from the internal ROM area to the external memory area. 5.10.2 Data space The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 have an address misalign function. With this function, data can be placed at all addresses, regardless of the format of the data (word data or halfword data). However, if the word data or halfword data is not aligned at the boundary, a bus cycle is generated at least twice, causing the bus efficiency to drop. (1) Halfword-length data access A byte-length bus cycle is generated twice if the least significant bit of the address is 1. (2) Word-length data access (a) A byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle are generated in that order if the least significant bit of the address is 1. (b) A halfword-length bus cycle is generated twice if the lower 2 bits of the address are 10.
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5.11 Bus Timing
Figure 5-6. Multiplex Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access)
T1
T2
T3
T1
T2
TW
TW
T3
TI
T1
CLKOUT A23 to A16 ASTB CS3 to CS0 WAIT AD15 to AD0 RD Programmable External wait wait 8-bit access AD15 to AD8 AD7 to AD0 Odd address Active - Even address - Active Idle state A1 D1 A2 D2 A3 A1 A2 A3
Remark The broken lines indicate high impedance.
Figure 5-7. Multiplex Bus Read Timing (Bus Size: 8 Bits)
T1 CLKOUT A23 to A16, AD15 to AD8 ASTB CS3 to CS0 WAIT AD7 to AD0 RD A1
T2
T3
T1
T2
TW
TW
T3
TI
T1
A1
A2
A3
D1
A2
D2
A3
Programmable External wait wait
Idle state
Remark The broken lines indicate high impedance.
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Figure 5-8. Multiplex Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access)
T1 CLKOUT A23 to A16 ASTB CS3 to CS0 WAIT AD15 to AD0 WR1, WR0 A1 11
T2
T3
T1
T2
TW
TW
T3
T1
A1
A2
A3
D1 00 11
A2 11
D2 00
A3 11
Programmable External wait wait 8-bit access AD15 to AD8 AD7 to AD0 WR1, WR0 Odd address Active Undefined 01 10 Even address Undefined Active
Figure 5-9. Multiplex Bus Write Timing (Bus Size: 8 Bits)
T1 CLKOUT A23 to A16, AD15 to AD8 ASTB CS3 to CS0 WAIT AD7 to AD0 WR1, WR0 A1 11
T2
T3
T1
T2
TW
TW
T3
T1
A1
A2
A3
D1 10 11
A2 11
D2 10
A3 11
Programmable External wait wait
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Figure 5-10. Multiplex Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access)
T1 CLKOUT HLDRQ HLDAK A23 to A16 AD15 to AD0 ASTB RD CS3 to CS0 A1
T2
T3
TINote
TH
TH
TH
TH
TINote
T1
T2
T3
A1 D1
Undefined Undefined
Undefined Undefined A2
A2 D2
1111
1111
Note This idle state (TI) does not depend on the BCC register settings. Remarks 1. Refer to Tables 2-2 to 2-4 for the pin statuses in the bus hold mode. 2. The broken lines indicate high impedance.
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Figure 5-11. Separate Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access)
T1 CLKOUT CS3 to CS0 WAIT A23 to A0 RD AD15 to AD0 A1
T2
T1
TW
TW
T2
TI
T1
T2
A2
A3
D1
D2
D3
Programmable External wait wait 8-bit access AD15 to AD8 AD7 to AD0 Odd address Active - Even address - Active
Idle state
Remark The broken lines indicate high impedance.
Figure 5-12. Separate Bus Read Timing (Bus Size: 8 Bits)
T1 CLKOUT CS3 to CS0 WAIT A23 to A0 RD AD7 to AD0 A1
T2
T1
TW
TW
T2
TI
T1
T2
A2
A3
D1
D2
D3
Programmable External wait wait
Idle state
Remark The broken lines indicate high impedance.
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Figure 5-13. Separate Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access)
T1 CLKOUT CS3 to CS0 WAIT A23 to A0 WR1, WR0 AD15 to AD0 11 A1
T2
T1
TW
TW
T2
T1
T2
A2 00 D1 11 11 00 D2 11
A3 00 D3 11
Programmable External wait wait 8-bit access AD15 to AD8 AD7 to AD0 WR1, WR0 Odd address Active Undefined 01 10 Even address Undefined Active
Remark The broken lines indicate high impedance.
Figure 5-14. Separate Bus Write Timing (Bus Size: 8 Bits)
T1 CLKOUT CS3 to CS0 WAIT A23 to A0 WR1, WR0 AD7 to AD0 11 A1
T2
T1
TW
TW
T2
T1
T2
A2 10 D1 11 11 10 D2 11
A3 10 D3 11
Programmable External wait wait
Remark The broken lines indicate high impedance.
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Figure 5-15. Separate Bus Hold Timing (Bus Size: 8 Bits, Write)
T1 CLKOUT HLDRQ HLDAK A23 to A0 AD7 to AD0 WR1, WR0 CS3 to CS0 11 A1
T2
T1
T2
TIic
TH
TH
TH
TH
TIic
T1
T2
A2 D1 D2 11 10
Undefined
Undefined
A3 D3
10
11 1111 1111
11
10
11
Note This idle state (TI) does not depend on the BCC register settings. Remark The broken lines indicate high impedance.
Figure 5-16. Address Wait Timing (Separate Bus Read, Bus Size: 16 Bits, 16-Bit Access)
T1 CLKOUT ASTB CS3 to CS0 WAIT A23 to A0 RD AD15 to AD0 A1
T2 CLKOUT ASTB CS3 to CS0 WAIT A23 to A0 RD D1 AD15 to AD0
TASW
T1
TAHW
T2
A1
D1
Remarks 1. TASW (address setup wait): Image of high-level width of T1 state expanded. 2. TAHW (address hold wait): Image of low-level width of T1 state expanded. 3. The broken lines indicate high impedance.
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5.12 Cautions
With the external bus function, signals may not be output at the correct timing under the following conditions. Multiplex bus mode <1> CLKOUT asynchronous (2.7 V VDD = EVDD = AVREF0 5.5 V, 2.7 V BVDD 5.5 V) When 1/fCPU < 84 ns Separate bus mode <1> Read cycle, CLKOUT asynchronous (4.0 V VDD = EVDD = AVREF0 5.5 V, 4.0 V BVDD 5.5 V) When 1/fCPU < 100 ns <2> Write cycle, CLKOUT asynchronous (4.0 V VDD = EVDD = AVREF0 5.5 V, 4.0 V BVDD 5.5 V) When 1/fCPU < 60 ns <3> Read cycle, CLKOUT asynchronous (2.7 V VDD = EVDD = AVREF0 5.5 V, 2.7 V BVDD 5.5 V) When 1/fCPU < 200 ns <4> Write cycle, CLKOUT asynchronous (2.7 V VDD = EVDD = AVREF0 5.5 V, 2.7 V BVDD 5.5 V) When 1/fCPU < 100 ns When used under the above conditions, be sure to insert an address setup/hold wait using the address wait control register (AWC) (n = 0 to 3). When used in multiplex bus mode and under condition <1> * 70 ns < 1/fCPU < 84 ns Set an address setup wait (ASWn bit = 1). * 62.5 ns < 1/fCPU < 70 ns Set an address setup wait (ASWn bit = 1) and address hold wait (AHWn bit = 1). When used in separate bus mode and under conditions <1> to <4> Set an address setup wait (ASWn bit =1).
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CHAPTER 6 CLOCK GENERATION FUNCTION
6.1 Overview
The following clock generation functions are available. Main clock oscillator * fX = 2 to 2.5 MHz (REGC = VDD = 2.7 to 5.5 V, in PLL mode) * fX = 2 to 5 MHz (REGC = VDD = 4.5 to 5.5 V, in PLL mode) * fX = 2 to 4 MHz (REGC = capacitor, VDD = 4.0 to 5.5 V, in PLL mode) * fX = 2 to 10 MHz (REGC = VDD = 2.7 to 5.5 V, in clock-through mode) Subclock oscillator * 32.768 kHz Multiply (x4) function by PLL (Phase Locked Loop) * Clock-through mode/PLL mode selectable * Usable voltage: VDD = 2.7 to 5.5 V Internal system clock generation * 7 steps (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT) Peripheral clock generation Clock output function
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6.2 Configuration
Figure 6-1. Clock Generator
FRC bit XT1 XT2 Subclock oscillator fXT fXT fBRG = fX/2 to fX/212 Prescaler 3 IDLE control CK2 to CK0 bits X1 X2
Selector
Watch timer clock, watchdog timer clock Watch timer clock
IDLE mode
MFRC bit Main clock oscillator Main clock oscillator stop control STOP mode fX
PLLON bit
IDLE mode
CLS bit, CK3 bit
PLL
IDLE fXX control
Prescaler 2 fXX/32 fXX/16 fXX/8 fXX/4 fXX/2 fXX HALT mode
Selector Selector
HALT fCPU control fCLK
CPU clock Internal system clock
SELPLL bit
IDLE mode
Prescaler 1
fXX to fXX/1024 Peripheral clock, watchdog timer 2 clock fXW Watchdog timer 1 clock
IDLE control CLKOUT Port CM
(1) Main clock oscillator The main resonator oscillates the following frequencies (fX): * fX = 2 to 2.5 MHz (REGC = VDD = 2.7 to 5.5 V, in PLL mode) * fX = 2 to 5 MHz (REGC = VDD = 4.5 V to 5.5 V, in PLL mode) * fX = 2 to 4 MHz (REGC = capacitor, VDD = 4.0 to 5.5 V, in PLL mode) * fX = 2 to 10 MHz (REGC = VDD = 2.7 to 5.5 V, in clock-through mode) (2) Subclock oscillator The sub-resonator oscillates a frequency of 32.768 kHz (fXT). (3) Main clock oscillator stop control This circuit generates a control signal that stops oscillation of the main clock oscillator. Oscillation of the main clock oscillator is stopped in the STOP mode or when the MCK bit of the PCC register = 1 (valid only when the CLS bit of the PCC register = 1).
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(4) Prescaler 1 This prescaler generates the clock (fXX to fXX/1024) to be supplied to the following on-chip peripheral functions: TM00 to TM05, TM50, TM51, TMH0, TMH1, CSI00 to CSI02, CSIA0, CSIA1, UART0 to UART2, I C0, I C1, ADC, DAC, and WDT2 (5) Prescaler 2 This circuit divides the CPU clock (fCPU) and main clock (fXX). The clock generated by prescaler 2 (fXX to fXX/32) is supplied to the selector that generates the internal system clock (fCLK). fCLK is the clock supplied to the INTC, ROM correction, ROM, and RAM blocks, and can be output from the CLKOUT pin. (6) Prescaler 3 This circuit divides the clock (fX) generated by the main clock oscillator to a specific frequency (32.768 kHz) and supplies that clock to the watch timer block. For details, refer to CHAPTER 11 WATCH TIMER FUNCTIONS. (7) PLL This circuit multiplies the clock (fX) generated by the main clock oscillator. It operates in two modes: clock-through mode in which fX is output as is, and PLL mode in which a multiplied clock is output. These modes can be selected by using the SELPLL bit of the PLL control register (PLLCTL). Operation of the PLL can be started or stopped by the PLLON bit of the PLLCTL register.
2 2
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6.3 Control Registers
(1) Processor clock control register (PCC) The processor clock control register (PCC) is a special register. Data can be written to this register only in combination of specific sequences (refer to 3.4.7 Special registers). This register can be read or written in 8-bit or 1-bit units. (1/2)
After reset: 03H R/W After reset: FFFFF828H
PCC
FRC
MCK
MFRC
CLSNote
CK3
CK2
CK1
CK0
FRC 0 1 Used Not used
Use of subclock on-chip feedback resistor
MCK 0 1 Operating Stopped
Operation of main clock
* Even if the MCK bit is set to 1 while the system is operating with the main clock as the CPU clock, the operation of the main clock does not stop. It stops after the CPU clock has been changed to the subclock. * When the main clock is stopped and the device is operating on the subclock, clear the MCK bit to 0 and wait until the oscillation stabilization time has been secured by the program before switching back to the main clock.
MFRC 0 1 Used Not used
Use of main clock on-chip feedback resistor
CLS 0 1 Main clock operation Subclock operation
Status of CPU clock (fCPU)
Note The CLS bit is a read-only bit.
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(2/2)
CK3 0 0 0 0 0 0 0 1 CK2 0 0 0 0 1 1 1 x CK1 0 0 1 1 0 0 1 x CK0 0 1 0 1 0 1 x x fXX fXX/2 fXX/4 fXX/8 (default value) fXX/16 fXX/32 Setting prohibited fXT Clock selection (fCLK/fCPU)
Cautions 1. Do not change the CPU clock (by using the CK3 to CK0 bits of the PCC register) while CLKOUT is being output. 2. Use a bit manipulation instruction to manipulate the CK3 bit. When using an 8-bit manipulation instruction, do not change the set values of the CK2 to CK0 bits. 3. When the CPU operates on the subclock and no clock is input to the X1 pin, do not access a register in which a wait occurs using an access method that causes a wait (refer to 3.4.8 (2) Access to special on-chip peripheral I/O register for details of the access methods). If a wait occurs, it can only be released by a reset. Remark x: Don't care
(a) Example of setting main clock operation subclock operation <1> Internal system clock check: Check that the following condition is satisfied. * Internal system clock (fXX) > subclock (32.768 kHz) x 4 When the above condition is not satisfied, change the CK2 to CK0 bits to satisfy the condition. At this time, do not change the CK3 bit. <2> CK3 1: <3> Subclock operation: Use of a bit manipulation instruction is recommended. Do not change CK2 to CK0 bits. It takes up to the following number of instructions after the CK3 bit is set until the subclock operation is started. Max.: (fCPU of main clock/fXT) Therefore, read the CLS bit to check if the subclock operation has started. <4> MCK 1: Set the MCK bit to 1 only when stopping the main clock.
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(b) Example of setting subclock operation main clock operation <1> MCK 0: <3> CK3 0: <4> Main clock operation: Main clock oscillation starts. Use of a bit manipulation instruction is recommended. Do not change CK2, CK1, and CK0 bits. It takes up to the following number of instructions after the CK3 bit is set until the main clock operation specified by CK2 to CK0 is started. Max.: (1/subclock frequency) Therefore, read the CLS bit to check if the subclock operation has started. (2) Power save control register (PSC) The power save control register (PSC) is a special register. Data can be written to this register only in a combination of specific sequences (refer to 3.4.7 Special registers). This register can be read or written in 8-bit or 1-bit units. <2> Insert wait cycles by program and wait until the oscillation of the main clock has been stabilized.
After reset: 00H <> PSC NMI2M
R/W
After reset: FFFFF1FEH <> <> INTM 0 0 <> STP 0
0
NMI0M
NMI2M 0 1
Controls non-maskable interrupt request (INTWDT2) from watchdog timer 2Note 1 INTWDT2 request enabled INTWDT2 request disabled Controls non-maskable interrupt request (NMI) from NMI pinNote 1 NMI request enabled NMI request disabled
NMI0M 0 1
INTM 0 1
Controls all maskable interrupt requests (INTxx)Note 1 INTxx request enabled INTxx request disabled
STP 0 1 Normal mode Standby modeNote 2
Sets operation mode
Notes 1. Setting these bits is valid only in the STOP mode. 2. Set STOP or IDLE mode using the PSM bit of the PSMR register. Remark For details of INTxx, refer to Tables 19-1 to 19-3 Interrupt Source Lists.
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(3) Power save mode register (PSMR) This is an 8-bit register that controls the operation status in the power save mode and the clock operation. This register can be read or written in 8-bit or 1-bit units. RESET input clears this register to 00H.
After reset: 00H
R/W
After reset: FFFFF820H <>
PSMR
0
0
0
0
0
0
0
PSM
PSM 0 1 IDLE mode STOP mode
Specifies operation in software standby mode
Cautions 1. Be sure to clear bits 1 to 7 of the PSMR register to 0. 2. The PSM bit is valid only when the STP bit of the PSC register is 1.
(4) Oscillation stabilization time selection register (OSTS) This register selects the oscillation stabilization time following reset or cancellation of the stop mode. Refer to 12.1.3 (1) Oscillation stabilization time selection register (OSTS).
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6.4 Operation
6.4.1 Operation of each clock The following table shows the operation status of each clock. Table 6-1. Operation Status of Each Clock
CLK bit = 0, MCK bit = 0 <1> Main clock oscillator (fX) Subclock oscillator (fXT) CPU clock (fCPU) Internal system clock (fCLK) Peripheral clock (fXX to fXX/1024) WT clock (main) WT clock (sub) WDT1 clock (fXW) WDT2 clock (main) WDT2 clock (sub) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x <2> <3> <4> <5> x CLS bit = 1, MCK bit = 0 <6> <7> CLS bit = 1, MCK bit = 1 <6> x <7> x
Remark CLS bit: O: x:
Bit 4 of the processor clock control register (PCC)
MCK bit: Bit 6 of the PCC register Operable Stopped
<1>: RESET pin input <2>: During oscillation stabilization time count <3>: HALT mode <4>: IDLE mode <5>: STOP mode <6>: Subclock operation mode <7>: Sub-IDLE mode 6.4.2 Clock output function The clock output function is used to output the internal system clock (fCLK) from the CLKOUT pin. The internal system clock (fCLK) is selected by using the CK3 to CK0 bits of the processor clock control register (PCC). The CLKOUT pin functions alternately as the PCM1 pin and functions as a clock output pin if so specified by the control register of port CM. The status of the CLKOUT pin is the same as the internal system clock in Table 6-1 and the pin can output the clock when it is in the operable status. It outputs a low level in the stopped status. However, the alternate-function pin function (PCM1: input mode) is selected in <1> and <2> after the RESET signal has been input. Consequently, the CLKOUT pin goes into a high-impedance state. 6.4.3 External clock input function An external clock can be directly input to the oscillator. Input the clock to the X1 pin and its inverse signal to the X2 pin. Set the MFRC bit of the PCC register to 1 (to cut off the feedback resistor). Note, however, that oscillation stabilization time is inserted even in the external clock mode.
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6.5 PLL Function
6.5.1 Overview The PLL function is used to output the operating clock of the CPU and peripheral macro at a frequency 4 times higher than the oscillation frequency, and select the clock-through mode. When PLL function is used: Input clock = 2 to 5 MHz (fXX: 8 to 20 MHz) (usable voltage: VDD = 2.7 to 5.5 V) Clock-through mode: 6.5.2 Control register (1) PLL control register (PLLCTL) This 8-bit register controls the PLL function. This register can be read or written in 8-bit or 1-bit units. RESET input sets PLLCTL to 01H. Input clock = 2 to 10 MHz (fXX: 2 to 10 MHz)
After reset: 01H
R/W
After reset: FFFFF806H <> <>
Note
<>
Note
<> PLLON
PLLCTL
0
0
0
0
RTOST1
RTOST0
SELPLL
PLLON 0 1 PLL stopped PLL operating
PLL operation stop register
SELPLL 0 1
PLL clock selection register Clock-through operation PLL operation
Note For the RTOST1 and RTOST2 bits, refer to CHAPTER 10 REAL-TIME OUTPUT FUNCTION (RTO). Caution Be sure to set bits 4 to 7 to 0.
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6.5.3 Usage (1) To use PLL * After the RESET has been released, the PLL operates (PLLON = 1), but because the default mode is the clock-through mode (SELPLL = 0), select the PLL mode (SELPLL = 1). * To set the IDLE or STOP mode, first select the clock-through mode and then stop the PLL. To return from the IDLE or STOP mode, first enable PLL operation (PLLON = 1), and then select the PLL mode (SELPLL = 1). * To enable the PLL operation, first set PLLON to 1, wait for 200 s, and then set PLLSEL to 1. To stop the PLL, first select the clock-through mode (SELPLL = 0), wait for 8 clocks or more, and then stop the PLL (PLLON = 0). (2) When PLL is not used * The clock-through mode (SELPLL = 0) is selected after the RESET has been released, but the PLL is operating (PLLON = 1) and must therefore be stopped (PLLON = 0).
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05
The number of 16-bit timer/event counter 00 to 05 channels incorporated differs as follows depending on the product.
Product Name Number of channels V850ES/KF1 2 channels (TM00, TM01) V850ES/KG1 4 channels (TM00 to TM03) V850ES/KJ1 6 channels (TM00 to TM05)
7.1 Functions
16-bit timer/event counters 00 to 05 have the following functions. (1) Interval timer Generates an interrupt at predetermined time intervals. (2) PPG output Can output a rectangular wave with any frequency and any output pulse width. (3) Pulse width measurement Can measure the pulse width of a signal input from an external source. (4) External event counter Can measure the pulse width of a signal input from an external source. (5) Square-wave output Can output a square wave of any frequency. (6) One-shot pulse output (16-bit timer/event counters 00, 01, 04 and 05 only) Can output a one-shot pulse with any output pulse width.
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7.2 Configuration
16-bit timer/event counters 00 to 05 consist of the following hardware. Table 7-1. Configuration of 16-Bit Timer/Event Counters 00 to 05
Item Timer/counters Registers Timer outputs Control registersNote 16 bits x 1 x 6 channels (TM0n) 16-bit timer capture/compare register: 16 bits x 2 x 6 channels (CR0n0, CR0n1) 1 x 6 channels (TO0n) 16-bit timer mode control register n (TMC0n) Capture/compare control register n (CRC0n) 16-bit timer output control register (TOC0n) Prescaler mode register 0n (PRM0n) Configuration
Note To use the TI0n0, TI0n1, and TO0n pin functions, refer to Table 4-28 Settings When Port Pins Are Used for Alternate Functions. Remark n = 0 to 5 Figure 7-1 shows the block diagram.
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Figure 7-1. Block Diagram of 16-Bit Timer/Event Counter 0n
Internal bus
Capture/compare control CRC0n2CRC0n1 CRC0n0 register 0n (CRC0n)
Selector
INTTM0n0
Noise eliminator
Selector
Tl0n1
16-bit timer capture/compare register 0n0 (CR0n0) Match
Selector
Count clockNote
16-bit timer counter 0n (TM0n) Match
Clear
Output controller
TO0n
fXX/4
Noise eliminator
2
Noise eliminator
Tl0n0
16-bit timer capture/compare register 0n1 (CR0n1)
Selector
INTTM0n1
CRC0n2 PRM0n1 PRM0n0 Prescaler mode register 0n (PRM0n) TMC0n3 TMC0n2 TMC0n1 OVF0n OSPT0m OSPE0m TOC0n4 LVS0n LVR0n TOC0n1 TOE0n Timer output control register 0n (TOC0n) 16-bit timer mode control register 0n (TMC0n) Internal bus
Note Set by the PRM0n register. Remarks 1. " " are signals that can be directly connected to ports. m = 0, 1, 4, 5
2. n = 0 to 5
3. fXX: Internal system clock frequency (1) 16-bit timer counter 0n (TM0n) The TM0n register is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the input clock. The count value is reset to 0000H in the following cases. <1> At RESET input <2> If the TMC0n3 and TMC0n2 bits are cleared. <3> If the valid edge of TI0n0 is input in the mode in which clear & start occurs when inputting the valid edge of TI0n0 <4> If the TM0n register and the CR0n0 register match each other in the mode in which clear & start occurs on CR0n0 register match <5> If the OSPT0m bit is set or if the valid edge of TI0k0 is input in the one-shot pulse output mode Remark n = 0 to 5 m = 0, 1, 4, 5 k = 4, 5
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(2) 16-bit timer capture/compare register 0n0 (CR0n0) The CR0n0 register is a 16-bit register that combines capture register and compare register functions. Bit 0 (CRC0n0) of the capture/compare control register (CRC0n) is used to set whether to use the CR0n0 register as a capture register or as a compare register. (a) When using the CR0n0 register as a compare register The value set to the CR0n0 register and the count value set to the TM0n register are always compared and when these values match, an interrupt request signal (INTTM0n0) is generated. When the TM0n register is set to operate as an interval timer, CR0n0 can be used as a register for holding the interval time. (b) When using the CR0n0 register as a capture register The TM0n register count value is captured to the CR0n0 register by inputting a capture trigger. The valid edge of the TI0n0 pin or TI0n1 pin can be selected as the capture trigger. The valid edge of the TI0n0 pin or TI0n1 pin is set with prescaler mode register 0n (PRM0n). Table 7-2 shows the settings when the valid edge of the TI0n0 pin is specified as the capture trigger, and Table 7-3 shows the settings when the valid edge of the TI0n1 is specified as the capture trigger. Table 7-2. Valid Edge of TI0n0 Pin and Capture Trigger of CR0n0 Register
ESn01 0 0 1 1 ESn00 0 1 0 1 Valid Edge of TI0n0 Pin Falling edge Rising edge Setting prohibited Both rising and falling edges Capture Trigger of CR0n0 Register Rising edge Falling edge Setting prohibited No capture operation
Remark n = 0 to 5 Table 7-3. Valid Edge of TI0n1 Pin and Capture Trigger of CR0n0 Register
ESn11 0 0 1 1 ESn10 0 1 0 1 Valid Edge of TI0n1 Pin Falling edge Rising edge Setting prohibited Both rising and falling edges Capture Trigger of CR0n0 Register Falling edge Rising edge Setting prohibited Both rising and falling edges
Remark n = 0 to 5 The CR0n0 register is set by a 16-bit memory manipulation instruction. RESET input sets this register to 0000H.
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Cautions 1. Set a value other than 0000H to the CR0n0 register in the mode in which clear & start occurs upon a match of the values of the TM0n register and CR0n0 register. However, if 0000H is set to the CR0n0 register in the free-running mode or the TI0n0 valid edge clear mode, an interrupt request (INTTM0n0) is generated after an overflow (FFFFH). 2. When the P33, P35, P613, P92, and P94 pins are used as the valid edges of TI000, TI010, TI020, TI030, and TI051, they cannot be used as timer outputs (TO00 to TO03, TO05). Moreover, when used as TO00 to TO03 and TO05, these pins cannot be used as the valid edge of TI000, TI010, TI020, TI030, and TI051. 3. If, when the CR0n0 register is used as a capture register, the register read interval and capture trigger input conflict, the read data becomes undefined (but the capture data itself is normal). Moreover, when the count stop input and capture trigger input conflict, the capture data becomes undefined. 4. The CR0n0 register cannot be rewritten during TM0n register operation.
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(3) 16-bit timer capture/compare register 0n1 (CR0n1) The CR0n1 register is a 16-bit register that combines capture register and compare register functions. Bit 2 (CRC0n2) of the CRC0n register is used to set whether to use the CR0n1 register as a capture register or as a compare register. (a) When using the CR0n1 register as a compare register The value set to the CR0n1 register and the count value of the TM0n register are always compared and when these values match, an interrupt request signal (INTTM0n1) is generated. (b) When using the CR0n1 register as a capture register The TM0n register count value is captured to the CR0n1 register by inputting a capture trigger. The valid edge of the TI0n0 pin can be selected as the capture trigger. The valid edge of the TI0n0 pin is set with the PRM0n register. Table 7-4 shows the settings when the valid edge of the TI0n0 pin is specified as the capture trigger. Table 7-4. Valid Edge of TI0n0 Pin and Capture Trigger of CR0n1 Register
ESn01 0 0 1 1 ESn00 0 1 0 1 Valid Edge of TI0n0 Pin Falling edge Rising edge Setting prohibited Both rising and falling edges Capture Trigger of CR0n1 Register Falling edge Rising edge Setting prohibited Both rising and falling edges
Remark n = 0 to 5 The CR0n1 register is set by a 16-bit memory manipulation instruction. RESET input sets this register to 0000H. Cautions 1. Set a value other than 0000H to the CR0n1 register in the mode in which clear & start occurs upon a match of the values of the TM0n register and CR0n0 register. However, if 0000H is set to the CR0n1 register in the free-running mode or the TI0n1 valid edge clear mode, an interrupt request (INTTM0n1) is generated after an overflow (FFFFH). 2. When the P33, P35, P613, P92, and P94 pins are used as the valid edges of TI000, TI010, TI020, TI030, and TI051, they cannot be used as timer outputs (TO00 to TO03, TO05). Moreover, when used as TO00 to TO03 and TO05, these pins cannot be used as the valid edges of TI000, TI010, TI020, TI030, and TI051. 3. If, when the CR0n1 register is used as a capture register, the register read interval and capture trigger input conflict, the read data becomes undefined (but the capture data itself is normal). Moreover, when the count stop input and capture trigger input conflict, the capture data becomes undefined. 4. The CR0n1 register can be rewritten during TM0n register operation only in the PPG output mode. Refer to 7.4.2 PPG output operation.
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7.3 Control Registers
The registers that control 16-bit timer/event counters 00 to 05 are as follows. * 16-bit timer mode control register 0n (TMC0n) * Capture/compare control register 0n (CRC0n) * 16-bit timer output control register 0n (TOC0n) * Prescaler mode register 0n (PRM0n) Remark To use the TI0n0, TI0n1, and TO0n pin functions, refer to Table 4-28 Settings When Port Pins Are Used for Alternate Functions. (1) 16-bit timer mode control register 0n (TMC0n) TMC0n is used to set the 16-bit timer operation mode, the 16-bit timer counter 0n (TM0n) clear mode, and the output timing, and to detect overflow. The TMC0n register is set by an 8-bit or 1-bit memory manipulation instruction. RESET input sets this register to 00H. Caution The TM0n register starts operating when a value other than 00 (operation stop mode) is set to the TMC0n3 and TMC0n2 bits of the TMC0n register. To stop the operation, set 00 to the TMC0n3 and TMC0n2 bits. Remark n = 0 to 5
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After reset: 00H
R/W
Address: FFFFF606H, FFFFF616H, FFFFF626H FFFFF636H, FFFFF646H, FFFFF656H 5 0 4 0 3 2 1 <0> OVF0n
7 TMC0n (n = 0 to 5 m = 4, 5) 0
6 0
TMC0n3 TMC0n2 TMC0n1
TMC0n3 TMC0n2 TMC0n1
Selection of operation mode and clear mode Operation stop (TM0n cleared to 0) Free-running mode
Selection of TO0n output timing Unchanged
Generation of interrupt Not generated
0 0 0
0 0 1
0 1 0
Match of TM0n and Generated upon CR0n0 or match of TM0n and CR0n1 match of TM0n and CR0n0 and match
0
1
1
Match of TM0m and of TM0n and CR0n1 CR0m0, match of TM0m and CR0m1, or valid edge of TI0m0Note
1
0
0
Clear & start with valid edge of TI0n0
Match of TM0m and CR0m0 or match of TM0m and CR0m1Note Match of TM0m and CR0m0, match of TM0m and CR0m1, or valid edge of TI0m0Note
1
0
1
1
1
0
Clear & start upon
Match of TM0n and
match of TM0n and CR0n0 or match of CR0n0 1 1 1 TM0n and CR0n1 Match of TM0m and CR0m0, match of TM0m and CR0m1, or valid edge of TI0m0Note OVF0n 0 1 No overflow Overflow Detection of overflow of 16-bit timer register 0n
Note Setting of TM00 to TM03 is prohibited. Cautions 1. Write to bits other than the OVF0n flag after stopping the timer operation. 2. The valid edge of the TI0n0 pin is set by prescaler mode register 0n (PRM0n). 3. When the mode in which the timer is cleared and started upon match of TM0n and CR0n0 is selected, the setting value of CR0n0 is FFFFH, and when the value of TM0n changes from FFFFH to 0000H, the OVF0n flag is set to 1. Remark TO0n: TI0n0: TM0n: Output pin of 16-bit timer/event counter 0n Input pin of 16-bit timer/event counter 0n 16-bit timer counter 0n
CR0n0: 16-bit timer capture/compare register 0n0 CR0n1: 16-bit timer capture/compare register 0n1
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(2) Capture/compare control register 0n (CRC0n) CRC0n controls the operation of 16-bit timer capture/compare registers 0n0 and 0n1 (CR0n0 and CRC0n1). The CRC0n register is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears CRC0n to 00H.
After reset: 00H
R/W
Address: FFFFF608H, FFFFF618H, FFFFF628H FFFFF638H, FFFFF648H, FFFFF658H 5 0 4 0 3 0 2 1 0
7 CRC0n (n = 0 to 5) CRC0n2 0 1 0
6 0
CRC0n2 CRC0n1 CRC0n0
Selection of operation mode of CR0n1 register Operation as compare register Operation as capture register
CRC0n1 0 1
Selection of capture trigger of CR0n0 register Capture at valid edge of TI0n1 Capture at inverse phase of valid edge of TI0n0
CRC0n0 0 1
Selection of operation mode of CR0n0 register Operation as compare register Operation as capture register
Cautions 1. Before setting the CRC0n register, be sure to stop the timer operation. 2. When the mode in which the timer is cleared and started upon match of the TM0n register and CR0n0 register is selected by 16-bit timer mode control register 0n (TMC0n), do not specify the CR0n0 register as the capture register. 3. When both the rising and falling edges are specified for the TI0n0 valid edge, capture operation is not performed. 4. To ensure reliable capture operation, a pulse longer than two of the count clocks selected by prescaler mode register 0n (PRM0n) is required. Remark TI0n0, TI0n1: Input pins of 16-bit timer/event counter 0n.
(3) 16-bit timer output control register 0n (TOC0n) TOC0n controls the operation of the 16-bit timer/event counter 0n output controller by setting or resetting the R-S flip-flop (LV0n), enabling or disabling inverse output, enabling or disabling the timer of 16-bit timer/event counter 0n, enabling or disabling the one-shot pulse output operation, and selecting an output trigger for a one-shot pulse by software (16-bit timer/event counters 02 and 03 do not have a one-shot pulse output function). The TOC0n register is set by an 8-bit memory manipulation instruction. RESET input clears TOC0n to 00H.
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After reset: 00H
R/W
Address: FFFFF609H, FFFFF619H, FFFFF629H FFFFF639H, FFFFF649H, FFFFF659H 5 4 3 LVS0n 2 LVR0n 1 TOC0n1 0 TOE0n
7 TOC0n (n = 0 to 5 m = 0, 1, 4, 5 k = 4, 5) 0
6
OSPT0mNote 1 OSPE0mNote 1 TOC0n4
OSPT0mNote 1 0 1
Control of output trigger for one-shot pulse by software Output disabled Output enabled
OSPE0mNote 1 0 1
Control of one-shot pulse output operation Successive pulse output One-shot pulse outputNote 2
TOC0n4 0 1
Control of timer output F/F upon match of CR0n1 register and TM0n register Inversion operation disabled Inversion operation enabled
LVS0n 0 0 1 1
LVR0n Setting of status of timer output F/F of 16-bit timer/event counter 0n 0 1 0 1 Unchanged Reset timer output F/F (0) Set timer output F/F (1) Setting prohibited
TOC0n1 0 1
Control of timer output F/F upon match of CR0n0 register and TM0n register Inversion operation disabled Inversion operation enabled
TOE0n 0 1
Control of output of 16-bit timer/event counter 0n Output disabled (output is fixed to 0 level) Output enabled
Notes 1. When using TM02 and TM03, be sure to set bits 5 and 6 to 0. When using TM00 and TM01, since the valid edges of the TI000 and TI010 pins cannot be used, set the TMC0n bit of the TMC00 and TMC01 registers to 0. 2. The one-shot pulse output operates normally in the free-running mode and the mode in which clear & start occurs on the valid edge of TI0k0. In the mode in which clear & start occurs on match between the TM0m register and the CR0m0 register, one-shot pulse output is not performed because no overflow occurs. Cautions 1. Be sure to stop the timer operation before setting other than the TOC0n4 bit. 2. The LVS0n and LVR0n bits are 0 when read after data has been set to them. 3. The OSPT0m bit is 0 when read because it is automatically cleared after data has been set. 4. Do not set (to 1) the OSPT0m bit other than for one-shot pulse output. 5. When performing successive writes to the OSPT0m bit, place an interval between writes of two or more operating clocks.
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(4) Prescaler mode register 0n (PRM0n) This register sets the count clock of 16-bit timer counter 0n (TM0n) and the valid edge of the TI0n0 and TI0n1 pin inputs. The PRM0n register is set by an 8-bit memory manipulation instruction. RESET input clears PRM0n to 00H. Cautions 1. When setting the count clock to the TI0n0 valid edge, do not set the mode in which clear & start occurs on TI0n0 valid edge and do not set the TI0n0 valid edge as the capture trigger. 2. Before setting the PRM0n register, be sure to stop the timer operation. 3. If 16-bit timer counter 0n (TM0n) operation is enabled by specifying the rising edge of both edges for the valid edge of the TI0n0 pin or TI0n1 pin while the TI0n0 pin or TI0n1 pin is high level immediately after system reset, the rising edge is detected immediately after the rising edge or both edges is specified. Be careful when pulling up the TI0n0 pin or TI0n1 pin. However, the rising edge is not detected when operation is enabled after it has been stopped. 4. When the P33, P35, P613, P92, and P94 pins are used as the valid edges of TI000, TI010, TI020, TI030, and TI051, they cannot be used as timer outputs (TO00 to TO03, TO05). Moreover, when used as TO00 to TO03 and TO05, these pins cannot be used as the valid edges of TI000, TI010, TI020, TI030, and TI051.
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(a) Prescaler mode register 00 (PRM00)
After reset: 00H 7 PRM00 ES011
R/W 6 ES010
Address: FFFFF607H 5 ES001 4 ES000 3 0 2 0 1 0
PRM001 PRM000
ES011 0 0 1 1
ES010 0 1 0 1 Falling edge Rising edge
Selection of valid edge of TI001
Setting prohibited Both rising and falling edges
ES001 0 0 1 1
ES000 0 1 0 1 Falling edge Rising edge
Selection of valid edge of TI000
Setting prohibited Both rising and falling edges
PRM001
PRM000
Selection of count clockNote 1 Count clock 20 MHz fXX 16 MHz 125 ns 250 ns 500 ns - -
0 0 1 1
0 1 0 1
fXX/2 fXX/4 fXX/8 Valid edge of TI000
Note 2
100 ns 200 ns 400 ns
Notes 1. When the internal clock is selected, set so as to satisfy the following conditions. VDD = 4.0 to 5.5 V: Count clock 10 MHz VDD = 2.7 to 4.0 V: Count clock 5 MHz 2. The external clock requires a pulse longer than two internal clocks (fXX/4). Remark fXX: Internal system clock frequency
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(b) Prescaler mode register 01 (PRM01)
After reset: 00H 7 PRM01 ES111
R/W 6 ES110
Address: FFFFF617H 5 ES101 4 ES100 3 0 2 0 1 0
PRM011 PRM010
ES111 0 0 1 1
ES110 0 1 0 1 Falling edge Rising edge
Selection of valid edge of TI0n1
Setting prohibited Both rising and falling edges
ES101 0 0 1 1
ES100 0 1 0 1 Falling edge Rising edge
Selection of valid edge of TI0n0
Setting prohibited Both rising and falling edges
PRM011
PRM010
Selection of count clockNote 1 Count clock 20 MHz fXX 16 MHz Setting prohibited 250 ns -
Note 2
0 0 1 1
0 1 0 1
fXX fXX/4 INTWT Valid edge of TI010
Setting prohibited 200 ns
- -
-
Notes 1. When the internal clock is selected, set so as to satisfy the following conditions. VDD = 4.0 to 5.5 V: Count clock 10 MHz VDD = 2.7 to 4.0 V: Count clock 5 MHz 2. The external clock requires a pulse longer than two internal clocks (fXX/4). Remark fXX: Internal system clock frequency
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(c) Prescaler mode register 02 (PRM02)
After reset: 00H 7 PRM02 ES211
R/W 6 ES210
Address: FFFFF627H 5 ES201 4 ES200 3 0 2 0 1 0
PRM021 PRM020
ES211 0 0 1 1
ES210 0 1 0 1 Falling edge Rising edge
Selection of valid edge of TI021
Setting prohibited Both rising and falling edges
ES201 0 0 1 1
ES200 0 1 0 1 Falling edge Rising edge
Selection of valid edge of TI020
Setting prohibited Both rising and falling edges
PRM021
PRM020
Selection of count clockNote 1 Count clock 20 MHz fXX 16 MHz 125 ns 250 ns 500 ns - -
0 0 1 1
0 1 0 1
fXX/2 fXX/4 fXX/8 Valid edge of TI020
Note 2
100 ns 200 ns 400 ns
Notes 1. When the internal clock is selected, set so as to satisfy the following conditions. VDD = 4.0 to 5.5 V: Count clock 10 MHz VDD = 2.7 to 4.0 V: Count clock 5 MHz 2. The external clock requires a pulse longer than two internal clocks (fXX/4). Remark fXX: Internal system clock frequency
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(d) Prescaler mode register 03 (PRM03)
After reset: 00H 7 PRM03 ES311
R/W 6 ES310
Address: FFFFF637H 5 ES301 4 ES300 3 0 2 0 1 0
PRM031 PRM030
ES311 0 0 1 1
ES310 0 1 0 1 Falling edge Rising edge
Selection of valid edge of TI031
Setting prohibited Both rising and falling edges
ES301 0 0 1 1
ES300 0 1 0 1 Falling edge Rising edge
Selection of valid edge of TI030
Setting prohibited Both rising and falling edges
PRM031
PRM030
Selection of count clockNote 1 Count clock 20 MHz fXX 16 MHz 250 ns 1 s 32 s -
0 0 1 1
0 1 0 1
fXX/4 fXX/16 fXX/512 Valid edge of TI030
Note 2
200 ns 800 ns 25.6 s -
Notes 1. When the internal clock is selected, set so as to satisfy the following conditions. VDD = 4.0 to 5.5 V: Count clock 10 MHz VDD = 2.7 to 4.0 V: Count clock 5 MHz 2. The external clock requires a pulse longer than two internal clocks (fXX/4). Remark fXX: Internal system clock frequency
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(e) Prescaler mode register 04 (PRM04)
After reset: 00H 7 PRM04 ES411
R/W 6 ES410
Address: FFFFF647H 5 ES401 4 ES400 3 0 2 0 1 0
PRM041 PRM040
ES411 0 0 1 1
ES410 0 1 0 1 Falling edge Rising edge
Selection of valid edge of TI041
Setting prohibited Both rising and falling edges
ES401 0 0 1 1
ES400 0 1 0 1 Falling edge Rising edge
Selection of valid edge of TI040
Setting prohibited Both rising and falling edges
PRM041
PRM040
Selection of count clockNote 1 Count clock 20 MHz fXX 16 MHz 125 ns 250 ns 500 ns - -
0 0 1 1
0 1 0 1
fXX/2 fXX/4 fXX/8 Valid edge of TI040
Note 2
100 ns 200 ns 400 ns
Notes 1. When the internal clock is selected, set so as to satisfy the following conditions. VDD = 4.0 to 5.5 V: Count clock 10 MHz VDD = 2.7 to 4.0 V: Count clock 5 MHz 2. The external clock requires a pulse longer than two internal clocks (fXX/4). Remark fXX: Internal system clock frequency
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(f)
Prescaler mode register 05 (PRM05)
After reset: 00H 7 PRM05 ES511
R/W 6 ES510
Address: FFFFF657H 5 ES501 4 ES500 3 0 2 0 1 0
PRM051 PRM050
ES511 0 0 1 1
ES510 0 1 0 1 Falling edge Rising edge
Selection of valid edge of TI051
Setting prohibited Both rising and falling edges
ES501 0 0 1 1
ES500 0 1 0 1 Falling edge Rising edge
Selection of valid edge of TI050
Setting prohibited Both rising and falling edges
PRM051
PRM050
Selection of count clockNote 1 Count clock 20 MHz fXX 16 MHz Setting prohibited 250 ns 16 s -
0 0 1 1
0 1 0 1
fXX fXX/4 fXX/256 Valid edge of TI050
Note 2
Setting prohibited 200 ns 128 s -
Notes 1. When the internal clock is selected, set so as to satisfy the following conditions. VDD = 4.0 to 5.5 V: Count clock 10 MHz VDD = 2.7 to 4.0 V: Count clock 5 MHz 2. The external clock requires a pulse longer than two internal clocks (fXX/4). Remark fXX: Internal system clock frequency
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7.4 Operation
7.4.1 Operation as interval timer (16 bits) 16-bit timer/event counter 0n can be made to operate as an interval timer by setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown in Figure 7-2 (n = 0 to 5). Setting procedure The basic operation setting procedure is as follows. <1> Set the CRC0n register (see Figure 7-2 for the setting value). <2> Set any value to the CRC0n0 register. <3> Set the count clock using the PRM0n register. <4> Enable the INTTM0n0 interrupt (see CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION for details). <5> Set the TMC0n register: Start operation (see Figure 7-2 for the setting value). The interval timer repeatedly generates interrupts at the interval of the preset count value in 16-bit timer capture/compare register 0n0 (CR0n0). If the count value in 16-bit timer counter 0n (TM0n) matches the value set in the CR0n0 register, an interrupt request signal (INTTM0n0) is generated at the same time that the value of the TM0n register is cleared to 0 and counting is continued. The count clock of 16-bit timer/event counter 0n can be selected with bits 0 and 1 of prescaler mode register 0n (PRM0n). The value of the CR0n0 and CR0n1 registers cannot be changed during timer count operation. However, the CR0n1 register value can be changed in the PPG output mode. For details, refer to 7.4.2 PPG output operation. Remark n = 0 to 5
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Figure 7-2. Control Register Setting Contents During Interval Timer Operation
(a) 16-bit timer mode control register 0n (TMC0n)
TMC0n3 TMC0n2 TMC0n1 TMC0n 0 0 0 0 1 1 0/1 OVF0n 0
Clears & starts upon match between TM0n and CR0n0
(b) Capture/compare control register 0n (CRC0n)
CRC0n2 CRC0n1 CRC0n0 CRC0n 0 0 0 0 0 0/1 0/1 0 CR0n0 used as compare register
Remarks 1. 0/1: When these bits are reset to 0 or set to 1, other functions can be used together with the interval timer function. For details, refer to 7.3 (1) 16-bit timer mode control register 0n (TMC0n) and 7.3 (2) Capture/compare control register 0n (CRC0n). 2. n = 0 to 5
Figure 7-3. Configuration of Interval Timer
16-bit timer capture/compare register 0n0 (CR0n0)
INTTM0n0 Count clockNote
Selector
TI0n0
Noise eliminator fxx/4
16-bit timer counter 0n (TM0n)
OVF0n
Clear circuit
Note Set with PRM0n register. Remarks 1. " " indicates a signal that can be directly connected to a port.
2. fXX: Internal system clock frequency 3. n = 0 to 5
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Figure 7-4. Timing of Interval Timer Operation
t Count clock TM0n count value 0000H 0001H N 0000H 0001H Clear N N 0000H 0001H Clear N N N
Count start CR0n0 INTTM0n0 N
Interrupt acknowledgment Interrupt acknowledgment Interval time Interval time Interval time
Remarks 1. Interval time = (N + 1) x t: N = 0001H to FFFFH 2. n = 0 to 5
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7.4.2 PPG output operation 16-bit timer/event counter 0n can be used for PPG (Programmable Pulse Generator) output by setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown in Figure 7-5. Setting procedure The basic operation setting procedure is as follows. <1> Set the pins to the TO0n pin mode (see CHAPTER 4 PORT FUNCTIONS). <2> Set the CRC0n register (see Figure 7-5 for the setting value). <3> Set any value to the CRC0n0 register. <4> Set any value as a duty to the CR0n1 register. <5> Set the TOC0n register (see Figure 7-5 for the setting value). <6> Set the count clock using the PRM0n register. <7> Enable the INTTM0n0 interrupt (see CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION for details). <8> Set the TMC0n register: Start operation (see Figure 7-5 for the setting value). Note To change the duty value (CR0n1 register) during operation, refer to Caution 2 in Figure 7-5 Control Register Settings in PPG Output Operation. The PPG output function outputs a rectangular wave from the TO0n pin with the cycle specified by the count value set in advance to 16-bit timer capture/compare register 0n0 (CR0n0) and the pulse width specified by the count value set in advance to 16-bit timer capture/compare register 0n1 (CR0n1).
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Figure 7-5. Control Register Settings in PPG Output Operation
(a) 16-bit timer mode control register 0n (TMC0n)
TMC0n3 TMC0n2 TMC0n1 TMC0n 0 0 0 0 1 1 0 OVF0n 0
Clears and starts upon match between TM0n and CR0n0
(b) Capture/compare control register 0n (CRC0n)
CRC0n2 CRC0n1 CRC0n0 CRC0n 0 0 0 0 0 0 x 0 x: Don't care
CR0n0 used as compare register CR0n1 used as compare register
(c) 16-bit timer output control register 0n (TOC0n)
OSPT0n OSPE0n TOC0n4 TOC0n 0 0 0 1 LVS0n 0/1 LVR0n 0/1 TOC0n1 1 TOE0n 1
Enables TO0n output Inverts output upon match between TM0n and CR0n0 Specifies initial value of TO0n output F/F Inverts output upon match between TM0n and CR0n1 Disables one-shot pulse output (other than TM02, TM03)
Cautions 1. Make sure that 0000H < CR0n1 < CR0n0 FFFFH is set to the CR0n0 register and CR0n1 register. 2. The cycle of the pulse generated by PPG output is (CR0n0 setting value + 1). The duty factor is (CR0n1 setting value + 1) / (CR0n0 setting value + 1) Remark n = 0 to 5
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Figure 7-6. Configuration of PPG Output
16-bit capture/compare register 0n0 (CR0n0)
Selector
Count clockNote TI0k0 Noise eliminator fxx/4
16-bit timer counter 0n (TM0n)
Clear circuit
Output controller
TO0n
16-bit capture/compare register 0n1 (CR0n1)
Note The count clock is set by the PRM0n register. Remarks 1. " 2. k = 4, 5 n =0 to 5 " indicates a signal that can be directly connected to a port.
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Figure 7-7. PPG Output Operation Timing
t
Count clock TM0n count value 0000H 0001H Count starts Value loaded to CR0n0 Value loaded to CR0n1 TO0n Pulse width: (M + 1) x t 1 cycle: (N + 1) x t N M M-1 M N-1 N 0000H 0001H
Clear
Caution CR0n0 cannot be rewritten during TM0n operation. Remarks 1. 0000H < M < N FFFFH 2. Change the pulse width during TM0n operation (rewrite CR0n1) as follows in a PPG output operation. <1> Disable the timer output inversion operation based on a match of TM0n and CR0n1 (TOC0n4 = 0). <2> Disable the INTTM0n1 interrupt (TM0MKn1 =1). <3> Rewrite CR0n1. <4> Wait for a cycle of the TM0n count clock. <5> Enable the timer output inversion operation based on a match of TM0n and CR0n1 (TOC0n4 = 1). <6> Clear the interrupt request flag of INTTM0n1 (TM0IFn1 = 0). <7> Enable the INTTM0n1 interrupt (TM0MKn1 = 0). 3. n = 0 to 5
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7.4.3 Pulse width measurement The 16-bit timer counter (TM0n) can be used to measure the pulse widths of the signals input to the TI0n0 and TI0n1 pins. Measurement can be carried out with the TM0n register used as a free-running counter or by restarting the timer in synchronization with the edge of the signal input to the TI0n0 pin. Setting procedure The basic operation setting procedure is as follows. <1> Set the pins to the TI0n0 (or TI0n1) pin mode (see CHAPTER 4 PORT FUNCTIONS). <2> Set the CRC0n register (see Figures 7-8, 7-11, 7-14, and 7-16 for the setting value). <3> Set the count clock using the PRM0n register. <4> Enable the INTTM0n0 (or INTTM0n1) interrupt (see CHAPTER 19 PROCESSING FUNCTION for details). <5> Set the TMC0n register: Start operation (see Figures 7-8, 7-11, 7-14, and 7-16 for the setting value). Note When using two capture registers, set the TI0n0 and TI0n1 pins. (1) Pulse width measurement with free-running counter and one capture register If the edge specified by prescaler mode register 0n (PRM0n) is input to the TI0n0 pin when 16-bit timer counter 0n (TM0n) is operated as a free-running counter (refer to Figure 7-8), the value of the TM0n register is loaded to 16-bit timer capture/compare register 0n1 (CR0n1) and an external interrupt request signal (INTTM0n1) is set. The edge is specified by using bits 4 and 5 (ESn00, ESn01) of the PRM0n register. The rising edge, falling edge, or both the rising and falling edges can be selected. The valid edge is detected through sampling at a count clock cycle selected with the PRM0n register, and the capture operation is not performed until the valid edge is detected twice. As a result, noise with a short pulse width can be eliminated. Remark n = 0 to 5 INTERRUPT/EXCEPTION
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Figure 7-8. Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register
(a) 16-bit timer mode control register 0n (TMC0n)
TMC0n3 TMC0n2 TMC0n1 TMC0n 0 0 0 0 0 1 0/1 OVF0n 0
Free-running mode
(b) Capture/compare control register 0n (CRC0n)
CRC0n2 CRC0n1 CRC0n0 CRC0n 0 0 0 0 0 1 0/1 0
CR0n0 used as compare register CR0n1 used as capture register
Remarks 1. 0/1: When these bits are reset to 0 or set to 1, other functions can be used together with the pulse width measurement function. For details, refer to 7.3 (1) 16-bit timer mode control register 0n (TMC0n) and 7.3 (2) Capture/compare control register 0n (CRC0n). 2. n = 0 to 5
Figure 7-9. Configuration for Pulse Width Measurement with Free-Running Counter
Selector
Count clockNote
16-bit timer counter 0n (TM0n)
OVF0n
TI0n0
16-bit timer capture/compare register 0n1 (CR0n1) INTTM0n1 Internal bus
Note The count clock is set with the PRM0n register. Remarks 1. " " indicates a signal that can be directly connected to a port.
2. n = 0 to 5
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Figure 7-10. Timing of Pulse Width Measurement with Free-Running Counter and One Capture Register (with Both Edges Specified)
t Count clock TM0n count value TI0n0 pin input D0 D1 D2 D3 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D3
Value loaded to CR0n1 INTTM0n1
OVF0n Cleared by instruction (D1 - D0) x t (10000H - D1 + D2) x t (D3 - D2) x t
Remark n = 0 to 5
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(2) Measurement of two pulse widths with free-running counter The pulse widths of two signals respectively input to the TI0n0 pin and the TI0n1 pin can be simultaneously measured when 16-bit timer counter 0n (TM0n) is used as a free-running counter (refer to Figure 7-11). When the edge specified by bits 4 and 5 (ESn00, ESn01) of prescaler mode register 0n (PRM0n) is input to the TI0n0 pin, the value of the TM0n register is loaded to 16-bit timer capture/compare register 0n1 (CR0n1) and an external interrupt request signal (INTTM0n1) is set. When the edge specified by bits 6 and 7 (ESn10 and ESn11) of the PRM0n register is input to the TI0n1 pin, the value of the TM0n register is loaded to 16-bit timer capture/compare register 0n0 and an external interrupt request signal (INTTM0n0) is set. The edges of the TI0n0 and TI0n1 pins are specified by bits 4 and 5 (ESn00 and ESn01) and bits 6 and 7 (ESn10, ESn11) of the PRM0n register, respectively. The rising, falling, or both rising and falling edges can be specified. The valid edge of the TI0n0 pin is detected through sampling at the count clock cycle selected with the PRM0n register, and the capture operation is not performed until the valid level is detected twice. As a result, noise with a short pulse width can be eliminated. Remark n = 0 to 5 Figure 7-11. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter
(a) 16-bit timer mode control register 0n (TMC0n)
TMC0n3 TMC0n2 TMC0n1 TMC0n 0 0 0 0 0 1 0/1 OVF0n 0
Free-running mode
(b) Capture/compare control register 0n (CRC0n)
CRC0n2 CRC0n1 CRC0n0 CRC0n 0 0 0 0 0 1 0 1
CR0n0 used as capture register Captures to CR0n0 at valid edge of TI0n1 pin CR0n1 used as capture register
Remarks 1. 0/1: When these bits are reset to 0 or set to 1, other functions can be used together with the pulse width measurement function. For details, refer to 7.3 (1) 16-bit timer mode control register 0n (TMC0n). 2. n = 0 to 5
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* Capture operation (free-running mode) The following figure illustrates the operation of the capture register when the capture trigger is input. Figure 7-12. CR0n1 Capture Operation with Rising Edge Specified
Count clock TM0n TI0n0 Rising edge detection CR0n1 INTTM0n1 n n-3 n-2 n-1 n n+1
Remark n = 0 to 5
Figure 7-13. Timing of Pulse Width Measurement with Free-Running Counter (with Both Edges Specified)
t Count clock TM0n count value TI0n0 pin input Value loaded to CR0n1 INTTM0n1 TI0n1 pin input Value loaded to CR0n0 INTTM0n0 OVF0n (D1 - D0) x t (10000H - D1 + D2) x t (10000H - D1 + (D2 + 1)) x t (D3 - D2) x t D1 D2 + 1 D0 D1 D2 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D2 + 1 D2 + 2 D3
Remark n = 0 to 5
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(3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 0n (TM0n) is used as a free-running counter (refer to Figure 7-14), the pulse width of the signal input to the TI0n0 pin can be measured. When the edge specified by bits 4 and 5 (ESn00 and ESn01) of prescaler mode register 0n (PRM0n) is input to the TI0n0 pin, the value of the TM0n register is loaded to 16-bit timer capture/compare register 0n1 (CR0n1) and an external interrupt request signal (INTTM0n1) is set. The value of the TM0n register is also loaded to 16-bit timer capture/compare register 0n0 (CR0n0) when an edge inverse to the one that triggers capturing to the CR0n1 register is input. The edge of the TI0n0 pin is specified by bits 4 and 5 (ESn00 and ESn01) of the PRM0n register. The rising or falling edge can be specified. The valid edge of the TI0n0 pin is detected through sampling at a count clock cycle selected with the PRM0n register, and the capture operation is not performed until the valid edge is detected twice. As a result, noise with a short pulse width can be eliminated. Caution If the valid edge of the TI0n0 pin is specified to be both the rising and falling edges, the CR0n0 register cannot perform capture operation. Figure 7-14. Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers
(a) 16-bit timer mode control register 0n (TMC0n)
TMC0n3 TMC0n2 TMC0n1 TMC0n 0 0 0 0 0 1 0/1 OVF0n 0
Free-running mode
(b) Capture/compare control register 0n (CRC0n)
CRC0n2 CRC0n1 CRC0n0 CRC0n 0 0 0 0 0 1 1 1
CR0n0 used as capture register Captures to CR0n0 at edge inverse to valid edge of TI0n0 pin CR0n1 used as capture register
Remarks 1. 0/1: When these bits are reset to 0 or set to 1, other functions can be used together with the pulse width measurement function. For details, refer to 7.3 (1) 16-bit timer mode control register 0n (TMC0n). 2. n = 0 to 5
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Figure 7-15. Timing of Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified)
t Count clock TM0n count value TI0n0 pin input Value loaded to CR0n1 Value loaded to CR0n0 INTTM0n1 OVF0n Cleared by instruction (D1 - D0) x t (10000H - D1 + D2) x t (D3 - D2) x t D0 D1 D2 D3 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D2 + 1 D3
Remark n = 0 to 5
(4) Pulse width measurement by restarting When the valid edge of the TI0n0 pin is detected, the pulse width of the signal input to the TI0n0 pin can be measured by clearing the TM0n register and then resuming counting after loading the count value of 16-bit timer counter 0n (TM0n) to 16-bit timer capture/compare register 0n1 (CR0n1) (refer to Figure 7-17). The edge is specified by bits 4 and 5 (ESn00 and ESn01) of prescaler mode register 0n (PRM0n). The rising or falling edge can be specified. The valid edge is detected through sampling at a count clock cycle selected with the PRM0n register and the capture operation is not performed until the valid level is detected twice. As a result, noise with a short pulse can be eliminated. Caution If the valid edge of the TI0n0 pin is specified to be both the rising and falling edges, capture/compare register 0n0 (CR0n0) cannot perform a capture operation.
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Figure 7-16. Control Register Settings for Pulse Width Measurement by Restarting
(a) 16-bit timer mode control register 0n (TMC0n)
TMC0n3 TMC0n2 TMC0n1 TMC0n 0 0 0 0 1 0 0/1 OVF0n 0
Clears and starts at valid edge of TI0n0 pin
(b) Capture/compare control register 0n (CRC0n)
CRC0n2 CRC0n1 CRC0n0 CRC0n 0 0 0 0 0 1 1 1
CR0n0 used as capture register Captures to CR0n0 at edge inverse to valid edge of TI0n0 pin CR0n1 used as capture register
Remarks 1. 0/1: When these bits are reset to 0 or set to 1, other functions can be used together with the pulse width measurement function. For details, refer to 7.3 (1) 16-bit timer mode control register 0n (TMC0n). 2. n = 0 to 5
Figure 7-17. Timing of Pulse Width Measurement by Restarting (with Rising Edge Specified)
t Count clock TM0n count clock TI0n0 pin input Value loaded to CR0n1 Value loaded to CR0n0 INTTM0n1 (D1 + 1) x t (D2 + 1) x t D0 D1 D2 0000H 0001H D0 0000H 0001H D1 D2 0000H 0001H
Remark n = 0 to 5
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7.4.4 Operation as external event counter Setting procedure The basic operation setting procedure is as follows. <1> Set the pins to the TI0n0 pin mode (see CHAPTER 4 PORT FUNCTIONS). <2> Set the CRC0n register (see Figure 7-18 for the setting value). <3> Set the count clock using the PRM0n register. <4> Set any value (except for 0000H) to the CRC0n0 register. <5> Enable the INTTM0n0 (or INTTM0n1) interrupt (see CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION for details). <6> Set the TMC0n register: Start operation (see Figure 7-18 for the setting value). The external event counter counts the number of clock pulses input to the TI0n0 pin from an external source by using 16-bit timer counter 0n (TM0n). Each time the valid edge specified by prescaler mode register 0n (PRM0n) has been input, the TM0n register is incremented. When the count value of the TM0n register matches the value of 16-bit timer capture/compare register 0n0 (CR0n0), the TM0n register is cleared to 0 and an interrupt request signal (INTTM0n0) is generated. Set the CR0n0 register to a value other than 0000H (one-pulse count operation is not possible). The edge is specified by bits 4 and 5 (ESn00 and ESn01) of the PRM0n register. The rising, falling, or both the rising and falling edges can be specified. The valid edge is detected through sampling at a count clock cycle of fXX/4, and the capture operation is not performed until the valid level is detected twice. As a result, noise with a short pulse width can be eliminated. Cautions 1. When using the TM00 to TM03 registers as external event counters, the timer outputs (TO00 to TO03) cannot be used. 2. The value of the CR0n0 and CR0n1 registers cannot be changed during timer count operation. However, the CR0n1 register value can be changed in the PPG output mode. For details, refer to 7.4.2 PPG output operation. Remark n = 0 to 5
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Figure 7-18. Control Register Settings in External Event Counter Mode
(a) 16-bit timer mode control register 0n (TMC0n)
TMC0n3 TMC0n2 TMC0n1 TMC0n 0 0 0 0 1 1 0/1 OVF0n 0
Clears and starts on match between TM0n and CR0n0
(b) Capture/compare control register 0n (CRC0n)
CRC0n2 CRC0n1 CRC0n0 CRC0n 0 0 0 0 0 0/1 0/1 0
CR0n0 used as compare register
Remarks 1. 0/1: When these bits are reset to 0 or set to 1, other functions can be used together with the external event counter function. For details, refer to 7.3 (1) 16-bit timer mode control register 0n (TMC0n) and 7.3 (2) Capture/compare control register 0n (CRC0n). 2. n = 0 to 5
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Figure 7-19. Configuration of External Event Counter
16-bit timer capture/compare register 0n0 (CR0n0) Match Clear
Selector
INTTM0n0
Count clock
Note
16-bit timer counter 0n (TM0n)
OVF0n
fxx/4 TI0n0 valid edge
Noise eliminator 16-bit timer capture/compare register 0n1 (CR0n1)
Internal bus
Note Set with the PRM0n register. Remarks 1. " " indicates a signal that can be directly connected to a port.
2. n = 0 to 5
Figure 7-20. Timing of External Event Counter Operation (with Rising Edge Specified)
TI0n0 pin input TM0n count value CR0n0 INTTM0n0 Count start 0000H 0001H 0002H 0003H 0004H 0005H N N-1 N 0000H 0001H 0002H 0003H
Cautions 1. Read the TM0n register when reading the count value of the external event counter. 2. Counting is not possible at the first valid edge after the external event counter mode is entered. Remark n = 0 to 5
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7.4.5 Square-wave output operation Setting procedure The basic operation setting procedure is as follows. <1> Set the count clock using the PRM0n register. <2> Set the CRC0n register (see Figure 7-21 for the setting value). <3> Set the TOC0n register (see Figure 7-21 for the setting value). <4> Set any value (except for 0000H) to the CRC0n0 register. <5> Set the pins to the TO0n pin mode (see CHAPTER 4 PORT FUNCTIONS). <6> Enable the INTTM0n0 interrupt (see CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION for details). <7> Set the TMC0n register: Start operation (see Figure 7-21 for the setting value). 16-bit timer/event counter 0n can be used to output a square wave with any frequency at an interval specified by the count value set in advance to 16-bit timer capture/compare register 0n0 (CR0n0). By setting bits 0 (TOE0n) and 1 (TOC0n1) of 16-bit timer output control register 0n (TOC0n) to 1, the output status of the TO0n pin is inverted at an interval set in advance to the CR0n0 register. In this way, a square wave of any frequency can be output. Caution The value of the CR0n0 and CR0n1 registers cannot be changed during timer count operation. However, the CR0n1 register value can be changed in the PPG output mode. For details, refer to 7.4.2 PPG output operation.
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Figure 7-21. Control Register Settings in Square-Wave Output Mode
(a) 16-bit timer mode control register 0n (TMC0n)
TMC0n3 TMC0n2 TMC0n1 TMC0n 0 0 0 0 1 1 0 OVF0n 0
Clears and starts upon match between TM0n and CR0n0
(b) Capture/compare control register 0n (CRC0n)
CRC0n2 CRC0n1 CRC0n0 CRC0n 0 0 0 0 0 0/1 0/1 0
CR0n0 used as compare register
(c) 16-bit timer output control register 0n (TOC0n)
OSPT0n OSPE0n TOC0n4 TOC0n 0 0 0 0 LVS0n 0/1 LVR0n 0/1 TOC0n1 1 TOE0n 1
Enables TO0n output Inverts output upon match between TM0n and CR0n0 Specifies initial value of TO0n output F/F Does not invert output upon match between TM0n and CR0n1 Disables one-shot pulse output (other than TM02 and TM03)
Remarks 1. 0/1: When these bits are reset to 0 or set to 1, other functions can be used together with the square-wave output function. For details, refer to 7.3 (2) Capture/compare control register 0n (CRC0n) and 7.3 (3) 16-bit timer output control register 0n (TOC0n). 2. n = 0 to 5
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Figure 7-22. Timing of Square-Wave Output Operation
Count clock TM0n count value CR0n0 INTTM0n0 TO0n pin output 0000H 0001H 0002H N N-1 N 0000H 0001H 0002H N-1 N 0000H
Remark n = 0 to 5
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7.4.6 One-shot pulse output operation The one-shot pulse output is valid only for 16-bit timer/event counters 00, 01, 04, and 05. 16-bit timer/event counter 0n can output a one-shot pulse in synchronization with a software trigger or an external trigger (TI0k0 pin input). Setting procedure The basic operation setting procedure is as follows. <1> Set the count clock using the PRM0m register. <2> Set the CRC0m register (see Figures 7-23 and 7-25 for the setting value). <3> Set the TOC0m register (see Figures 7-23 and 7-25 for the setting value). <4> Set any value to the CRC0m0 and CRC0m1 registers. <5> Set the pins to the TO0m0 pin mode (see CHAPTER 4 PORT FUNCTIONS). <6> Enable the INTTM0m0 interrupt (see CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION for details). <7> Set the TMC0m register: Start operation (see Figures 7-23 and 7-25 for the setting value). (1) One-shot pulse output with software trigger (16-bit timer/event counters 00, 01, 04, and 05 only) A one-shot pulse can be output from the TO0m pin by setting 16-bit timer mode control register 0m (TMC0m), capture/compare control register 0m (CRC0m), and 16-bit timer output control register 0m (TOC0m) as shown in Figure 7-23, and by setting bit 6 (OSPT0m) of the TOC0m register to 1 by software. By setting the OSPT0m bit to 1, 16-bit timer/event counter 0m is cleared and started, and its output becomes active at the count value (N) set in advance to 16-bit timer capture/compare register 0m1 (CR0m1). After that, the output becomes inactive at the count value (M) set in advance to 16-bit timer capture/compare register 0m0 (CR0m0)
Note
.
Even after the one-shot pulse has been output, the TM0m register continues its operation. To stop the TM0m register, the TMC0m3 and TMC0m2 bits of the TMC0m register must be set to 00. Note The case where N < M is described here. When N > M, the output becomes active with the CR0m0 register and inactive with the CR0m1 register. Cautions 1. Do not set the OSPT0m bit while the one-shot pulse is being output. To output the oneshot pulse again, wait until the current one-shot pulse output is completed. 2. The value of the CR0m0 and CR0m1 registers cannot be changed during timer count operation. However, the CR0m1 register value can be changed in the PPG output mode. For details, refer to 7.4.2 PPG output operation. Remark m = 0, 1, 4, 5 k = 4, 5
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Figure 7-23. Control Register Settings for One-Shot Pulse Output with Software Trigger
(a) 16-bit timer mode control register 0m (TMC0m)
TMC0m3 TMC0m2 TMC0m1 TMC0m 0 0 0 0 0 1 0 OVF0m 0
Free-running mode
(b) Capture/compare control register 0m (CRC0m)
CRC0m2 CRC0m1 CRC0m0 CRC0m 0 0 0 0 0 0 0/1 0
CR0m0 used as compare register CR0m1 used as compare register
(c) 16-bit timer output control register 0m (TOC0m)
OSPT0m OSPE0m TOC0m4 TOC0m 0 0 1 1 LVS0m 0/1 LVR0m 0/1 TOC0m1 1 TOE0m 1
Enables TO0m output Inverts output upon match between TM0m and CR0m0 Specifies initial value of TO0m output F/F Inverts output upon match between TM0m and CR0m1 Sets one-shot pulse output mode
Set to 1 for output
Caution Do not set 0000H to the CR0m0 and CR0m1 registers. Remarks 1. 0/1: When these bits are reset to 0 or set to 1, other functions can be used together with the oneshot pulse output function. For details, refer to 7.3 (2) Capture/compare control register 0n (CRC0n) and 7.3 (3) 16-bit timer output control register 0n (TOC0n). 2. m = 0, 1, 4, 5
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Figure 7-24. Timing of One-Shot Pulse Output Operation with Software Trigger
Set TMC0m to 0CH (TM0m count starts) Count clock TM0m count 0000H 0001H CR0m1 set value CR0m0 set value OSPT0m INTTM0m1 INTTM0m0 TO0m pin output N M N N+1 N M 0000H N-1 N N M M-1 M M+1 M+2 N M
Caution 16-bit timer counter 0m starts operating as soon as a value other than 00 (operation stop mode) is set to the TMC0m3 and TMC0m2 bits. Remark m = 0, 1, 4, 5 N(2) One-shot pulse output with external trigger (16-bit timer/event counters 04 and 05 only) A one-shot pulse can be output from the TO0k pin by setting 16-bit timer mode control register 0k (TMC0k), capture/compare control register 0k (CRC0k), and 16-bit timer output control register 0k (TOC0k) as shown in Figure 7-25, and by using the valid edge of the TI0k0 pin as an external trigger. The valid edge of the TI0k0 pin is specified by bits 4 and 5 (ESk00, ESk01) of prescaler mode register 0k (PRM0k). The rising, falling, or both the rising and falling edges can be specified. When the valid edge of the TI0k0 pin is detected, the 16-bit timer/event counter is cleared and started, and the output becomes active at the count value set in advance to 16-bit timer capture/compare register 0k1 (CR0k1). After that, the output becomes inactive at the count value set in advance to 16-bit timer capture/compare register 0k0 (CR0k0)
Note
.
Note The case where N < M is described here. When N > M, the output becomes active with the CR0k0 register and inactive with the CR0k1 register. Cautions 1. Even if the external trigger is generated again while the one-shot pulse is output, it is ignored. 2. The value of the CR0k0 and CR0k1 registers cannot be changed during timer count operation. However, the CR0k1 register value can be changed in the PPG output mode. For details, refer to 7.4.2 PPG output operation. Remark k = 4, 5
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Figure 7-25. Control Register Settings for One-Shot Pulse Output with External Trigger
(a) 16-bit timer mode control register 0k (TMC0k)
TMC0k3 TMC0k 0 0 0 0 1 TMC0k2 TMC0k1 0 0 OVF0k 0
Clears and starts at valid edge of TI0k0 pin
(b) Capture/compare control register 0k (CRC0k)
CRC0k2 CRC0k1 CRC0k 0 0 0 0 0 0 0/1 CRC0k0 0
CR0k0 used as compare register CR0k1 used as compare register
(c) 16-bit timer output control register 0k (TOC0k)
OSPT0k OSPE0k TOC0k4 TOC0k 0 0 1 1 LVS0k 0/1 LVR0k 0/1 TOC0k1 1 TOE0k 1
Enables TO0k output Inverts output upon match between TM0k and CR0k0 Specifies initial value of TO0k output F/F Inverts output upon match between TM0k and CR0k1 Sets one-shot pulse output mode
Caution Do not set the CR0k0 and CR0k1 registers to 0000H. Remarks 1. 0/1: When these bits are reset to 0 or set to 1, other functions can be used together with the oneshot pulse output function. For details, refer to 7.3 (2) Capture/compare control register 0n (CRC0n) and 7.3 (3) 16-bit timer output control register 0n (TOC0n). 2. k = 4, 5
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Figure 7-26. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified)
Set TMC0k to 08H (TM0k count starts) Count clock TM0k count value 0000H 0001H CR0k1 set value CR0k0 set value TI0k0 pin input INTTM0k1 INTTM0k0 TO0k pin output N M 0000H N M N N+1 N+2 N M M-2 M-1 M N M M+1 M+2
Caution 16-bit timer/event counter 0k starts operating as soon as a value other than 00 (operation stop mode) is set to the TMC0k2 and TMC0k3 bits. Remark k = 4, 5 N344
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7.4.7 Cautions (1) Error on starting timer An error of up to 1 clock occurs before the match signal is generated after the timer has been started. This is because 16-bit timer counter 0n (TM0n) is started asynchronously to the count pulse. Figure 7-27. Start Timing of 16-Bit Timer Counter 0n
Count pulse TM0n count value 0000H Timer start 0001H 0002H 0003H 0004H
Remark n = 0 to 5
(2) Setting 16-bit timer capture/compare register (in the mode in which clear & start occurs upon match between TM0n register and CR0n0 register) Set 16-bit timer capture/compare registers 0n0 and 0n1 (CR0n0 and CR0n1) to a value other than 0000H (when using these registers as event counters, one-pulse count operation is not possible). (3) Data hold timing of capture register If the valid edge of the TI0n0 pin is input while 16-bit timer capture/compare register 0n1 (CR0n1) is read, the CR0n1 register performs capture operation, but the capture value at this time is not guaranteed. However, the interrupt request signal (INTTM0n1) is generated as a result of detection of the valid edge. Figure 7-28. Data Hold Timing of Capture Register
Count pulse TM0n count value Edge input INTTM0n1 Capture read signal CR0n1 interrupt value X Capture operation N+ 1 Capture operation is performed but not guaranteed N N+1 N+2 M M+1 M+2
Remark n = 0 to 5
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(4) Setting valid edge Before setting the valid edge of the TI0n0 pin, stop the timer operation by setting bits 2 and 3 (TMC0n2 and TMC0n3) of 16-bit timer mode control register 0n to 0, 0. Set the valid edge by using bits 4 and 5 (ESn00 and ESn01) of prescaler mode register 0n (PRM0n). (5) Re-triggering one-shot pulse (TM00, TM01, TM04, TM05) (a) One-shot pulse output by software When a one-shot pulse is output, do not set the OSPT0m bit to 1. Do not output the one-shot pulse again until INTTM0m0, which occurs upon match with the CR0m0 register, or INTTM0m1, which occurs upon match with the CR0m1 register, occurs. Remark m = 4, 5 (b) One-shot pulse output with external trigger If the external trigger occurs again while a one-shot pulse is output, it is ignored. (c) One-shot pulse output function When using the one-shot pulse output of timer 0 with a software trigger, do not change the level of the TI0m0 pin or its alternate function port pin. Because the external trigger is effective even in this case, the timer is cleared and started even with the TI0m0 pin or its alternate function port pin level, resulting in the output of a pulse at an undesired timing. Remark m = 4, 5
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(6) Operation of OVF0n flag (a) Setting of OVF0n flag The OVF0n flag is set to 1 in the following case in addition to when the TM0n register overflows. Select the mode in which clear & start occurs upon match between the TM0n register and the CR0n0 register. Set the CR0n0 register to FFFFH When the TM0n register is cleared from FFFFH to 0000H upon match with the CR0n register Figure 7-29. Operation Timing of OVF0n Flag
Count pulse CR0n0 TM0n OVF0n INTTM0n0 FFFEH FFFFH FFFFH 0000H 0001H
Remark n = 0 to 5
(b) Clearing of OVF0n flag After the TM0n register overflows, clearing OVF0n flag is invalid and set again even if the OVF0n flag is cleared before the next count clock is counted (before TM0n register becomes 0001H). Remark n = 0 to 5 (7) Conflict between read period and capture trigger input If the read period conflicts with the capture trigger input when 16-bit timer capture/compare registers 0n0 and 0n1 (CR0n0 and CR0n1) are being used as capture registers, the capture trigger input has priority and the read data of the CR0n0 and CR0n1 registers becomes undefined. Remark n = 0 to 5
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(8) Timer operation (a) CR0n1 register capture Even if 16-bit timer counter 0n (TM0n) is read, the read data cannot be captured into 16-bit timer capture/compare register 0n1 (CR0n1). (b) TI0n0, TI0n1 pin acknowledgement Regardless of the CPU's operation mode, if the timer is stopped, signals input to the TI0n0 and TI0n1 pins are not acknowledged. (c) One-shot pulse output (16-bit timer/event counters 00, 01, 04, and 05 only) One-shot pulse output operates normally in either the free-running mode or the mode in which clear & start occurs on the valid edge of the TI0k0 pin. Because no overflow occurs in the mode in which clear & start occurs upon match between the TM0m register and the CR0m0 register, one-shot pulse output is not possible. Remark n = 0 to 5 m = 0, 1, 4, 5 k = 4, 5 (9) Capture operation (a) If valid edge of TI0n0 is specified for count clock If the valid edge of TI0n0 is specified for the count clock, the capture register that specified TI0n0 as the trigger does not operate normally. (b) If both rising and falling edges are selected for valid edge of TI0n0 If both the rising and falling edges are selected for the valid edge of TI0n0, capture operation is not performed. (c) To ensure that signals from TI0n1 and TI0n0 are correctly captured For the capture trigger to capture the signals from TI0n1 and TI0n0 correctly, a pulse longer than two of the count clocks selected by prescaler mode register 0n (PRM0n) is required. (d) Interrupt request input Although a capture operation is performed at the falling edge of the count clock, an interrupt request signal (INTTM0n0, INTTM0n1) is generated at the rising edge of the next count clock. Remark n = 0 to 5
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(10) Compare operation (a) When overwriting CR0n1 register during timer operation in PPG output mode When overwriting 16-bit timer capture/compare register 0n1 (CR0n1) while the timer is operating, if the new value is close to and larger than the timer value, match interrupt request generation may not be performed normally. (b) When setting CR0n0, CR0n1 to compare mode When set to the compare mode, the CR0n0 and CR0n1 registers do not perform capture operation even if a capture trigger is input. Caution The value of the CR0n0 register cannot be changed during timer operation. The value of the CR0n1 register cannot be changed during timer operation other than in the PPG output mode. To change the CR0n1 register in the PPG output mode, refer to 7.4.2 PPG output operation. Remark n = 0 to 5 (11) Edge detection (a) When TI0n0 pin or TI0n1 pin is high level immediately following system reset When the TI0n0 or TI0n1 pin is high level immediately after a system reset, if either the rising edge or both edges of the TI0n0 pin or TI0n1 pin is specified as the valid edge and 16-bit timer counter 0n (TM0n) operation is enabled, the immediately following rising edge is detected. Care is therefore required when pulling up the TI0n0 pin or the TI0n1 pin. However, once the timer is stopped and the operation enabled again, the rising edge is not detected. (b) Sampling clock for noise elimination The sampling clock for noise elimination differs depending on whether the valid edge of TI0n0 is used for the count clock or as a capture trigger. In the former case, sampling is performed using fXX/4, and in the latter case, sampling is performed using the count clock selected by prescaler mode register 0n (PRM0n). The first capture operation does not start until the valid edges are sampled and two valid levels are detected, thus eliminating noise with a short pulse width. Remarks 1. fXX: Internal system clock frequency 2. n = 0 to 5
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CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
Two 8-bit timer/event counter 50 and 51 channels are incorporated in each product.
Product Name Number of channels V850ES/KF1 V850ES/KG1 2 channels (TM50, TM51) V850ES/KJ1
8.1 Functions
8-bit timer/event counter 5n has the following two modes (n = 0, 1). * Mode using 8-bit timer/event counter alone (individual mode) * Mode using cascade connection (16-bit resolution: cascade connection mode) These two modes are described below. (1) Mode using 8-bit timer/event counter alone (individual mode) 8-bit timer/event counter 5n operates as an 8-bit timer/event counter. The following functions can be used. * Interval timer * External event counter * Square-wave output * PWM output (2) Mode using cascade connection (16-bit resolution: cascade connection mode) 8-bit timer/event counters 50 and 51 operate as a 16-bit timer/event counter by connecting the TM50 and TM51 registers in cascade. The following functions can be used. * Interval timer with 16-bit resolution * External event counter with 16-bit resolution * Square-wave output with 16-bit resolution The block diagram of 8-bit timer/event counters 50 and 51 is shown next.
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Figure 8-1. Block Diagram of 8-Bit Timer/Event Counters 50 and 51
Internal bus
Mask circuit
8-bit timer compare register 5n (CR5n) Match
Selector
Selector
INTTM5n
TI5n Count clockNote
8-bit timer counter 5n (TM5n)
OVF
S INV Q R
Selector
TO5n
Clear 3 Selector S R Q Invert level
TCL5n2 TCL5n1 TCL5n0 Timer clock selection register 5n (TCL5n)
TCE5n TMC5n6 TMC5n4 LVS5n LVR5n TMC5n1 TOE5n 8-bit timer mode control register 5n (TMC5n) Internal bus
Note The count clock is set by the TCL5n register. Remarks 1. " " are signals that can be directly connected to ports.
2. n = 0 to 5.
8.2 Configuration
8-bit timer/event counters 50 and 51 consist of the following hardware. Table 8-1. Configuration of 8-Bit Timer/Event Counters 50 and 51
Item Timer registers Configuration 8-bit timer counters 50 and 51 (TM50, TM51) 16-bit timer counter 5 (TM5): Only when using cascade connection 8-bit timer compare registers 50, 51 (CR50, CR51) 16-bit timer compare register 5 (CR5): Only when using cascade connection TO50, TO51
Note
Registers Timer output Control registers
Timer clock selection registers 50, 51 (TCL50, TCL51) Timer clock selection register 5 (TCL5): Only when using cascade connection 8-bit timer mode control registers 50, 51 (TMC50, TMC51) 16-bit timer mode control register 5 (TMC5): Only when using cascade connection
Note When using the functions of the TI5n and TO5n pins, refer to Table 4-28 Settings When Port Pins Are Used for Alternate Functions.
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(1) 8-bit timer counters 50 and 51 (TM50, TM51) The TM5n register is an 8-bit read-only register that counts the count pulses. The counter is incremented in synchronization with the rising edge of the count clock. Through cascade connection, the TM5n registers can be used as a 16-bit timer. When using the TM50 register and the TM51 register in cascade as a 16-bit timer, these registers can be read by a 16-bit memory manipulation instruction. However, because these registers are connected by an internal 8-bit bus, the TM50 register and TM51 register must be read divided into two times. Therefore, read these registers twice and compare the values, taking into consideration that the reading occurs during a count change. In the following cases, the count value becomes 00H. * RESET input * When the TCE5n bit of 8-bit timer mode control register 5n (TMC5n) is cleared * The TM5n register and CR5n register match in the mode in which clear & start occurs on a match between the TM5n register and 8-bit timer compare register 5n (CR5n) Caution When connected in cascade, these registers become 00H even when the TCE50 bit in the lowest timer (TM50) is cleared. Remark n = 0, 1 (2) 8-bit timer compare registers 50 and 51 (CR50, CR51) The CR5n register can be read and written by an 8-bit memory manipulation instruction. In a mode other than the PWM mode, the value set to the CR5n register is always compared to the count value of 8-bit counter 5n (TM5n), and if the two values match, an interrupt request signal (INTTM5n) is generated. In the PWM mode, TM5n register overflow causes the TO5n pin output to change to the active level, and when the values of the TM5n register and the CR5n register match, the TO5n pin output changes to the inactive level. The value of the CR5n register can be set in the range of 00H to FFH. When using the TM50 register and TM51 register in cascade as a 16-bit timer, the CR50 register and CR51 register operate as 16-bit timer compare register 5 (CR5). The counter value and register value are compared in 16-bit lengths, and if they match, an interrupt request (INTTM50) is generated. Cautions 1. In the mode in which clear & start occurs upon a match of the TM5n register and CR5n register (TMC5n6 =0), do not write a different value to the CR5n register during the count operation. 2. In the PWM mode, set the CR5n register rewrite interval to three or more count clocks (clock selected with timer clock selection register 5n (TCL5n)). 3. Before changing the value of the CR5n register when using a cascade connection, be sure to stop the timer operation. Remark n = 0, 1
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8.3 Control Registers
The following two registers are used to control 8-bit timer/event counter 5n. * Timer clock selection register 5n (TCL5n) * 8-bit timer mode control register 5n (TMC5n) Remark To use the functions of the TI5n and TO5n pins, refer to Table 4-28 Settings When Port Pins Are Used for Alternate Functions. (1) Timer clock selection registers 50 and 51 (TCL50, TCL51) These registers set the count clock of 8-bit timer/event counter 5n and the valid edge of the TI5n pin input. The TCL5n register is set by an 8-bit memory manipulation instruction. RESET input clears this register to 00H.
After reset: 00H 7 TCL5n (n = 0, 1) 0
R/W 6 0
Address: TCL50 FFFFF5C4H, TCL51 FFFFF5C5H 5 0 4 0 3 0 2 TCL5n2 1 TCL5n1 0 TCL5n0
TCL5n2 TCL5n1 TCL5n0 Clock
Count clock selectionNote fXX 16 MHz 8 MHz - - 125 ns 250 ns 0.5 s 8 s 32 s - -
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Falling edge of TI5n Rising edge of TI5n fXX fXX/2 fXX/4 fXX/64 fXX/256 INTTM010
- - 62.5 ns 125 ns 250 ns 4 s 16 s
Note When the internal clock is selected, set so as to satisfy the following conditions. VDD = 4.0 to 5.5 V: Count clock 10 MHz VDD = 2.7 to 4.0 V: Count clock 5 MHz Caution Before overwriting the TCL5n register with different data, stop the timer operation. Remark When TM50 and TM51 are connected in cascade, the TCL51 register settings are invalid.
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(2) 8-bit timer mode control registers 50 and 51 (TMC50, TMC51) The TMC5n register performs the following six settings. * Controls counting by 8-bit timer counters 50 and 51 (TM50, TM51) * Selects the operation mode of the TM50 and TM51 registers * Selects the individual mode or cascade connection mode * Sets the status of the timer output flip-flop * Controls the timer output flip-flop or selects the active level in the PWM (free-running) mode * Controls timer output The TMC50 and TMC51 registers are set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears these registers to 00H.
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After reset: 00H <7> TMC5n (n = 0, 1) TCE5n 0 1 TCE5n
R/W 6 TMC5n6
Address: TMC50 FFFFF5C6H 5 0 4 TMC514
Note
TMC51 FFFFF5C7H 2 LVR5n 1 TMC5n1 <0> TOE5n
3 LVS5n
Control of count operation of 8-bit timer/event counter 5n Counting is disabled after the counter is cleared to 0 (counter disabled) Start count operation
TMC5n6 0 1
Selection of operation mode of 8-bit timer/event counter 5n Mode in which clear & start occurs on match between TM5n register and CR5n register PWM (free-running) mode
TMC514 Selection of individual mode or cascade connection mode for 8-bit timer/event counter 51 0 1 Individual mode Cascade connection mode (connected with TM50)
LVS5n 0 0 1 1
LVR5n 0 1 0 1 Unchanged
Setting of status of timer output F/F
Reset timer output F/F to 0 Set timer output F/F to 1 Setting prohibited
TMC5n1
Other than PWM (free-running) mode (TMC5n6 = 0) Controls timer F/F
PWM (free-running) mode (TMC5n6 = 1) Selects active level High active Low active
0 1
Disable inversion operation Enable inversion operation
TOE5n 0 1
Timer output control Disable output (TO5n pin is low level) Enable output
Note Bit 4 of the TMC50 register is fixed to 0. Cautions 1. Because the TO51 and TI51 pins are alternate functions of the same pin, only one can be used at one time. 2. The LVS5n and LVR5n bit settings are valid in modes other than the PWM mode. 3. Do not rewrite the TMC5n1 bit and TOE5n bit at the same time. 4. When switching to the PWM mode, do not rewrite the TMC5n6 bit and the LVS5n and LVR5n bits at the same time. 5. Before rewriting the TMC5n6 bit or TMC514 bit, stop the timer operation. Remarks 1. In the PWM mode, the PWM output is set to the inactive level by TCE5n = 0. 2. When the LVS5n and LVR5n bits are read, 0 is read. 3. The values of the TMC5n6, LVS5n, LVR5n, TMC5n1, and TOE5n bits are reflected to the TO5n output regardless of the TCE5n value.
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8.4 Operation
8.4.1 Operation as interval timer (8 bits) 8-bit timer/event counter 5n operates as an interval timer that repeatedly generates interrupts at the interval of the count value preset in 8-bit timer compare register 5n (CR5n). If the count value in 8-bit timer counter 5n (TM5n) matches the value set in the CR5n register, the value of the TM5n register is cleared to 0 and counting is continued, and at the same time, an interrupt request signal (INTTM5n) is generated. Setting method <1> Set each register. * TCL5n register: * CR5n register: Selects the count clock (t). Compare value (N) between the TM5n register and CR5n register (TMC5n register = 0000xx00B, x: don't care). <2> When the TCE5n bit of the TMC5n register is set to 1, the count operation starts. <3> When the values of the TM5n register and CR5n register match, INTTM5n is generated (TM5n register is cleared to 00H). <4> Then, INTTM5n is repeatedly generated at the same interval. To stop counting, set TCE5n = 0. Interval time = (N + 1) x t: N = 00H to FFH
* TMC5n register: Stops count operation and selects the mode in which clear & start occurs on a match
Caution During interval timer operation, do not rewrite the value of the CR5n register. Remark n = 0, 1 Figure 8-2. Timing of Interval Timer Operation (1/2)
Basic operation
t Count clock TM5n count value 00H 01H N 00H Clear N 01H N 00H Clear N N 01H N
Count start CR5n TCE5n INTTM5n N
Interrupt acknowledgment Interrupt acknowledgment Interval time Interval time
Remark n = 0, 1
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Figure 8-2. Timing of Interval Timer Operation (2/2)
When CR5n register = 00H
t Count clock TM5n count value 00H CR5n TCE5n INTTM5n Interval time 00H 00H 00H 00H
Remark n = 0, 1 When CR5n register = FFH
t Count clock TM5n count value 00H CR5n TCE5n INTTM5n Interrupt acknowledgment Interval time Interrupt acknowledgment FFH 01H FEH FFH FFH 00H FEH FFH FFH 00H
Remark n = 0, 1
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8.4.2 Operation as external event counter (8 bits) The external event counter counts the number of clock pulses input to the TI5n pin from an external source by using 8-bit timer counter 5n (TM5n). Each time the valid edge specified by timer clock selection register 5n (TCL5n) is input to the TI5n pin, the TM5n register is incremented. Either the rising edge or the falling edge can be specified as the valid edge. When the count value of the TM5n register matches the value of 8-bit timer compare register 5n (CR5n), the TM5n register is cleared to 0 and an interrupt request signal (INTTM5n) is generated. Setting method <1> Set each register. * TCL5n register: Selects the TI5n input edge. Falling edge of TI5n pin TLC5n = 00H Rising edge of TI5n pin TCL5n = 01H * CR5n register: Compare value (N) between the TM5n register and CR5n register, disables timer output F/F inversion operation, and disables timer output. (TMC5n register = 0000xx00B, x: don't care) <2> When the TCE5n bit of the TMC5n register is set to 1, the counter counts the number of pulses input from TI5n. <3> When the values of the TM5n register and CR5n register match, INTTM5n is generated (TM5n register is cleared to 00H). <4> Then, INTTM5n is generated each time the values of the TM5n register and CR5n register match. INTTM5n is generated when the valid edge of TI5n is input N + 1 times: N = 00H to FFH * TMC5n register: Stops count operation, selects the mode in which clear & start occurs on a match
Caution During external event counter operation, do not rewrite the value of the CR5n register. Remark n = 0, 1 Figure 8-3. Timing of External Event Counter Operation (with Rising Edge Specified)
TI5n TM5n count value 00H 01H 02H 03H 04H 05H N-1 N 00H 01H 02H 03H
Count start CR5n N
TCE5n INTTM5n
Remark n = 0, 1
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8.4.3 Square-wave output operation (8-bit resolution) A square wave with any frequency can be output at an interval specified by the value preset in 8-bit timer compare register 5n (CR5n). By setting the TOE5n bit of 8-bit timer mode control register 5n (TMC5n) to 1, the output status of the TO5n pin is inverted at an interval specified by the count value preset in the CR5n register. In this way, a square wave of any frequency can be output (duty = 50%) (n = 0, 1). Setting method <1> Set each register. * TCL5n register: * CR5n register: Selects the count clock (t). Compare value (N) between the TM5n register and CR5n register.
LVS5n 1 0 LVR5n 0 1 Timer Output F/F Status Setting High-level output Low-level output
* TMC5n register: Stops count operation, selects the mode in which clear & start occurs on a match
Enables timer output F/F inversion operation, and enables timer output. (TMC5n register = 00001011B or 00000111B) <2> When the TCE5n bit of the TMC5n register is set to 1, counting starts. <3> When the values of the TM5n register and CR5n register match, the timer output F/F is inverted. Moreover, INTTM5n is generated and the TM5n register is cleared to 00H. <4> Then, the timer F/F is inverted during the same interval and a square wave is output from the TO5n pin. 1/2t(N + 1) : N = 00H to FFH t(n + 1)
Frequency =
Caution Do not rewrite the value of the CR5n register during square-wave output.
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Figure 8-4. Timing of Square-Wave Output Operation
t Count clock TM5n count value 00H 01H N 00H Clear N 01H N 00H Clear N N 01H N
Count start CR5n TCE5n INTTM5n N
Interrupt acknowledgement TO5n Interval time
Interrupt acknowledgement
Interval time
Note The initial value of the TO5n output can be set using the LVS5n and LVR5n bits of the TMC5n register. Remark n = 0, 1
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8.4.4 8-bit PWM output operation By setting the TMC5n6 bit of 8-bit timer mode control register 5n (TMC5n) to 1, 8-bit timer/event counter 5n performs PWM output. Pulses with a duty factor determined by the value set in 8-bit timer compare register 5n (CR5n) are output from the TO5n pin. Set the width of the active level of the PWM pulse in the CR5n register. The active level can be selected using the TMC5n1 bit of the TMC5n register. The count clock can be selected using timer clock selection register 5n (TCL5n). PWM output can be enabled/disabled by the TOE5n bit of the TMC5n register. Caution The CR5n register rewrite interval must be three or more operation clocks (set by the TCL5n register). (1) Basic operation of PWM output Setting method <1> Set each register. * TCL5n register: * CR5n register: Selects the count clock (t). Compare value (N) unchanged.
TMC5n1 0 1 Active Level Selection Active-high Active-low
* TMC5n register: Stops count operation, selects PWM mode, and leave timer output F/F
Timer output enabled (TMC5n register = 01000001B or 01000011B) <2> When the TCE5n bit of the TMC5n register is set to 1, counting starts. PWM output operation <1> When counting starts, PWM output (output from the TO5n pin) outputs the inactive level until an overflow occurs. <2> When an overflow occurs, the active level set by setting method <1> is output. The active level is output until the value of the CR5n register and the count value of 8-bit timer counter 5n (TM5n) match. <3> When the value of the CR5n register and the count value match, the inactive level is output and continues to be output until an overflow occurs again. <4> Then, steps <2> and <3> are repeated until counting is stopped. <5> When counting is stopped by setting TCE5n to 0, PWM output becomes inactive. Cycle = 2 t, active level width = Nt, duty = N/2 : N = 00H to FFH
8 8
Remark n = 0, 1
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(a) Basic operation of PWM output Figure 8-5. Timing of PWM Output Operation
Basic operation (active level = H)
t Count clock TM5n count value CR5n TCE5n INTTM5n TO5n Active level Inactive level Active level
00H 01H N FFH 00H 01H 02H N N+1 FFH 00H 01H 02H M 00H
When CR5n register = 00H
t Count clock TM5n count value CR5n TCE5n INTTM5n TO5n Inactive level Inactive level
00H 01H 00H FFH 00H 01H 02H N N + 1N + 2 FFH 00H 01H 02H M 00H
When CR5n register = FFH
t Count clock TM5n count value CR5n TCE5n INTTM5n TO5n Inactive level Active level Inactive level Active level Inactive level
00H 01H FFH FFH 00H 01H 02H N N + 1N + 2 FFH 00H 01H 02H M 00H
Remark n = 0, 1
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(b) Operation based on CR5n register transitions Figure 8-6. Timing of Operation Based on CR5n Register Transitions
When the value of the CR5n register changes from N to M before the rising edge of the FFH clock The value of the CR5n register is reloaded at the overflow that occurs immediately after.
t Count clock TM5n count value CR5n TCE5n INTTM5n TO5n <2> <1> CR5n transition (N M) H N N-1N-2 N FFH 00H 01H 02H M M M-1M-2 FFH 00H 01H 02H M M-1M-2
When the value of the CR5n register changes from N to M after the rising edge of the FFH clock The value of the CR5n register is reloaded at the second overflow.
t Count clock TM5n count value CR5n TCE5n INTTM5n TO5n <1> CR5n transition (N M) <2> H N N-1N-2 N FFH 00H 01H 02H 03H N N N-1N-2 FFH 00H 01H 02H M M M-1M-2
Caution In the case of reload from the CR5n register between <1> and <2>, the value that is actually used differs (Read value: M; Actual value of CR5n register: N). Remark n = 0, 1
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8.4.5 Operation as interval timer (16 bits) The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 are provided with a 16-bit register that can be used only during cascade connection. The 16-bit resolution timer/event counter mode is selected by setting the TMC514 bit of 8-bit timer mode control register 51 (TMC51) to 1. 8-bit timer/event counter 5n operates as an interval timer by repeatedly generating interrupts using the count value preset in 16-bit timer compare register 5 (CR5) as the interval. Setting method <1> Set each register. * TCL50 register: * CR50 register: * CR51 register: Selects the count clock (t) (The TCL51 register does not need to be set in cascade connection) Compare value (N) ... Lower 8 bits (settable from 00H to FFH) Compare value (N) ... Higher 8 bits (settable from 00H to FFH) register and CR5 register (x: don't care) TMC50 register = 0000xx00B TMC51 register = 0001xx00B <2> Set the TCE51 bit of the TMC51 register to 1. Then set the TCE50 bit of the TMC50 register to 1 to start the count operation. <3> When the values of the TM5 register and CR5 register connected in cascade match, INTTM50 is generated (the TM5 register is cleared to 0000H). <4> INTTM50 is then generated repeatedly at the same interval. Interval time = (N + 1) x t: N = 0000H to FFFFH
* TMC50, TMC51 register: Selects the mode in which clear & start occurs on a match between TM5
Cautions 1. To write using 8-bit access during cascade connection, set the TCE51 bit to 1 at operation start and then set the TCE50 bit to 1. When operation is stopped, set the TCE50 bit to 0 and then set the TCE51 bit to 0. 2. During cascade connection, TI50 input, TO50 output, and INTTM50 signal output are used while TI51 input, TO51 output, and INTTM51 signal output are not, so set bits LVS51, LVR51, TMC511, and TOE51 to 0. 3. Do not change the value of the CR5 register during timer operation.
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Figure 8-35 shows a timing example of the cascade connection mode with 16-bit resolution. Figure 8-7. Cascade Connection Mode with 16-Bit Resolution
t Count clock TM50 count value 00H TM51 count value 00H CR50 CR51 TCE50 TCE51 INTTM50 Interval time Operation enabled, count start Interrupt occurrence, level inverted, counter cleared Operation stopped N M 01H N N- 1 FFH 00H 01H FFH 00H 02H FFH 00H 01H M-1 M N 00H 01H 00H A 00H B 00H
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8.4.6 Operation as external event counter (16 bits) The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 are provided with a 16-bit register that can be used only during cascade connection. The 16-bit resolution timer/event counter mode is selected by setting the TMC514 bit of 8-bit timer mode control register 51 (TMC51) to 1. The external event counter counts the number of clock pulses input to the TI50 pin from an external source using 16-bit timer counter 5 (TM5). Setting method <1> Set each register. * TCL50 register: Selects the TI50 input edge. (The TCL51 register does not have to be set during cascade connection.) Falling edge of TI50 TCL50 = 00H Rising edge of TI50 TCL50 = 01H * CR50 register: * CR51 register: Compare value (N) ... Lower 8 bits (settable from 00H to FFH) Compare value (N) ... Higher 8 bits (settable from 00H to FFH) between the TM5 register and CR5 register, disables timer output F/F inversion, and disables timer output. (x: don't care) TMC50 register = 0000xx00B TMC51 register = 0001xx00B <2> Set the TCE51 bit of the TMC51 register to 1. Then set the TCE50 bit of the TMC50 register to 1 and count the number of pulses input from TI50. <3> When the values of the TM5 register and CR5 register connected in cascade match, INTTM50 is generated (the TM5 register is cleared to 0000H). <4> INTTM50 is then generated each time the values of the TM5 register and CR5 register match. INTTM50 is generated when the valid edge of TI50 is input N + 1 times: N = 0000H to FFFFH
* TMC50, TMC51 registers: Stops count operation, selects the clear & stop mode entered on a match
Cautions 1. During external event counter operation, do not rewrite the value of the CR5n register. 2. To write using 8-bit access during cascade connection, set the TCE51 bit to 1 and then set the TCE50 bit to 1. When operation is stopped, set the TCE50 bit to 0 and then set the TCE51 bit to 0 (n = 0, 1). 3. During cascade connection, TI50 input and INTTM50 signal output are used while TI51 input, TO51 output, and INTTM51 signal output are not, so set bits LVS51, LVR51, TMC511, and TOE51 to 0. 4. Do not change the value of the CR5 register during external counter operation.
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8.4.7 Square-wave output operation (16-bit resolution) The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 are provided with a 16-bit register that can be used only during cascade connection. The 16-bit resolution timer/event counter mode is selected by setting the TMC514 bit of 8-bit timer mode control register 51 (TMC51) to 1. 8-bit timer/event counter 5n outputs a square wave of any frequency using the interval preset in 16-bit timer compare register 5 (CR5). Setting method <1> Set each register. * TCL50 register: * CR50 register: * CR51 register: TCL50 selects the count clock (t) (The TCL51 register does not have to be set in cascade connection) Compare value (N) ... Lower 8 bits (settable from 00H to FFH) Compare value (N) ... Higher 8 bits (settable from 00H to FFH) match between the TM5 register and CR5 register.
LVS50 1 0 LVR50 0 1 Timer Output F/F Status Settings High-level output Low-level output
* TMC50, TCM51 registers: Stops count operation, selects the mode in which clear & start occurs on a
Enables timer output F/F inversion, and enables timer output. TMC50 register = 00001011B or 00000111B TMC51 register = 00010000B <2> Set the TCE51 bit of the TMC51 register to 1. Then set the TCE50 bit of the TMC50 register to 1 to start the count operation. <3> When the values of the TM5 register and the CR5 register connected in cascade match, the TO50 timer output F/F is inverted. Moreover, INTTM50 is generated and the TM5 register is cleared to 0000H. <4> Then, the timer F/F is inverted during the same interval and a square wave is output from the TO50 pin. Frequency = 1/2t(N + 1): N = 0000H to FFFFH
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8.4.8 Cautions (1) Error on starting timer An error of up to 1 clock occurs before the match signal is generated after the timer has been started. This is because 8-bit timer counter 5n (TM5n) is started asynchronously to the count pulse. Figure 8-8. Start Timing of Timer 5n
Count pulse TM5n count value 00H Timer start 01H 02H 03H 04H
Remark n = 0, 1
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Two 8-bit timer H0 and H1 channels are incorporated in each product.
Product Name Number of channels V850ES/KF1 V850ES/KG1 2 channels (TMH0, TMH1) V850ES/KJ1
9.1 Functions
8-bit timers H0 and H1 have the following functions. * Interval timer with 8-bit accuracy * PWM pulse generator mode with 8-bit accuracy * Carrier generator mode with 8-bit accuracy
9.2 Configuration
8-bit timers H0 and H1 consist of the following hardware. Table 9-1. Configuration of 8-Bit Timers H0 and H1
Item Timer registers Register Timer outputs Control registers
Note
Configuration 8-bit timer counter Hn: 1 each 8-bit timer H compare register n0 (CMPn0): 1 each 8-bit timer H compare register n1 (CMPn1): 1 each 1 each (TOHn) 8-bit timer H mode register n (TMHMDn) 8-bit timer H carrier control register n (TMCYCn)
Note To use the TOHn pin function, refer to Table 4-28 Settings When Port Pins Are Used for Alternate Functions. Remark n = 0, 1
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Figure 9-1 shows the block diagram. Figure 9-1. Block Diagram of 8-Bit Timers H0 and H1
Internal bus
8-bit timer H mode register n (TMHMDn)
TMHEn CKSHn2 CKSHn1 CKSHn0 TMMDn1TMMDn0 TOLEVn TOENn
8-bit timer H compare register n1 (CMPn1)
8-bit timer H compare register n0 (CMPn0)
8-bit timer H carrier control register n (TMCYCn) RMCn NRZBn NRZn Reload/ interrupt control
INTTM5n
3
2
Decoder
Selector
TOHn
Match
fXX fXX/2 fXX/22 fXX/24 fXX/26 fXX/210 fXT
Interrupt generator
F/F R
Output controller
Level inversion
Selector
Carrier generator mode signal PWM mode signal
8-bit timer counter Hn Clear
Timer H enable signal
1 0
INTTMHn
Remarks 1. " 2. n = 0, 1
" indicates a signal that can be directly connected to a port.
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(1) 8-bit timer H compare register n0 (CMPn0) The CMPn0 register can be read and written by an 8-bit memory manipulation instruction. RESET input clears CMPn0 to 00H.
After reset: 00H 7 CMPn0
R/W 6
Address: FFFFF582H, FFFFF592H 5 4 3 2 1 0
Caution Rewriting the CMPn0 register during timer count operation is prohibited. Remark n = 0, 1 (2) 8-bit timer H compare register n1 (CMPn1) The CPMn1 register can be read and written by an 8-bit memory manipulation instruction. RESET input clears CMPn1 to 00H.
After reset: 00H 7 CMPn1
R/W 6
Address: FFFFF583H, FFFFF593H 5 4 3 2 1 0
The CMPn1 register can be rewritten during timer count operation. After the CMPn1 register is set, if the count value of 8-bit timer counter Hn and the value of the CMPn1 register match, an interrupt request signal (INTTMHn) is generated. At the same time, the value of 8-bit timer counter Hn is cleared to 00H. If the value of the CMPn1 register is rewritten during timer operation, the reload timing is when the count value of 8-bit timer counter Hn and the value of the CMPn1 register match. If the transfer timing and write to the CMPn1 register from the CPU conflict, transfer is not performed. Caution In the PWM pulse generator mode and carrier generator mode, be sure to set the CMPn1 register when starting the timer count operation (TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the same value to the CMPn1 register).
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9.3 Control Registers
The registers that control 8-bit timers H0 and H1 are as follows. * 8-bit timer H mode register n (TMHMDn) * 8-bit timer H carrier control register n (TMCYCn) Remarks 1. To use the TOHn pin function, refer to Table 4-28 Settings When Port Pins Are Used for Alternate Functions. 2. n = 0, 1 (1) 8-bit timer H mode registers 0 and 1 (TMHMD0, TMHMD1) These registers control the mode of the 8-bit timers H0 and H1. TMHMD0 and TMHMD1 registers are set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears TMHMD0 and TMHMD1 to 00H.
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(a) 8-bit timer H mode register 0 (TMHMD0)
After reset: 00H <7> TMHMD0 TMHE0
R/W 6
Address: FFFFF580H 5 4 3 2 1 <0> TOEN0
CKSH02 CKSH01 CKSH00 TMMD01 TMMD00 TOLEV0
TMHE0 0 1
8-bit timer H0 operation enable Stop timer count operation (8-bit timer counter H0 = 00H) Enable timer count operation (Counting starts when clock is input)
CKSH02 CKSH01 CKSH00
Selection of count clock Count clockNote fXX = 16.0 MHz 62.5 ns 125 ns 250 ns 1 s 4 s 64 s Setting prohibited
0 0 0 0 1 1
0 0 1 1 0 0 Other than above
0 1 0 1 0 1
fXX fXX/2 fXX/4 fXX/16 fXX/64 fXX/1024
TMMD01 TMMD00 0 0 1 1 0 1 0 1
8-bit timer H0 operation mode Interval timer mode Carrier generator mode PWM pulse generator mode Setting prohibited
TOLEV0 0 1 Low level High level
Timer output level control (default)
TOEN0 0 1 Disable output Enable output
Timer output control
Note Set so as to satisfy the following conditions. VDD = 4.0 to 5.5 V: Count clock 10 MHz VDD = 2.7 V to 4.0 V: Count clock 5 MHz Cautions 1. When TMHE0 = 1, setting bits other than those of the TMHMD0 register is prohibited. 2. In the PWM pulse generator mode and carrier generator mode, be sure to set 8-bit timer H compare register 01 (CMP01) when starting the timer count operation (TMHE0 = 1) after the timer count operation was stopped (TMHE0 = 0) (be sure to set again even if setting the same value to the CMP01 register). 3. When using the carrier generator mode, set the TMH0 count clock frequency to six times the TM50 count clock frequency or higher.
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(b) 8-bit timer H mode register 1 (TMHMD1)
After reset: 00H <7> TMHMD1 TMHE1
R/W 6
Address: FFFFF590H 5 4 3 2 1 <0> TOEN1
CKSH12 CKSH11 CKSH10 TMMD11 TMMD10 TOLEV1
TMHE1 0 1
8-bit timer H1 operation enable Stop timer count operation (8-bit timer counter H1 = 00H) Enable timer count operation (Counting starts when clock is input)
CKSH12 CKSH11 CKSH10
Selection of count clock Count clockNote fXX = 16.0 MHz 62.5 ns 125 ns 250 ns 1 s 4 s fXT (subclock) Setting prohibited
0 0 0 0 1 1
0 0 1 1 0 0 Other than above
0 1 0 1 0 1
fXX fXX/2 fXX/4 fXX/16 fXX/64
TMMD11 TMMD10 0 0 1 1 0 1 0 1
8-bit timer H1 operation mode Interval timer mode Carrier generator mode PWM pulse generator mode Setting prohibited
TOLEV1 0 1 Low level High level
Timer output level control (default)
TOEN1 0 1 Disable output Enable output
Timer output control
Note Set so as to satisfy the following conditions. VDD = 4.0 to 5.5 V: Count clock 10 MHz VDD = 2.7 V to 4.0 V: Count clock 5 MHz Cautions 1. When TMHE1 = 1, setting bits other than those of the TMHMD1 register is prohibited. 2. In the PWM pulse generator mode and carrier generator mode, be sure to set 8-bit timer H compare register 11 (CMP11) when starting timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to the CMP11 register). 3. When using the carrier generator mode, set the TMH1 count clock frequency to six times the TM51 count clock frequency or higher.
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(2) 8-bit timer H carrier control register n (TMCYCn) This register controls the 8-bit timer Hn remote control output and carrier pulse output status. TMCYCn register is set by an 8- bit or 1-bit memory manipulation instruction. The NRZn bit is a read-only bit. RESET input clears TMCYCn to 00H. Remark n = 0, 1
After reset: 00H 7 TMCYCn (n = 0, 1) RMCn 0 0 1 1 0
R/W 6 0
Address: FFFFF581H, FFFFF591H 5 0 4 0 3 0 2 RMCn 1 NRZBn 0 NRZn
NRZBn 0 1 0 1 Low level output
Remote control output
High level output Low level output Carrier pulse output
NRZn 0 1
Carrier pulse output status flag Carrier output disabled status (low level status) Carrier output enable status
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9.4 Operation
8-bit timers H0 and H1 can operate in the following three modes. * Interval timer mode * Carrier generator mode * PWM pulse generator mode Caution Rewriting the values of 8-bit timer H compare registers 00 and 10 (CMP00 and CMP10) while 8-bit timers H0 and H1 are operating is prohibited. 9.4.1 Operation as interval timer When the count value of 8-bit timer counter Hn and the value of 8-bit timer H compare register n0 (CMPn0) match, an interrupt request signal (INTTMHn) is generated and 8-bit timer counter Hn is cleared to 00H. 8-bit timer H compare register n1 (CMPn1) cannot be used in the interval timer mode. Even if the CMPn1 register is set, this has no effect on the timer output because matches between 8-bit timer counter Hn and the CMPn1 register are not detected. (1) Usage method The INTTMHn signal is repeatedly generated in the same interval. <1> Set each register. Figure 9-2. Register Settings in Interval Timer Mode
(i)
8-bit timer H mode register n (TMHMDn) settings
TMHEn TMHMDn 0 CKSHn2 CKSHn1 CKSHn0 TMMDn1 TMMDn0 TOLEVn 0/1 0/1 0/1 0 0 0/1 TOENn 0/1
Sets timer output Sets timer output level inversion Sets interval timer mode Selects count clock (fCNT) Stops count operation
(ii) CMPn0 register settings * Compare value (N)
<2> When TMHEn = 1 is set, counting starts.
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<3> When the count value of 8-bit timer counter Hn and the value of the CMPn0 register match, the INTTMHn signal is generated and 8-bit timer counter Hn is cleared to 00H. Interval time = (N + 1)/fCNT
<4> Then, the INTTMHn signal is generated in the same interval. To stop the count operation, set the TMHEn bit to 0. (2) Timing chart The timing in the interval timer mode is as follows. Figure 9-3. Timing of Interval Timer Operation (1/2)
Basic operation
Count clock Count start 8-bit timer counter Hn count value 00H 01H N 00H Clear CMPn0 N 01H N 00H Clear 01H 00H
TMHEn
INTTMHn Interval time TOHn <1> <2> Level inversion, match interrupt occurrence, 8-bit timer counter clear <3> <2> Level inversion, match interrupt occurrence, 8-bit timer counter clear
<1> When TMHEn = 1 is set, counting starts. <2> When the count value of 8-bit timer counter Hn and the value of the CMPn0 register match, the value of 8-bit timer counter Hn is cleared, the TOHn output level is inverted, and the INTTMHn signal is output. <3> The INTTMHn signal and TOHn output become inactive when the TMHEn bit is set to 0 during 8-bit timer Hn operation. If the level is already inactive, it remains unchanged. Remark n = 0, 1
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Figure 9-3. Timing of Interval Timer Operation (2/2)
Operation when CMPn0 = FFH
Count clock Count start 8-bit timer counter Hn count value 00H 01H FEH FFH 00H Clear CMPn0 FFH FEH FFH 00H Clear
TMHEn
INTTMHn
TOHn Interval time
Operation when CMPn0 = 00H
Count clock Count start 8-bit timer counter Hn count value 00H
CMPn0
00H
TMHEn
INTTMHn
TOHn Interval time
Remark n = 0, 1
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9.4.2 PWM pulse generator mode operation In the PWM mode, a pulse of any duty and cycle can be output. 8-bit timer H compare register n0 (CMPn0) controls the timer output (TOHn) cycle. Rewriting the CMPn0 register during timer operation is prohibited. 8-bit timer H compare register n1 (CMPn1) controls the timer output (TOHn) duty. The CMPn1 register can be rewritten during timer operation. The operation in the PWM mode is as follows. After timer counting starts, when the count value of 8-bit timer counter Hn and the value of the CMPn0 register match, the TOHn output becomes active and 8-bit timer counter Hn is cleared to 00H. When the count value of 8-bit timer counter Hn and the CMPn1 register match, TOHn output becomes inactive. (1) Usage method In the PWM mode, a pulse of any duty and cycle can be output. <1> Set each register. Figure 9-4. Register Settings in PWM Pulse Generator Mode
(i)
8-bit timer H mode register n (TMHMDn) settings
TMHEn CKSHn2 CKSHn1 CKSHn0 TMMDn1 TMMDn0 TOLEVn 0/1 0/1 0/1 1 0 0/1 TOENn 1
TMHMDn
0
Enables timer output Sets timer output level inversion Selects PWM mode Selects count clock (fCNT) Stops count operation
(ii) CMPn0 register setting * Compare value (N): Sets cycle (ii) CMPn1 register setting * Compare value (N): Sets duty Remarks 1. n = 0, 1 2. 00H CMPn1 (M) < CMPn0 (N) FFH
<2> When TMHEn = 1 is set, counting starts.
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<3> After the count operation is enabled, the first compare register to be compared is the CMPn0 register. When the count value of 8-bit timer counter Hn and the value of the CMPn0 register match, 8-bit timer counter Hn is cleared, an interrupt request signal (INTTMHn) is generated, and the TOHn output becomes active. At the same time, the register that is compared with 8-bit timer counter Hn changes from the CMPn0 register to the CMPn1 register. <4> When the count value of 8-bit timer counter Hn and the value of the CMPn1 register match, the TOHn output becomes inactive, and at the same time the register that is compared with 8-bit timer counter Hn changes from the CMPn1 register to the CMPn0 register. At this time, 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated. <5> A pulse of any duty ratio can be obtained through the repetition of steps <3> and <4> above. <6> To stop the count operation, set TMHEn = 0. Designating the setting value of the CMPn0 register as (N), the setting value of the CMPn1 register as (M), and the count clock frequency as fCNT, the PWM pulse output cycle and duty ratio are as follows. PWM pulse output cycle = (N + 1)/fCNT Duty ratio = inactive width: Active width = (M + 1) : (N - M)
Cautions 1. In the PWM mode, three operating clocks (signal selected by CKSHn0 to CKSHn2 bits of TMHMDn register) are required for actual transfer of the new value to the register after the CMPn1 register has been rewritten. 2. Be sure to set the CMPn1 register when starting the timer count operation (TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the same value to the CMPn1 register).
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(2) Timing chart The operation timing in the PWM mode is as follows. Caution The setting value (M) of the CMPn1 register and the setting value (N) of the CMPn0 register must always be set within the following range. 00H CMPn1 (M) < CMPn0 (N) FFH Figure 9-5. Operation Timing in PWM Pulse Generator Mode (1/4)
Basic operation
Count clock
8-bit timer counter Hn count value
00H 01H
A5H 00H 01H 02H
A5H 00H 01H 02H
A5H 00H
CMPn0
A5H
CMPn1
01H
TMHEn
INTTMHn
TOHn (TOLEVn = 0) <1> TOHn (TOLEVn = 1) <2> <3> <4>
<1> When TMHEn = 1 is set, counting starts. At this time TOHn output stays inactive (TOLEVn = 0). <2> When the count value of 8-bit timer counter Hn and the value of the CMPn0 register match, the TOHn output level is inverted, 8-bit timer counter Hn is cleared, and the INTTMHn signal is output. <3> When the count value of 8-bit timer counter Hn and the value of the CMPn1 register match, the TOHn output level is returned to its former level. At this time, the value of 8-bit timer counter Hn is not cleared and the INTTMHn signal is not output. <4> When the TMHEn bit is set to 0 during 8-bit timer Hn operation, the INTTMHn signal and TOHn output becomes inactive. Remark n = 0, 1
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Figure 9-5. Operation Timing in PWM Pulse Generator Mode (2/4)
Operation when CMPn0 = FFH, CMPn1 = 00H
Count clock
8-bit timer counter Hn count value
00H 01H
FFH 00H 01H 02H
FFH 00H 01H 02H
FFH 00H
CMPn0
FFH
CMPn1
00H
TMHEn
INTTMHn
TOHn (TOLEVn = 0)
Operation when CMPn0 = FFH, CMPn1 = FEH
Count clock
8-bit timer counter Hn count value
00H 01H
FEH FFH 00H 01H
FEH FFH 00H 01H
FEH FFH 00H
CMPn0
FFH
CMPn1
FEH
TMHEn
INTTMHn
TOHn (TOLEVn = 0)
Remark n = 0, 1
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Figure 9-5. Operation Timing in PWM Pulse Generator Mode (3/4)
Operation when CMPn0 = 01H, CMPn1 = 00H
Count clock
8-bit timer counter Hn count value
00H
01H 00H 01H 00H
00H 01H 00H 01H
CMPn0
01H
CMPn1
00H
TMHEn
INTTMHn
TOHn (TOLEVn = 0)
Remark n = 0, 1
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Figure 9-5. Operation Timing in PWM Pulse Generator Mode (4/4)
Operation based on CMPn1 transitions (CMPn1 = 01H 03H, CMPn0 = A5H)
Count clock
8-bit timer counter Hn count value
00H 01H 02H
A5H 00H 01H 02H 03H
A5H 00H 01H 02H 03H
A5H 00H
CMPn0
A5H
CMPn1
01H
01H (03H) <2>'
03H
<2> TMHEn
INTTMHn
TOHn (TOLEVn = 0) <1> <3> <4> <5> <6>
<1> When TMHEn = 1 is set, counting starts. At this time, the TOHn output remains inactive (TOLEVn = 0). <2> The setting value of the CMPn1 register can be changed during count operation. This operation is asynchronous to the count clock. <3> When the count value of 8-bit timer counter Hn and the value of the CMPn0 register match, 8-bit timer counter Hn is cleared, the TOHn output becomes active, and the INTTMHn signal is generated. <4> Even if the value of the CMPn1 register is changed, that value is latched and not transferred to the register. When the count value of 8-bit timer counter Hn and the value of the CMPn1 register prior to the change match, the changed value is transferred to the CMPn1 register and the value of the CMPn1 register is changed (<2>'). However, three or more count clocks are required from the time the value of the CMPn1 register is changed until it is transferred to the register. Even if a match signal is generated within three count clocks, the changed value cannot be transferred to the register. <5> When the count value of 8-bit timer counter Hn matches the changed value of the CMPn1 register, the TOHn output becomes inactive. 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated. <6> When the TMHEn bit is set to 0 during 8-bit timer Hn operation, the INTTMHn signal and TOHn output become inactive.
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9.4.3 Carrier generator mode operation The carrier clock generated by 8-bit timer Hn is output using the cycle set with 8-bit timer/event counter 5n. In the carrier generator mode, 8-bit timer/event counter 5n is used to control the extent to which the carrier pulse of 8-bit timer Hn is output, and the carrier pulse is output from the TOHn output. In the carrier generator mode, the connection diagram of 8-bit timer Hn and 8-bit timer/event counter 5n is as follows. Figure 9-6. Connection Example of 8-Bit Timer Hn and 8-Bit Timer/Event Counter 5n
INTTM5n
8-bit timer/event counter 5n
TO5n TMMDn0, TMMDn1 INTTM5n Selector INTC INTTM5Hn
8-bit timer Hn
INTTMHn TOHn
Prescaler
CPU
Remark n = 0, 1
(1) Carrier generation In the carrier generator mode, 8-bit timer H compare register n0 (CMPn0) generates a waveform with the lowlevel width of the carrier pulse and 8-bit timer H compare register n1 (CMPn1) generates a waveform with the high-level width of the carrier pulse. During 8-bit timer Hn operation, the CMPn1 register can be rewritten, but rewriting of the CMPn0 register is prohibited. (2) Carrier output control Carrier output control is performed with the interrupt request signal (INTTM5n) of 8-bit timer/event counter 5n and the NRZn and RMCn bits of 8-bit timer H carrier control register (TMCYCn). The output relationships are as follows.
RMCn Bit 0 0 1 1 NRZn Bit 0 1 0 1 Output Low level output High level output Low level output Carrier pulse output
Remark n = 0, 1
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To control carrier pulse output during count operation, the NRZn and NRZBn bits of the TMCYCn register have a master and slave bit configuration. The NRZn bit is read-only while the NRZBn bit can be read and written. The INTTM5n signal is synchronized with the 8-bit timer Hn clock and output as the INTTM5Hn signal. The INTTM5Hn signal becomes the data transfer signal of the NRZn bit and the value of the NRZBn bit is transferred to the NRZn bit. The transfer timing from the NRZBn bit to the NRZn bit is as follows. Figure 9-7. Transfer Timing
TMHEn
8-bit timer Hn count clock
INTTM5n
INTTM5Hn <1> NRZn 0 <2> NRZBn 1 0 1 1 0
RMCn
<1> The INTTM5n signal is synchronized with the count clock of 8-bit timer Hn and is output as the INTTM5Hn signal. <2> The value of the NRZBn bit is transferred to the NRZn bit at the second clock from the rising edge of the INTTM5Hn signal. Cautions 1. Do not rewrite the NRZBn bit again until at least the second clock after it has been rewritten, or else transfer from the NRZBn bit to the NRZn bit is not guaranteed. 2. When using 8-bit timer/event counter 5n in the carrier generator mode, an interrupt occurs at the timing of <1>. An interrupt occurs at a different timing when it is used in other than the carrier generator mode. Remark n = 0, 1
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(3) Usage method Any carrier clock can be output from the TOHn pin. <1> Set each register. Figure 9-8. Register Settings in Carrier Generator Mode
* 8-bit timer H mode register n (TMHMDn)
TMHEn TMHMDn 0 CKSHn2 CKSHn1 CKSHn0 TMMDn1 TMMDn0 TOLEVn 0/1 0/1 0/1 0 1 0/1 TOENn 0/1
Enables timer output Sets timer output level inversion Selects carrier generator mode Selects count clock (fCNT) Stops count operation
* CMPn0 register: * CMPn1 register: * TMCYCn register:
Compare value Compare value RMCn = 1 ... Remote control output enable bit NRZBn = 0/1 ... Carrier output enable bit
* TCL5n, TMC5n registers: Refer to 8.3 Control Registers. Remark n = 0, 1
<2> When TMHEn = 1 is set, 8-bit timer Hn count operation starts. <3> When the TCE5n bit of 8-bit timer mode control register 5n (TMC5n) is set to 1, 8-bit timer/event counter 5n count operation starts. <4> After the count operation is enabled, the first compare register to be compared is the CMPn0 register. When the count value of 8-bit timer counter Hn and the value of the CMPn0 register match, the INTTMHn signal is generated, 8-bit timer counter Hn is cleared, and at the same time, the register that is compared with 8-bit timer counter Hn changes from the CMPn0 register to the CMPn1 register. <5> When the count value of 8-bit timer counter Hn and the value of the CMPn1 register match, the INTTMHn signal is generated, 8-bit timer counter Hn is cleared, and at the same time, the register that is compared with 8-bit timer counter Hn changes from the CMPn1 register to the CMPn0 register. <6> The carrier clock is obtained through the repetition of steps <4> and <5> above. <7> The INTTM5n signal is synchronized with 8-bit timer Hn and output as the INTTM5Hn signal. This signal becomes the data transfer signal of the NRZBn bit and the value of the NRZBn bit is transferred to the NRZn bit. <8> When the NRZn bit becomes high level, the carrier clock is output from the TOHn pin. <9> Any carrier clock can be obtained through the repetition of the above steps. To stop the count operation, set TMHEn = 0.
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Designating the setting value of the CMPn0 register as (N), the setting value of the CMPn1 register as (M), and the count clock frequency as fCNT, the carrier clock output cycle and duty ratio are as follows. Carrier clock output cycle = (N + M + 2)/fCNT Duty ratio = High level width: Low level width = (M + 1) : (N + 1)
Caution Be sure to set the CMPn1 register when starting the timer count operation (TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the same value to the CMPn1 register). (4) Timing chart The carrier output control timing is as follows. Cautions 1. Set the values of the CMPn0 and CMPn1 registers in the range of 01H to FFH. 2. In the carrier generator mode, three operating clocks (signal selected by CKSHn0 to CKSHn2 bits of TMHMDn register) are required for actual transfer of the new value to the register after the CMPn1 register has been rewritten. 3. Be sure to perform the RMCn bit setting before the start of the count operation. 4. When using the carrier generator mode, set the TMHn count clock frequency to six times the TM5n count clock frequency or higher.
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Figure 9-9. Carrier Generator Mode (1/3) Operation when CMPn0 = N, CMPn1 = N is set
8-bit timer Hn count clock 8-bit timer counter Hn count value CMPn0 CMPn1 TMHEn INTTMHn <1> <2> Carrier clock 8-bit timer 5n count clock TM5n count value CR5n TCE5n <5> INTTM5n NRZBn NRZn Carrier clock TOHn <7> 0 0 1 1 0 <6> 0 1 0 1 0
00H 01H L 00H 01H L 00H 01H L L 00H 01H L 00H 01H 00H N 00H N 00H N 00H N N 00H N 00H N
N
<3>
<4>
<1> When TMHEn = 0 and TCE5n = 0, the operation of 8-bit timer Hn is stopped. <2> When TMHEn = 1 is set, 8-bit timer Hn starts counting. The carrier clock is maintained inactive at this time. <3> When the count value of 8-bit timer counter Hn and the value of the CMPn0 register match, the first INTTMHn signal is generated, the carrier clock signal is inverted, and the register that is compared with 8-bit timer counter Hn changes from the CMPn0 register to the CMPn1 register. 8-bit timer counter Hn is cleared to 00H. <4> When the count value of 8-bit timer counter Hn and the value of the CMPn1 register match, the INTTMHn signal is generated, the carrier clock signal is inverted, and the register that is compared with 8-bit timer counter Hn changes from the CMPn1 register to the CMPn0 register. 8-bit timer counter Hn is cleared to 00H. A carrier clock with a duty ratio of 50% is generated through the repetition of steps <3> and <4>. <5> When the INTTM5n signal is generated, this signal is synchronized with 8-bit timer Hn and output as the INTTM5Hn signal. <6> The INTTM5Hn signal becomes the data transfer signal of the NRZBn bit, and the value of the NRZBn bit is transferred to the NRZn bit. <7> The TOHn output is made low level by setting NRZn = 0. Remark n = 0, 1
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Figure 9-9. Carrier Generator Mode (2/3) Operation when CMPn0 = N, CMPn1 = M is set (operation with carrier clock phase asynchronous to NRZn phase)
8-bit timer Hn count clock 8-bit timer counter Hn count value CMPn0 CMPn1 TMHEn INTTMHn <1> <2> Carrier clock 8-bit timer 5n count clock TM5n count value CR5n TCE5n <5> INTTM5n NRZBn NRZn Carrier clock TOHn <7> 0 0 1 1 0 <6> 0 1 0 1 0
00H 01H L 00H 01H L 00H 01H L L 00H 01H L 00H 01H 00H N 00H 01H M 00H N N 00H 01H M 00H N 00H
M
<3>
<4>
<1> When TMHEn = 0 and TCE5n = 0, the operation of 8-bit timer Hn is stopped. <2> When TMHEn = 1 is set, 8-bit timer Hn starts counting. The carrier clock is maintained inactive at this time. <3> When the count value of 8-bit timer counter Hn and the value of the CMPn0 register match, the first INTTMHn signal is generated, the carrier clock signal is inverted, and the register that is compared with 8-bit timer counter Hn changes from the CMPn0 register to the CMPn1 register. 8-bit timer counter Hn is cleared to 00H. <4> When the count value of 8-bit timer counter Hn and the value of the CMPn1 register match, the INTTMHn signal is generated, the carrier clock signal is inverted, and the register that is compared with 8-bit timer counter Hn changes from the CMPn1 register to the CMPn0 register. 8-bit timer counter Hn is cleared to 00H. A carrier clock with a fixed duty ratio (other than 50%) is generated through the repetition of steps <3> and <4>. <5> The INTTM5n signal is generated. This signal is synchronized with 8-bit timer Hn and output as the INTTM5Hn signal. <6> When the carrier clock phase becomes asynchronous to the phase of the NRZn bit, the carrier is output from the rising edge of the first carrier clock by setting NRZn = 1. <7> By setting NRZn = 0, the TOHn output is also maintained high level while the carrier clock is high level, and does not change to low level (the high level width of the carrier waveform is guaranteed through steps <6> and <7>). Remark n = 0, 1
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Figure 9-9. Carrier Generator Mode (3/3) Operation based on CMPn1 transitions
8-bit timer Hn count clock
8-bit timer counter Hn count value
00H 01H
N
00H 01H
M
00H
N
00H 01H
L
00H
CMPn0 <3> CMPn1 M M (L)
N <3>' L
TMHEn
INTTMHn <2> Carrier clock <1> <4> <5>
<1> When TMHEn = 1 is set, counting starts. The carrier clock is maintained inactive at this time. <2> When the count value of 8-bit timer counter Hn and the value of the CMPn0 register match, 8-bit timer counter Hn is cleared and the INTTMHn signal is output. <3> The CMPn1 register can be rewritten during 8-bit timer Hn operation, but the changed value (L) is latched. The value of the CMPn1 register is changed when the count value of 8-bit timer counter Hn and the value of the CMPn1 register prior to the change (M) match (<3>'). <4> When the count value of 8-bit timer counter Hn and the value (M) of the CMPn1 register match, the INTTMHn signal is output, the carrier signal is inverted, and 8-bit timer counter Hn is cleared to 00H. <5> The timing at which the count value of 8-bit timer counter Hn and the value of the CMPn1 register match again is the changed value (L). Remark n = 0, 1
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CHAPTER 10 REAL-TIME OUTPUT FUNCTION (RTO)
10.1 Function
The real-time output function (RTO) transfers preset data to real-time output buffer registers n (RTBLn, RTBHn), and then transfers this data with hardware to an external device via the real-time output latches, upon occurrence of an external interrupt or external trigger. The pins through which the data is output to an external device constitute a port called a real-time output port. Because RTO can output signal without jitter, it is suitable for controlling a stepping motor. In the V850ES/KF1 and V850ES/KG1, one 6-bit real-time output port channel is provided. In the V850ES/KJ1, two 6-bit real-time output port channels are provided. The real-time output port can be set in the port mode or real-time output port mode in 1-bit units. The block diagram of RTO is shown below. Figure 10-1. Block Diagram of RTO
Internal bus
Real-time buffer register nH (RTBHn)
Real-time output latch nH
2 RTPOUTn4, RTPOUTn5
Real-time buffer register nL (RTBLn)
Real-time output latch nL
4 RTPOUTn0 to RTPOUTn3
INTTM000 (INTTM020Note)
Transfer trigger (H)
INTTM50 INTTM51
Selector Transfer trigger (L)
2 4
RTPOEn RTPEGn BYTEn
EXTRn
RTPMn5 RTPMn4 RTPMn3 RTPMn2 RTPMn1 RTPMn0
Real-time output port control register n (RTPCn)
Real-time output port mode register n (RTPMn)
Note When n = 0, INTTM000 When n = 1, INTTM020
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10.2 Configuration
RTO consists of the following hardware. Table 10-1. Configuration of RTO
Item Registers Control registers Configuration Real-time output buffer register n (RTBLn, RTBHn) Real-time output port mode register n (RTPMn) Real-time output port control register n (RTPCn)
(1) Real-time output buffer register n (RTBLn, RTBHn) RTBLn and RTBHn are 4-bit registers that hold output data in advance. These registers are mapped to independent addresses in the peripheral I/O register area. They can be read/written in 8-bit or 1-bit units. If an operation mode of 4 bits x 2 channels is specified (BYTEn = 0), data can be individually set to the RTBLn and RTBHn registers. The data of both these registers can be read at once by specifying the address of either of these registers. If an operation mode of 6 bits x 1 channel is specified (BYTEn = 1), 8-bit data can be set to both the RTBLn and RTBHn registers by writing the data to either of these registers. Moreover, the data of both these registers can be read at once by specifying the address of either of these registers. Table 10-2 shows the operation when the RTBLn and RTBHn registers are manipulated.
After reset : 00H
R/W
Address : RTBLn : FFFFF6E0H, FFFFF6F0 RTBHn : FFFFF6E2H, FFFFF6F2
RTBLn RTBHn 0 0 RTBHn5 RTBHn4
RTBLn3
RTBLn2
RTBLn1
RTBLn0
Caution When writing to bits 6 and 7 of the RTBHn register, always write 0. Remark n = 0, 1 n = 1 only for the V850ES/KJ1.
Table 10-2. Operation During Manipulation of Real-Time Output Buffer Registers n
Operation Mode Register to Be Manipulated RTBLn RTBHn RTBLn RTBHn Read Higher 4 bits RTBHn RTBHn RTBHn RTBHn Lower 4 bits RTBLn RTBLn RTBLn RTBLn WriteNote Higher 4 bits Invalid RTBHn RTBHn RTBHn Lower 4 bits RTBLn Invalid RTBLn RTBLn
4 bits x 1 channel, 2 bits x 1 channel 6 bits x 1 channel
Note After setting the real-time output port, set output data to the RTBLn and RTBHn registers by the time a realtime output trigger is generated.
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10.3 RTO Control Registers
RTO is controlled using the following two types of registers. * Real-time output port mode register n (RTPMn) * Real-time output port control register n (RTPCn) (1) Real-time output port mode register n (RTPMn) This register selects the real-time output port mode or port mode in 1-bit units. The RTPMn register is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears RTPMn to 00H.
After reset : 00H
R/W
Address : FFFFF6E4H, FFFF6F4H
RTPMn (n = 0, 1)
0
0
RTPMn5 RTPMn4 RTPMn3 RTPMn2 RTPMn1 RTPMn0
RTPMn 0 1 Port mode
Selection of real-time output port (n = 0 to 5)
Real-time output port mode
Cautions 1. To reflect real-time output signals (RTPOUTn0 to RTPOUTn5) to the pins (RTPn0 to RTPn5), set them to the real-time output port with the PMC and PFC registers. 2. By enabling real-time output operation (RTPOEn = 1), the bits specified for the real-time output port mode perform real-time output, and the bits specified for the port mode output 0. 3. If real-time output is disabled (RTPOEn = 0), real-time output signals (RTPOUTn0 to RTPOUTn5) all output 0, regardless of the RTPMn register setting. Remark n = 1 only for the V850ES/KJ1.
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(2) Real-time output port control register n (RTPCn) RTPCn are registers used to set the operation mode and output trigger of the real-time output port. The relationship between the operation mode and output trigger of the real-time output port is as shown in Tables 10-3 and 10-4. The RTPCn register is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears RTPCn to 00H.
After reset : 00H R/W Address : FFFFF6E5H, FFFFF6F5H
RTPCn (n = 0, 1)
RTPOEn RTPEGn
BYTEn
EXTRn
0
0
0
0
RTPOEn 0 1 Disables operation Enables operation
Control of real-time output operation
Note 1
RTPEGn 0 1
Valid edge of INTTM000 (n = 0), INTTM020 (n = 1) signal Falling edgeNote 2 Rising edge
BYTEn 0 1
Specification of channel configuration for real-time output 4 bits x 2 channels 8 bits x 1 channel
Notes 1. When real-time output operation is disabled (RTPOEn = 0), real-time output signals (RTPOUTn0 to RTPOUTn5) all output 0. 2. INTTM000 and INTTM020 are output for 1 clock of the count clock selected with the respective timers. Caution Perform the settings for the RTPEGn, BYTEn, and EXTRn bits only when RTPOEn = 0. Remark n = 1 only for the V850ES/KJ1
Table 10-3. Operation Modes and Output Triggers of Real-Time Output Port (n = 0)
BYTE0 0 EXTR0 0 1 1 0 1 Operation Mode 4 bits x 1 channel, 2 bits x 1 channel 6 bits x 1 channel RTBH0 (RTP04, RTP05) INTTM51 INTTM50 INTTM50 INTTM000 RTBL0 (RTP00 to RTP03) INTTM50 INTTM000
Table 10-4. Operation Modes and Output Triggers of Real-Time Output Port (n = 1, V850ES/KJ1 only)
BYTE1 0 EXTR1 0 1 1 0 1 Operation Mode 4 bits x 1 channel, 2 bits x 1 channel 6 bits x 1 channel RTBH1 (RTP14, RTP15) INTTM50 INTTM51 INTTM51 INTTM020
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RTBL1 (RTP10 to RTP13) INTTM51 INTTM020
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10.4 Operation
If the real-time output operation is enabled by setting bit 7 (RTPOEn) of real-time output port control register n (RTPCn) to 1, the data of real-time output buffer register n (RTBHn, RTBLn) is transferred to the real-time output latch in synchronization with the generation of the selected transfer trigger (set by EXTRn and BYTEn
Note
). Of the
transferred data, only the data of the bits specified in the real-time output port mode by real-time output port mode registers n (RTPMn) is output from bits RTPOUTn0 to RTPOUTn5. The bits specified in the port mode by the RTPMn register output 0. If the real-time output operation is disabled by clearing RTPOEn to 0, RTPOUTn0 to RTPOUTn5 output 0 regardless of the setting of the RTPMn register. Note EXTRn: Bit 4 of the real-time output port control register n (RTPCn) BYTEn: Bits 5 of the real-time output port control register n (RTPCn) Figure 10-2. Example of Operation Timing of RTO0 (When EXTR0 = 0, BYTE0 = 0)
INTTM51 (internal)
INTTM50 (internal)
CPU operation
A
B
A
B
A
B
A
B
RTBH0 D01
D02
D03
D04
RTBL0
D11
D12
D13
D14
RT output latch 0 (H)
D01
D02
D03
D04
RT output latch 0 (L)
D11
D12
D13
D14
A: Software processing by interrupt request input to INTTM51 (RTBH0 write) B: Software processing by interrupt request input to INTTM50 (RTBL0 write)
Remark For the operation during standby, refer to CHAPTER 21 STANDBY FUNCTION.
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10.5 Usage
(1) Disable real-time output. Clear bit 7 (RTPOEn) of real-time output port control register n (RTPCn) to 0. (2) Perform initialization as follows. * Specify the real-time output port mode or port mode in 1-bit units. Set real-time output port mode register n (RTPMn). * Channel configuration: Select the trigger and valid edge. Set bits 4 to 6 (EXTRn, BYTEn, and RTPEGn) of the RTPCn register. * Set the initial values to real-time output buffer register n (RTBHn, RTBLn) (3) Enable real-time output. Set RTPOEn = 1. (4) Set the next output value to the RTBHn and RTBLn registers by the time the selected transfer trigger is generated
Note 2 Note 1
.
.
(5) Set the next real-time output value to the RTBHn and RTBLn registers through interrupt servicing corresponding to the selected trigger. Notes 1. If write to the RTBHn and RTBLn registers is performed when RTPOEn = 0, that value is transferred to real-time output latches nH and nL, respectively. 2. Even if write is performed to the RTBHn and RTBLn registers when RTPOEn = 1, data transfer to realtime output latches nH and nL is not performed. Caution To reflect the real-time output signals (RTPOUTn0 to RTPOUTn5) to the pins, set the real-time output ports (RTPn0 to RTPn5) with the PMC and PFC registers.
10.6 Cautions
(1) Prevent the following conflicts by software. * Conflict between real-time output disable/enable switching (RTPOEn bit) and selected real-time output trigger * Conflict between write to the RTBHn and RTBLn registers in the real-time output enabled status and the selected real-time output trigger. (2) Before performing initialization, disable real-time output (RTPOEn = 0). (3) Once real-time output has been disabled (RTPOEn = 0), be sure to initialize the real-time output buffer registers (RTBHn and RTBLn) before enabling real-time output again (RTPOEn = 0 1).
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10.7 Security Function
A circuit that sets the pin outputs to high impedance as a security function for when malfunctions of a stepping motor controlled by RTO occur is provided on chip. It forcibly resets the pins allocated to RTP00 to RTP05 via external interrupt INTP0 edge detection, and the pins allocated to RTP10 to RTP15 via INTP1 edge detection in the high-impedance state. The ports (P50 to 55, P60 to 65
Note 1 Note 1
, placing them
Note 2
) placed in high impedance by INTP0 and INTP1
Note 1
are initialized
, so
settings for these ports must be performed again. Notes 1. Only for the V850ES/KJ1 2. Regardless of the port settings, P50 to 55 and P60 to 65 are all placed in high impedance via INTPn. 3. The bits that are initialized are all the bits corresponding to P50 to 55 and P60 to 65 of the following registers. * P5, P6L * PM5, PM6L * PMC5, PMC6L * PU5, PU6L * PFC5 * PF5 The block diagram of the security function is shown below. Figure 10-3. Block Diagram of Security Function
INTPn
Edge detection
INTC EVDD
R RTOSTn RTPOUTn0 to RTPOUTn5 RTPn0 to RTPn5
6
Remark
n = 0, 1 n = 1 only for the V850ES/KJ1.
This function is set with bits 3 and 2 (RTOST1, RTOST0) of the PLL control register (PLLCTL).
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(1) PLL control register (PLLCTL) PLLCTL is an 8-bit register that controls the PLL. This register can be read/written in 8-bit or 1-bit units. RESET input clears PLLCTL to 00H.
After reset : 01H
R/W
Address : FFFFF806H <> <> <>
Note 2
<> PLLONNote 2
PLLCTL
0
0
0
0
RTOST1
Note 1
RTOST0 SELPLL
RTOSTn 0 1
Control of RTPn0 to RTPn5 security function INTPn is not used as trigger for security function INTPn is used as trigger for security function
Notes 1. The RTOST1 bit is valid only for the V850ES/KJ1. In the V850ES/KG1 and V850ES/KF1, this bit is fixed to 0. Changing the value of this bit does not affect the operation. 2. For details on the SELPLL bit and the PLLON bit, refer to CHAPTER 6 CLOCK GENERATION FUNCTION. Cautions 1. Before outputting a value to the real-time output ports (RTPn0 to RTPn5), select INTPn interrupt edge detection and then set the RTOST0 and RTOS1 bits. 2. To set again the ports (P50 to P55, P60 to P65) as real-time output ports after placing them in high impedance via INTPn, first cancel the security function. [Procedure to set ports again] <1> Cancel the security function and enable port setting by setting RTOSTn = 0. <2> Set RTOSTn = 1 (only if required) <3> Set again as RTP pin. 3. Be sure to set bits 4 to 7 to 0. Remark n = 0 (V850ES/KF1, V850ES/KG1) n = 0, 1 (V850ES/KJ1)
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CHAPTER 11 WATCH TIMER FUNCTIONS
11.1 Functions
The watch timer has the following functions. * Watch timer * Interval timer The watch timer and interval timer functions can be used at the same time. Figure 11-1. Block Diagram of Watch Timer
Clear
Selector
Selector
5-bit counter
Selector
INTWT
fX
Prescaler fBRG 3Note fXT
fW
11-bit prescaler fW/24 fW/25 fW/26 fW/27 fW/28 fW/210 fW/211 fW/29
Clear
Selector
INTWTI
3
WTM7
WTM6
WTM5
WTM4
WTM3
WTM2
WTM1
WTM0
Watch timer operation mode register (WTM) Internal bus
Note For details about prescaler 3, refer to Figure 11-2 Block Diagram of Prescaler 3. Remark fBRG: fX: fXT: fW: INTWT: INWTI: Prescaler 3 clock frequency Oscillation frequency Subclock frequency Watch timer clock frequency Watch timer interrupt Interval timer interrupt
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Figure 11-2. Block Diagram of Prescaler 3
fX 3-bit prescaler
Selector
fX/8 fX/4 fX/2 fX
fBGCS Clear
8-bit counter Match
INTBRG
Output control
fBRG
2
Prescaler compare register (PRSCM)
BGCE
TODIS
BGCS1
BGCS0 Prescaler mode register (PRSM)
Remark fBRG: fX:
Prescaler 3 clock frequency Oscillation frequency
INTBRG: Prescaler 3 interval timer interrupt
(1) Watch timer The watch timer generates an interrupt request (INTWT) at time intervals of 0.5 or 0.25 seconds by using the main clock or subclock. (2) Interval timer The watch timer generates an interrupt request (INTWTI) at time intervals specified in advance. Table 11-1. Interval Time of Interval Timer
Interval Time 2 x 1/fW
4
Operating at fW = 32.768 kHz 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms 31.3 ms 62.5 ms
2 x 1/fW
5
2 x 1/fW
6
2 x 1/fW
7
2 x 1/fW
8
2 x 1/fW
9
210 x 1/fW 2 x 1/fW
11
Remark fW: Watch timer clock frequency
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11.2 Configuration
The watch timer consists of the following hardware. Table 11-2. Configuration of Watch Timer
Item Counter Prescaler Control register 5 bits x 1 11 bits x 1 Watch timer operation mode register (WTM) Configuration
11.3 Watch Timer Control Registers
Two registers control the watch timer, the watch timer operation mode register (WTM). Before operating the watch timer, set the count clock and the interval time. (1) Watch timer operation mode register (WTM) This register enables or disables the count clock and operation of the watch timer, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the set time of the watch flag. The WTM register is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears WTM to 00H.
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After reset: 00H
R/W
Address: FFFFF680H <> <> WTM0
WTM
WTM7
WTM6
WTM5
WTM4
WTM3
WTM2
WTM1
WTM7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
WTM6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
WTM5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
WTM4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Selection of interval time of prescaler 24/fW (488 s: fW = fXT) 25/fW (977 s: fW = fXT) 26/fW (1.95 ms: fW = fXT) 27/fW (3.91 ms: fW = fXT) 28/fW (7.81 ms: fW = fXT) 29/fW (15.6 ms: fW = fXT) 210/fW (31.3 ms: fW = fXT) 211/fW (62.5 ms: fW = fXT) 24/fW (488 s: fW = fBRG) 25/fW (977 s: fW = fBRG) 26/fW (1.95 ms: fW = fBRG) 27/fW (3.91 ms: fW = fBRG) 28/fW (7.81 ms: fW = fBRG) 29/fW (15.6 ms: fW = fBRG) 210/fW (31.3 ms: fW = fBRG) 211/fW (62.5 ms: fW = fBRG)
WTM7 0 0 0 0 1 1 1 1
WTM3 0 0 1 1 0 0 1 1
WTM2 0 1 0 1 0 1 0 1
Selection of set time of watch flag 214/fW (0.5 s: fW = fXT) 213/fW (0.25 s: fW = fXT) 25/fW (977 s: fW = fXT) 24/fW (488 s: fW = fXT) 214/fW (0.5 s: fW = fBRG) 213/fW (0.25 s: fW = fBRG) 25/fW (977 s: fW = fBRG) 24/fW (488 s: fW = fBRG)
WTM1 0 1
Control of 5-bit counter operation Clears after operation stops Starts
WTM0 0 1
Watch timer operation enable Stops operation (clears both prescaler and 5-bit counter) Enables operation
Caution Rewrite the WTM2 to WTM7 bits while both the WTM0 and WTM1 bits are 0. Remarks 1. fW: Watch timer clock frequency 2. Values in parentheses apply when fW = 32.768 kHz
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11.4 Operation
11.4.1 Operation as watch timer The watch timer generates an interrupt request at fixed time intervals. The watch timer operates using time intervals of 0.5 seconds with the subclock (32.768 kHz). The count operation starts when bit 0 (WTM0) and bit 1 (WTM1) of the watch timer operation mode register (WTM) are set to 1. When these bits are set to 0, the 11-bit prescaler and 5-bit counter are cleared and the count operation stops. The 5-bit counter of the watch timer can be cleared to synchronize the time by setting the WTM1 bit to 0. At this time, an error of up to 15.6 ms may occur. The interval timer may be cleared by setting the WTM0 bit to 0. However, because the 5-bit counter is cleared at the same time, an error of up to 0.5 seconds may occur when the watch timer overflows (INTWT). 11.4.2 Operation as interval timer The watch timer can also be used as an interval timer that repeatedly generates an interrupt at intervals specified by a count value set in advance. The interval time can be selected by bits 4 to 7 (WTM4 to WTM7) of the watch timer operation mode register (WTM). Table 11-3. Interval Time of Interval Timer
WTM7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 WTM6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 WTM5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WTM4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 x 1/fw
4
Interval Time 488 s (operating at fW = fXT = 32.768 kHz) 977 s (operating at fW = fXT = 32.768 kHz) 1.95 ms (operating at fW = fXT = 32.768 kHz) 3.91 ms (operating at fW = fXT = 32.768 kHz) 7.81 ms (operating at fW = fXT = 32.768 kHz) 15.6 ms (operating at fW = fXT = 32.768 kHz) 31.3 ms (operating at fW = fXT = 32.768 kHz) 62.5 ms (operating at fW = fXT = 32.768 kHz) 488 s (operating at fW = fBRG = 32.768 kHz) 977 s (operating at fW = fBRG = 32.768 kHz) 1.95 ms (operating at fW = fBRG = 32.768 kHz) 3.91 ms (operating at fW = fBRG = 32.768 kHz) 7.81 ms (operating at fW = fBRG = 32.768 kHz) 15.6 ms (operating at fW = fBRG = 32.768 kHz) 31.3 ms (operating at fW = fBRG = 32.768 kHz) 62.5 ms (operating at fW = fBRG = 32.768 kHz)
2 x 1/fw
5
2 x 1/fw
6
2 x 1/fw
7
2 x 1/fw
8
2 x 1/fw
9
210 x 1/fw 211 x 1/fw 2 x 1/fw
4
2 x 1/fw
5
2 x 1/fw
6
2 x 1/fw
7
2 x 1/fw
8
2 x 1/fw
9
210 x 1/fw 211 x 1/fw
Remark fW: Watch timer clock frequency
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Figure 11-3. Operation Timing of Watch Timer/Interval Timer
5-bit counter
0H Start Count clock fW or fW/29 Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTI Interval time (T) nT Interval time (T) nT Overflow Overflow
Remark fW: Watch timer clock frequency Values in parentheses apply when count clock fW = 32.768 kHz. n: Number of interval timer operations
11.4.3 Cautions Some time is required before the first watch timer interrupt request (INTWT) is generated after operation is enabled (WTM1 and WTM0 bits of WTM register = 1). Figure 11-4. Example of Generation of Watch Timer Interrupt Request (INTWT) (When Interrupt Period = 0.5 s)
It takes 0.515625 seconds for the first INTWT to be generated (2 x 1/32768 = 0.015625 s longer). INTWT is
9
then generated every 0.5 seconds.
WTNM0, WTNM1 0.515625 s 0.5 s 0.5 s
INTWT
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11.5 Prescaler 3
The prescaler 3 has the following functions. * Generation of watch timer count clock (source clock: main oscillation clock) * Interval timer (INTBRG) 11.5.1 Control registers (1) Prescaler mode register (PRSM) The PRSM register controls the generation of the count clock for the watch timer. PRSM can be read and written in 8-bit units.
After reset: 00H
R/W
Address: FFFFF8B0H <>
PRSM
0
0
0
BGCE
0
TODIS
BGCS1
BGCS0
BGCE 0 1 1 BGCS1
TODIS x 0 1 BGCS0
Prescaler output Fixed to 0 Operates Fixed to 0
Prescaler interrupt signal (INTBRG) Fixed to 0 Operates Operates
Selection of input clock (fBGCS)Note 10 MHz 4 MHz 250 ns 500 ns 1 s 2 s
0 0 1 1
0 1 0 1
fX fX/2 fX/4 fX/8
100 ns 200 ns 400 ns 800 ns
Note Set so as to satisfy the following conditions. VDD = 4.0 to 5.5 V: BGCS 10 MHz VDD = 2.7 to 4.0 V: BGCS 5 MHz Cautions 1. Do not change the values of the BGCS0 and BGCS1 bits during prescaler 3 operation. 2. Set the PRSM register before setting the BGCE bit to 1. 3. The 8-bit counter is cleared by clearing (0) the BGCE bit.
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(2) Prescaler compare register (PRSCM) This is an 8-bit compare register. PRSCM can be read and written in 8-bit units.
After reset: 00H
R/W
Address: FFFFF8B1H
PRSCM
PRSCM7 PRSCM6 PRSCM5 PRSCM4 PRSCM3 PRSCM2 PRSCM1 PRSCM0
Cautions 1. Do not rewrite the PRSCM register during prescaler operation. 2. Set the PRSCM register before setting the BGCE bit of the PRSM register to 1.
11.5.2 Generation of count clock (1) Watch timer count clock The clock (fBRG) input to the watch timer can be corrected to approximate 32.768 kHz. The relationships among the main oscillation clock (fX), input clock selection bit BGCSn setting value (m), PRSCM register setting value (N) and output clock (fBRG) are as follows. Example: When fX = 4.00 MHz, m = 0 (BGCS1 = BGCS = 0), and N = 3DH, fBRG = 32.787 kHz fBRG = fX 2 xNx2
m
Remark fBRG: Count clock N: m: (2) Interval timer A prescaler 3 interrupt request (INTBRG) is generated at a time interval set in advance. The interval time can be set with bits 0 and 1 (BGCS0, BGCS1) of the prescaler mode register (PRSM) and the prescaler compare register (PRSCM). The interval time is obtained with the following equation. Interval time = 2 xN
m
PRSCM register setting value (1 to FFH) In the case of PRSCM register setting value 00H, N = 256 BGCS1 and BGCS0 bit setting values (0 to 3)
fX
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12.1 Watchdog Timer 1
12.1.1 Functions Watchdog timer 1 has the following operation modes. * Watchdog timer 1 * Interval timer * Selecting the oscillation stabilization time The following functions are realized from the above-listed operation modes. * Generation of non-maskable interrupt request signal (INTWDT1) upon overflow of watchdog timer 1 * Generation of system reset signal (WDTRES1) upon overflow of watchdog timer 1 * Generation of maskable interrupt request signal (INTWDTM1) upon overflow of interval timer * Securing of oscillation stabilization time for main clock Note Restoring using the RETI instruction following a non-maskable interrupt servicing due to non-maskable interrupt request (INTWDT1) is not possible. Therefore, following completion of interrupt servicing, perform system reset. Remark Select whether to use watchdog timer 1 in the watchdog timer 1 mode or the interval timer mode with watchdog timer mode register 1 (WDTM1).
Note Note
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Figure 12-1. Block Diagram of Watchdog Timer 1
Watchdog timer mode register 1 (WDTM1) RUN1 WDTM14 WDTM13
Internal bus Watchdog timer clock selection register (WDCS) WDCS2 WDCS1
Oscillation stabilization time selection register (OSTS) WDCS0 OSTS2 OSTS1 OSTS0
2 Clear fXW Prescaler fXW/221 fXW/219 fXW/218
Selector
3
3
fXW/217 fXW/2
16
INTWDTM1 Output controller INTWDT1 WDTRES1
fXW/215 fXW/2
14
fXW/213
fXW/213 fXW/215 fXW/216
Selector
fXX/217 fXW/218 fXW/219 fXW/220 fXW/221
OSC
Remark INTWDTM1: Request signal for maskable interrupt through watchdog timer 1 overflow INTWDT1: fXW = fX: Request signal for non-maskable interrupt through watchdog timer 1 overflow Watchdog timer 1 clock frequency WDTRES1: Reset signal through watchdog timer 1 overflow
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12.1.2 Configuration Watchdog timer 1 consists of the following hardware. Table 12-1. Configuration of Watchdog Timer 1
Item Control register Configuration Oscillation stabilization time selection register (OSTS) Watchdog timer clock selection register (WDCS) Watchdog timer mode register 1 (WDTM1)
12.1.3 Watchdog timer 1 control register The registers that control watchdog timer 1 are as follows. * Oscillation stabilization time selection register (OSTS) * Watchdog timer clock selection register (WDCS) * Watchdog timer mode register 1 (WDTM1) (1) Oscillation stabilization time selection register (OSTS) This register selects the oscillation stabilization time following reset or cancellation of the stop mode. The OSTS register is set by an 8-bit or 1-bit memory manipulation instruction. RESET input sets OSTS to 01H.
After reset: 01H
R/W
Address: FFFFF6C0H
OSTS
0
0
0
0
0
OSTS2
OSTS1
OSTS0
OSTS2
OSTS1
OSTS0
Selection of oscillation stabilization time fX 4 MHz 5 MHz 1.638 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms 419.4 ms 10 MHz 0.819 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
2 /fX 2 /fX 216/fX 2 /fX 2 /fX 2 /fX 220/fX 2 /fX
21 19 18 17 15
13
2.048 ms 8.192 ms 16.38 ms 32.77 ms 65.54 ms 131.1 ms 262.1 ms 524.3 ms
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(2) Watchdog timer clock selection register (WDCS) This register sets the overflow time of watchdog timer 1 and the interval timer. The WDCS register is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears WDCS to 00H.
After reset: 00H
R/W
Address: FFFFF6C1H
WDCS
0
0
0
0
0
WDCS2
WDCS1
WDCS0
WDCS2
WDCS1
WDCS0
Overflow time of watchdog timer 1/interval timer fXW 4 MHz 5 MHz 1.638 ms 3.276 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 419.4 ms 10 MHz 0.819 ms 1.638 ms 3.277 ms 6.554 ms 13.11 ms 26.2 ms 52.43 ms 209.7 ms
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
2 /fXW 214/fXW 2 /fXW 2 /fXW 2 /fXW 218/fXW 2 /fXW 2 /fXW
21 19 17 16 15
13
2.048 ms 4.096 ms 8.192 ms 16.38 ms 32.77 ms 65.54 ms 131.1 ms 524.3 ms
Remark fXW = fX: Watchdog timer 1 clock frequency
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(3) Watchdog timer mode register 1 (WDTM1) This register sets the watchdog timer 1 operation mode and enables/disables count operations. This register is a special register that can be written only in a special sequence (refer to 3.4.7 Special registers). The WDTM1 register is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears WDTM1 to 00H.
After reset: 00H <> WDTM1 RUN1
R/W
Address: FFFFF6C2H
0
0
WDTM14 WDTM13
0
0
0
RUN1 0 1
Selection of operation mode of watchdog timer 1Note 1 Stops counting Clears counter and starts counting
WDTM14 WDTM13 Selection of operation mode of watchdog timer 1Note 2 0 0 1 0 1 0 Interval timer mode (Upon overflow, maskable interrupt INTWDTM1 is generated.) Watchdog timer mode 1Note 3 (Upon overflow, non-maskable interrupt INTWDT1 is generated.) 1 1 Watchdog timer mode 2 (Upon overflow, reset operation WDTRES1 is started.)
Notes 1. Once RUN1 bit is set (to 1), it cannot be cleared (to 0) by software. Therefore, when counting is started, it cannot be stopped except through RESET input. 2. Once the WDTM13 and WDTM14 bits are set (to 1), they cannot be cleared (to 0) by software and can be cleared only through RESET input. 3. Restoring using the RETI instruction following a non-maskable interrupt servicing due to nonmaskable interrupt request (INTWDT1) is not possible. Therefore, following completion of interrupt servicing, perform system reset.
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12.1.4 Operation (1) Oscillation stabilization time selection function The wait time until the oscillation stabilizes after the STOP mode is released is controlled by the oscillation stabilization time register (OSTS). The OSTS register is set by an 8-bit memory manipulation instruction. RESET input sets OSTS to 01H.
After reset: 01H
R/W
Address: FFFFF6C0H
OSTS
0
0
0
0
0
OSTS2
OSTS1
OSTS0
OSTS2
OSTS1
OSTS0
Selection of oscillation stabilization time fX 4 MHz 5 MHz 1.638 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms 419.4 ms 10 MHz 0.819 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
2 /fX 2 /fX 2 /fX 217/fX 2 /fX 2 /fX 2 /fX 221/fX
20 19 18 16 15
13
2.048 ms 8.192 ms 16.38 ms 32.77 ms 65.54 ms 131.1 ms 262.1 ms 524.3 ms
Cautions 1. The wait time following release of the STOP mode does not include the time until the clock oscillation starts (Figure a below) following release of the STOP mode, even if the STOP mode is released through RESET input or the occurrence of an interrupt request signal.
STOP mode release Voltage waveform of X1 pin a VSS
2. Be sure to set bits 3 to 7 to 0. 3. The oscillation stabilization time following reset release is 2 /fX (because the initial value of the OSTS register = 01H). 4. The oscillation stabilization time is also inserted during external clock input. Remark fX = Oscillation frequency
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(2) Operation as watchdog timer 1 Watchdog timer 1 operation to detect a program loop is selected by setting bit 4 (WDTM14) of watchdog timer mode register 1 (WDTM1) to 1. The count clock (program loop detection time interval) of watchdog timer 1 can be selected using bits WDCS0 to WDCS2 of the watchdog timer clock selection register (WDCS). The count operation is started by setting bit 7 (RUN1) of the WDTM1 register to 1. When, after the count operation is started, the RUN1 bit is again set to 1 within the set program loop detection time interval, watchdog timer 1 is cleared and the count operation starts again. If the program loop detection time is exceeded without RUN1 bit being set to 1, reset (WDTRES1) through the value of bit WDTM13 of the WDTM1 register or a non-maskable interrupt request signal (INTWDT1) is generated. The count operation of watchdog timer 1 stops in the STOP mode and IDLE mode. Therefore, set the RUN1 bit to 1 before the STOP mode or IDLE mode is entered in order to clear watchdog timer 1. Because watchdog timer 1 operates in the HALT mode, do not use watchdog timer 1 when using the HALT mode. Cautions 1. When the subclock is selected for the CPU clock, the count operation of watchdog timer 1 is stopped (the value of watchdog timer 1 is maintained). 2. Restoring using the RETI instruction following a non-maskable interrupt servicing due to INTWDT1 is not possible. Therefore, following completion of interrupt servicing, perform system reset. Table 12-2. Program Loop Detection Time of Watchdog Timer 1
Clock Program Loop Detection Time fXW = 4 MHz 2 /fXW 215/fXW 2 /fXW 2 /fXW 2 /fXW 2 /fXW 2 /fXW 2 /fXW
21 20 19 18 17 16 13
fXW = 5 MHz 1.638 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms 419.4 ms
fXW = 10 MHz 0.819 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms
2.048 ms 8.192 ms 16.38 ms 32.77 ms 65.54 ms 131.1 ms 262.1 ms 524.3 ms
Remark fXW = fX: Watchdog timer 1 clock frequency
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(3) Operation as interval timer Watchdog timer 1 can be made to operate as an interval timer that repeatedly generates interrupts using the count value set in advance as the interval, by setting bit 4 (WDTM14) of watchdog timer mode register 1 (WDTM1) to 0. When watchdog timer 1 operates as an interval timer, the interrupt mask flag (WDTMK) and priority specification flags (WDTPR0 to WDTPR2) of the WDTIC register are valid and maskable interrupt request signals (INTWDTM1) can be generated. The default priority of the INTWDTM1 signal is set to the highest level among the maskable interrupt request signals. The interval timer continues to operate in the HALT mode, but it stops operating in the STOP mode and the IDLE mode. Therefore, set the RUN1 bit of the WDTM1 register to 1 before the STOP mode or IDLE mode is entered in order to clear the interval timer. Cautions 1. Once the WDTM14 bit is set to 1 (thereby selecting the watchdog timer 1 mode), the interval timer mode is not entered as long as RESET is not input. 2. When the subclock is selected for the CPU clock, the count operation of the watchdog timer 1 stops (the value of the watchdog timer is maintained). Table 12-3. Interval Time of Interval Timer
Clock fXW = 4 MHz 2 /fXW 2 /fXW 2 /fXW 2 /fXW 2 /fXW 218/fXW 2 /fXW 2 /fXW
21 19 17 16 15 14 13
Interval Time fXW = 5 MHz 1.638 ms 3.276 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 419.4 ms fXW = 10 MHz 0.819 ms 1.638 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 209.7 ms
2.048 ms 4.096 ms 8.192 ms 16.38 ms 32.77 ms 65.54 ms 131.1 ms 524.3 ms
Remark fXW = fX: Watchdog timer 1 clock frequency
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12.2 Watchdog Timer 2
12.2.1 Functions Watchdog timer 2 has the following functions. * Default start watchdog timer
Note 1
Reset mode: Reset operation upon overflow of watchdog timer 2 (generation of WDTRES2) Non-maskable interrupt request mode: NMI operation upon overflow of watchdog timer 2 (generation of INTWDT2)
Note 2
* Input selectable from main clock and subclock as the source clock Notes 1. Watchdog timer 2 automatically starts in the reset mode following reset release. When watchdog timer 2 is not used, either stop its operation before reset is executed through this function, or clear once watchdog timer 2 and stop it within the next interval time. Also, write to the WDTM2 register for verification purposes only once, even if the default settings (reset mode, interval time: fXX/2 ) need not be changed. 2. Restoring using the RETI instruction following a non-maskable interrupt servicing due to a nonmaskable interrupt request (INTWDT2) is not possible. Therefore, following completion of interrupt servicing, perform system reset. Figure 12-2. Block Diagram of Watchdog Timer 2
25
fXX/29 fXT
Clock input controller 2
fXX/218 to fXX/225 16-bit Selector counter or fXT/29 to fXT/216 Clear 3
Output controller
INTWDT2 WDTRES2 (internal reset signal)
3
Watchdog timer enable register (WDTE)
0
WDM21 WDM20 WDCS24 WDCS23 WDCS22 WDCS21 WDCS20
Watchdog timer mode register 2 (WDTM2) Internal bus
Remark fXX: fXT: INTWDT2:
Internal system clock frequency Subclock frequency Non-maskable interrupt request signal through watchdog timer 2
WDTRES2: Watchdog timer 2 reset signal
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12.2.2 Configuration Watchdog timer 2 consists of the following hardware. Table 12-4. Configuration of Watchdog Timer 2
Item Control register Configuration Watchdog timer mode register 2 (WDTM2) Watchdog timer enable register (WDTE)
12.2.3 Watchdog timer 2 control register (1) Watchdog timer mode register 2 (WDTM2) This register sets the overflow time and operation clock of watchdog timer 2. WDTM2 is set with an 8-bit memory manipulation instruction. This register can be read any number of times, but it can be written only once following reset release. RESET input sets WDTM2 to 67H.
After reset: 67H
R/W
Address: FFFFF6D0H
WDTM2
0
WDM21
WDM20 WDCS24 WDCS23 WDCS22 WDCS21 WDCS20
WDM21 0 0 1
WDM20 0 1 -
Selection of operation mode of watchdog timer 2 Stops operation Non-maskable interrupt request mode (generation of INTWDT2) Reset mode (generation of WDTRES2)
Cautions 1. To stop the operation of watchdog timer 2, write "1FH" to the WDTM2 register. 2. For details about bits WDCS0 to WDCS4, refer to Table 12-5 Watchdog Timer 2 Clock Selection. 3. If the WDTM2 register is written twice after a reset, an overflow signal is forcibly output.
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Table 12-5. Watchdog Timer 2 Clock Selection
WDCS24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 WDCS23 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x WDCS22 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x WDCS21 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 x WDCS20 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 x Selected Clock 2 /fXX 2 /fXX 220/fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXT 2 /fXT 211/fXT 2 /fXT 2 /fXT 2 /fXT 2 /fXT 2 /fXT
16 15 14 13 12 10 9 25 24 23 22 21 19 18
fXX = 20 MHz 13.1 ms 26.2 ms 52.4 ms 104.9 ms 209.7 ms 419.4 ms 838.9 ms 1677.7 ms
fXX = 16 MHz 16.4 ms 32.8 ms 65.5 ms 131.1 ms 262.1 ms 524.3 ms 1048.6 ms 2097.2 ms
fXX = 10 MHz 26.2 ms 52.4 ms 104.9 ms 209.7 ms 419.4 ms 838.9 ms 1677.7 ms 3355.4 ms
15.625 ms (fXT = 32.768 kHz) 31.25 ms (fXT = 32.768 kHz) 62.5 ms (fXT = 32.768 kHz) 125 ms (fXT = 32.768 kHz) 250 ms (fXT = 32.768 kHz) 500 ms (fXT = 32.768 kHz) 1000 ms (fXT = 32.768 kHz) 2000 ms (fXT = 32.768 kHz)
Operation stopped
(2) Watchdog timer enable register (WDTE) The counter of watchdog timer 2 is cleared and counting restarted by writing "ACH" to WDTE. WDTE is set by an 8-bit memory manipulation instruction. RESET input sets WDTE to 9AH.
After reset: 9AH
R/W
Address: FFFFF6D1H
WDTE
Cautions 1. When a value other than "ACH" is written to the WDTE register, an overflow signal is forcibly output. 2. When a 1-bit memory manipulation instruction is executed for the WDTE register, an overflow signal is forcibly output (an error results in the assembler). 3. The read value of the WDTE register is "9AH" (value that differs from written value "ACH").
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12.2.4 Operation Watchdog timer 2 automatically starts in the reset mode following reset release. The WDTM2 register can be written to only once following reset through byte access. To use watchdog timer 2, write the operation mode and the interval time to the WDTM2 register using 8-bit memory manipulation instructions. After this is done, the operation of watchdog timer 2 cannot be stopped. The watchdog timer 2 program loop detection time interval can be selected by the WDCS24 to WDCS20 bits of the WDTM2 register. Writing ACH to the WDTE register clears the counter of watchdog timer 2 and starts the count operation again. After the count operation starts, write ACH to the WDTE register within the set program loop detection time interval. If the program loop detection time is exceeded without ACH being written to the WDTE register, a reset signal (WDTRES2) or non-maskable interrupt request signal (INTWDT2) is generated depending on the set value of the WDM21 and WDM20 bits of the WDTM2 register. To not use watchdog timer 2, write 1FH to the WDTM2 register. If the non-maskable interrupt request mode has been set, restoring using the RETI instruction following a nonmaskable interrupt servicing is not possible. Therefore, following completion of interrupt servicing, perform system reset.
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13.1 Function
The A/D converter converts analog input signals into digital values with a resolution of 10 bits. In the V850ES/KF1 and V850ES/KG1, it has an 8-channel (ANI0 to ANI7) configuration, and in the V850ES/KJ1, it has a 16-channel (ANI0 to ANI15) configuration. The A/D converter supports a power fail monitoring function (conversion result comparison function). Conversion is started by selecting one analog input channel and setting the A/D converter mode register (ADM). The A/D conversion operation is repeated and each time A/D conversion has been completed, INTAD is generated. The block diagram is shown below. Figure 13-1. Block Diagram of A/D Converter
ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8Note ANI9Note ANI10Note ANI11Note ANI12Note ANI13Note ANI14Note ANI15Note
Sample & hold circuit
Tap selector
AVREF0
Voltage comparator
Selector
AVSS
Successive approximation register (SAR)
AVSS
Controller Controller A/D conversion result registers (ADCR/ADCRH)
INTAD
4
Power fail comparison threshold register (PFT)
ADS3
ADS2
ADS1
ADS0
ADS3
ADS2
ADS1
ADS0
ADS1
PFEN PFCM
Analog input channel specification register (ADS)
A/D converter mode register (ADM) Internal bus
Power fail comparison mode register (PFM)
Note V850ES/KJ1 only
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13.2 Configuration
The A/D converter consists of the following hardware. Table 13-1. Configuration of A/D Converter
Item Analog input Configuration V850ES/KF1, V850ES/KG1: 8 channels (ANI0 to ANI7) V850ES/KJ1: 16 channels (ANI0 to ANI15) Successive approximation register (SAR) A/D conversion result register (ADCR) A/D conversion result register H (ADCRH): Only higher 8 bits can be read Power fail comparison threshold register (PFT) A/D converter mode register (ADM) Analog input channel specification register (ADS) Power fail comparison mode register (PFM)
Registers
Control registers
(1) Successive approximation register (SAR) This register compares the voltage value of the analog input signal with the voltage tap (compare voltage) value from the series resistor string, and holds the comparison result starting from the most significant bit (MSB). When the comparison result has been saved down to the least significant bit (LSB) (A/D conversion completion), the contents of the SAR are transferred to the A/D conversion result register. (2) A/D conversion result register (ADCR), A/D conversion result register H (ADCRH) Each time A/D conversion has been completed, the result of the conversion is loaded to this register from the successive approximation register, and the higher 10 bits of this register hold the result of the A/D conversion (the lower 6 bits are fixed to 0). The ADCR register is read by a 16-bit memory manipulation instruction. RESET input sets ADCR to 0000H. When using only the higher 8 bits of the A/D conversion result, the ADCRH register is read by an 8-bit memory manipulation instruction. RESET input clears ADCRH to 00H. (3) Power fail comparison threshold register (PFT) This register sets the threshold when comparing with the A/D conversion result register. The 8-bit data set in the PFT register and the higher 8 bits (ADCRH) of the A/D conversion result register are compared. The PFT register is read and written by an 8-bit memory manipulation instruction. RESET input clears PFT to 00H. (4) Sample & hold circuit The sample & hold circuit samples the analog input signals selected by the input circuit and sends the sampled data to the voltage comparator. This circuit holds the sampled analog input voltage during A/D conversion. (5) Voltage comparator The voltage comparator compares the value that is sampled and held with the output voltage of the series resistor string.
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(6) Series resistor string The series resistor string is connected between AVREF0 and AVSS and generates a voltage for comparison with the analog input signal. (7) ANI0 to ANI15 pins
Note Note
These are analog input pins for the 16 channels
of the A/D converter that are used to input analog signals to
be converted into digital signals. Pins other than those selected as analog input with the analog input channel specification register (ADS) can be used as input ports. Note The V850ES/KF1 and V850ES/KG1 provide only 8 channels, ANI0 to ANI7. Caution Make sure that the voltage input to ANI0 to ANI15 does not exceed the rated values. If a voltage higher than AVREF0 or lower than AVSS (even within the absolute maximum ratings) is input to a channel, the conversion value of the channel is undefined and the conversion values of the other channels may also be affected. (8) AVREF0 pin This is the analog power supply pin/reference voltage input pin of the A/D converter. Always use the same potential as the VDD pin even when not using the A/D converter. The signals input to the ANI0 to ANI15 pins are converted into digital signals based on the voltage applied across AVREF0 and AVSS.
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13.3 Control Registers
The A/D converter is controlled by the following registers. * A/D converter mode register (ADM) * Analog input channel specification register (ADS) * Power fail comparison mode register (PFM) (1) A/D converter mode register (ADM) This register sets the conversion time of the analog input signal to be converted into a digital signal as well as conversion start and stop. The ADM register is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears ADM to 00H.
After reset: 00H <> ADM ADCS
R/W
Address: FFFFF200H <>
0
FR2
FR1
FR0
0
0
ADCS2
ADCS 0 1 Stops conversion Enables conversion
A/D conversion control
FR2
FR1 FR0 Conversion timeNote
Conversion time selection fXX 20 MHz 16 MHz 10 MHz Setting prohibited Setting prohibited 14.4 s Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
288/fXX 240/fXX 192/fXX
Setting prohibited Setting prohibited Setting prohibited Setting prohibited 144/fXX 120/fXX 96/fXX 14.4 s 18.0 s 28.8 s 24.0 s
Setting prohibited 15.0 s
Setting prohibited Setting prohibited 19.2 s
Setting prohibited Setting prohibited Setting prohibited Setting prohibited
ADCS2 0 1 Comparator off Comparator on
Comparator control
Note Setting the conversion time (time actually required for A/D conversion) as follows is prohibited. AVREF0 4.0 V: Less than 14 s AVREF0 < 4.0 V: Less than 17 s Cautions 1. Always set bits 1, 2, and 6 to 0. 2. Changing bits FR0 to FR2 while ADCS = 1 is prohibited (write access to the ADM register is enabled and rewriting of bits FR0 to FR2 is prohibited).
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Table 13-2. Operation Mode Control
ADCS 0 0 1 1 ADCS2 0 1 0 1 Stopped status DC power consumption path does not exist. Conversion standby mode Only the comparator consumes power. Conversion modeNote Conversion modeNote
Note When A/D conversion is started as follows, the first conversion result is invalid. <1> (ADCS, ADCS2) = (0, 0) (1, 0) <2> (ADCS, ADCS2) = (0, 0) (1, 1) In the case of <1>, when ADCS bit is set (to 1) and A/D conversion starts, the comparator is automatically switched on regardless of whether the ADCS2 bit is set. The comparator is automatically switched off when the ADCS bit is cleared (to 0) following conversion. Similarly, in the case of <2>, the comparator is automatically switched on when the ADCS bit is set (to 1) and A/D conversion starts. However, the comparator remain switched on even if the ADCS bit is cleared. Caution The operation of the comparator is controlled with the ADCS2 bit, and 14 s are required from the start of operation until the operation stabilizes. Therefore, when ADCS = 1 (A/D conversion operation start) is set after 14 s have elapsed from the time ADCS2 = 1 (comparator on) is set, the conversion results are valid from the first result. Figure 13-2. Operation Sequence
Reference voltage generator for boosting: Operating
ADCS2
Comparator control Conversion operation
ADCS
Conversion wait
Conversion operation
Conversion stop
Note
Note 14 s or more are required as the time from the rising edge of the ADCS2 bit to the rising edge of the ADCS bit to allow the comparator operation to stabilize.
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(2) Analog input channel specification register (ADS) This register specifies the analog voltage input ports for A/D conversion. The ADS register is set by an 8-bit or 1-bit memory manipulation. RESET input clears ADS to 00H.
After reset: 00H
R/W
Address: FFFFF201H
ADS
0
0
0
0
ADS3
ADS2
ADS1
ADS0
ADS3Note 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
ADS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
ADS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
ADS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Specification of analog input channel ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8Note 2 ANI9Note 2 ANI10Note 2 ANI11Note 2 ANI12Note 2 ANI13Note 2 ANI14Note 2 ANI15Note 2
Notes 1. Because V850ES/KF1 and V850ES/KG1 have 8 channels (ANI0 to ANI7), be sure to set the ADS3 bit to 0. 2. The ANI8 to ANI15 channels are available only in the V850ES/KJ1. In the V850ES/KF1 and V850ES/KG1, setting these channels is prohibited.
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(3) Power fail comparison mode register (PFM) This register sets the power fail monitoring mode. It compares the value of the power fail comparison threshold register (PFT) and the value of the A/D conversion result register (ADCRH). The PFM register is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears PFM to 00H.
After reset: 00H <> PFM PFEN
R/W
Address: FFFFF202H
PFCM
0
0
0
0
0
0
PFEN 0 1
Selection of power fail comparison enable/disable Disables power fail comparison Enables power fail comparison
PFCM 0 1
Selection of power fail comparison mode Generates interrupt request signal (INTAD) when ADCR PFT Generates interrupt request signal (INTAD) when ADCR < PFT
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13.4 Relationship Between Analog Input Voltage and A/D Conversion Result
The relationship between the analog voltage input to an analog input pin (ANI0 to ANI15) and the value of the A/D conversion result register (ADCR) is as follows: VIN ADCR = INT ( AVREF0 Or, (ADCR - 0.5) x AVREF0 1,024 VIN < (ADCR + 0.5) x AVREF0 1,024 x1,024 + 0.5)
INT ( ): Function that returns integer of value in ( ) VIN: Analog input voltage AVREF0: AVREF0 pin voltage ADCR: Value of A/D conversion result register (ADCR) Figure 13-3 illustrates the relationship between the analog input voltages and A/D conversion results. Figure 13-3. Relationship Between Analog Input Voltages and A/D Conversion Results
1,023
1,022
A/D conversion result 1,021 (ADCR)
3
2
1
0
1 1 3 2 5 3 2,048 1,024 2,048 1,024 2,048 1,024
2,043 1,022 2,045 1,023 2,047 1 2,048 1,024 2,048 1,024 2,048
Input voltage/AVREF0
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13.5 Operation
13.5.1 Basic operation <1> Select one channel whose analog signal is to be converted into a digital signal using the analog input channel specification register (ADS). <2> The sample & hold circuit samples the voltage input to the selected analog input channel. <3> After sampling for a specific time, the sample & hold circuit enters the hold status and holds the input analog voltage until it has been converted into a digital signal. <4> Set bit 9 of the successive approximation register (SAR). The tap selector sets the voltage tap of the series resistor string to (1/2)AVREF0. <5> The voltage comparator compares the voltage difference between the voltage tap of the series resistor string and the analog input voltage. If the analog input voltage is greater than (1/2)AVREF0, the MSB of the SAR remains set. If the analog input voltage is less than the (1/2)AVREF0, the MSB is reset. <6> Next, bit 8 of SAR is automatically set and the next comparison starts. Depending on the value of bit 9 to which the result of the preceding comparison has been set, the voltage tap of the series resistor string is selected as follows. * Bit 9 = 1: (3/4)AVREF0 * Bit 9 = 0: (1/4)AVREF0 The analog input voltage is compared with one of these voltage taps and bit 8 of SAR is manipulated as follows depending on the result of the comparison. Analog input voltage voltage tap: bit 8 = 1 Analog input voltage voltage tap: bit 8 = 0 <7> The above steps are repeated until bit 0 of SAR has been manipulated. <8> When comparison of all 10 bits of SAR has been completed, the valid digital value remains in SAR, and the value of SAR is transferred and latched to the A/D conversion result register (ADCR). At the same time, an A/D conversion end interrupt request (INTAD) can be generated. Caution The first conversion value immediately following the start of A/D conversion may not satisfy the ratings.
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13.5.2 Conversion operation (software trigger mode) * Setting ADCS of the A/D converter mode register (ADM) to 1 starts conversion of the signal input to the channel specified with the analog input channel specification register (ADS). Upon completion of the conversion, the conversion result is stored to the ADCR register and a new conversion starts. * If ADM, ADS, the power fail comparison threshold value register (PFT), or the power fail comparison mode register (PFM) is written to during conversion, conversion is interrupted and the conversion operation starts again from the beginning. * If ADCS is set to 0 during conversion, conversion is interrupted and the conversion operation is stopped. * For whether or not the conversion end interrupt request signal (INTAD) is generated, refer to 13.5.3 Power fail monitoring function. 13.5.3 Power fail monitoring function The conversion end interrupt request signal (INTAD) can be controlled as follows using the PFM and PFT registers. * If PFEN = 0, INTAD is generated each time conversion ends. * If PFEN = 1 and PFCM = 0, the conversion result and the value of the PFT register are compared when conversion ends, and INTAD is output only if ADCRH PFT. * If PFEN and PFCM = 1, the conversion result and the value of the PFT register are compared when conversion ends and INTAD is output only if ADCRH < PFT. * Because, when PFEN = 1, the conversion result is overwritten after INTAD has been output, unless the conversion result is read by the time the next conversion ends, in some cases it may appear as if the actual operation differs from the operation described above (refer to Figure 13-4). Figure 13-4. Power Fail Monitoring Function (PFCM = 0)
Conversion operation
ANI0
ANI0
ANI0
ANI0
ADCRH
80H
7FH
80H
PFT
80H
INTAD
Note
Note If reading is not performed during this interval, the conversion result changes to the next conversion result.
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13.6 Cautions
(1) Power consumption in standby mode The operation of the A/D converter stops in the STOP and IDLE modes (operation of the A/D converter is possible in the HALT mode). At this time, the power consumption can be reduced by stopping the conversion operation (bit 7 (ADCS) and bit 0 (ADCS2) of the A/D converter mode register (ADM) = 0). (2) Changing bits FR0 to FR2 stops while ADCS = 1 is prohibited. (Write access to the ADM register is enabled and overwriting bits FR0 to FR2 is prohibited.) (3) A/D converter sampling time and A/D conversion start delay time The A/D converter sampling time differs depending on the set value of the A/D converter mode register (ADM). The delay time exists until actual sampling is started after A/D converter operation is enabled. When using a set in which the A/D conversion time must be strictly observed, care is required for the contents shown in Figure 13-5 and Table 13-3. Figure 13-5. Timing of A/D Converter Sampling and A/D Conversion Start Delay
ADCS 1 or ADS rewrite
ADCS
Sampling timing
INTAD
Wait period
A/D Sampling conversion time start delay time
Conversion time
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Table 13-3. A/D Converter Sampling Time and A/D Conversion Start Delay Time (ADM Set Value)
FR2 FR1 FR0 Conversion Time Sampling Time A/D Conversion Start Delay TimeNote MIN. 0 0 0 1 1 1 0 0 1 0 0 1 Other than above 0 1 0 0 1 0 288/fXX 240/fXX 192/fXX 144/fXX 120/fXX 96/fXX Setting prohibited 40/fXX 32/fXX 24/fXX 20/fXX 16/fXX 12/fXX - 32/fXX 28/fXX 24/fXX 16/fXX 14/fXX 12/fXX - 36/fXX 32/fXX 28/fXX 18/fXX 16/fXX 14/fXX - MAX.
Note The A/D conversion start delay time is the time after wait period. For the wait function, refer to 3.4.8 (2) Access to special on-chip peripheral I/O register. Remark fXX: Internal system clock frequency
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13.7 How to Read A/D Converter Characteristics Table
Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is expressed by %FSR (Full Scale Range). %FSR indicates the ratio of analog input voltage that can be converted as a percentage, and is always represented by the following formula regardless of the resolution. 1%FSR = (Max. value of analog input voltage that can be converted - Min. value of analog input voltage that can be converted)/100 = (AVREF0 - 0)/100 = AVREF0/100 1LSB is as follows when the resolution is 10 bits. 1LSB = 1/2 = 1/1024 = 0.098%FSR Accuracy has no relation to resolution, but is determined by overall error. (2) Overall error This shows the maximum error value between the actual measured value and the theoretical value. Zero-scale error, full-scale error, linearity error and errors that are combinations of these express the overall error. Note that the quantization error is not included in the overall error in the characteristics table. Figure 13-6. Overall Error
10
1......1
Ideal line
Digital output
Overall error
0......0 0 Analog input AVREF0
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(3) Quantization error When analog values are converted to digital values, a 1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of 1/2LSB is converted to the same digital code, so a quantization error cannot be avoided. Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. Figure 13-7. Quantization Error
1......1
Digital output
1/2LSB
Quantization error 1/2LSB
0......0 0 Analog input AVREF0
(4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2 LSB) when the digital output changes from 0......000 to 0......001. Figure 13-8. Zero-Scale Error
111
Digital output (Lower 3 bits)
Ideal line 100 Zero-scale error 011
010 001 000 -1 0 1 2 3 AVREF0 Analog input (LSB)
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(5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 1......110 to 1......111. Figure 13-9. Full-Scale Error
Full-scale error
Digital output (Lower 3 bits)
111 100 011 010
000 0 AVREF0-3 AVREF0-2 AVREF0-1 AVREF0 Analog input (LSB)
(6) Differential linearity error While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value and the ideal value. Figure 13-10. Differential Linearity Error
1......1 Ideal 1LSB width
Digital output
Differential linearity error 0......0 0 Analog input AVREF0
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(7) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. Figure 13-11. Integral Linearity Error
1......1 Ideal line
Digital output
0......0 0
Integral linearity error AVREF0 Analog input
(8) Conversion time This expresses the time from when the analog input voltage was applied to the time when the digital output was obtained. The sampling time is included in the conversion time in the characteristics table. (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. Figure 13-12. Sampling Time
Sampling time
Conversion time
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14.1 Functions
V850ES/KG1 and V850ES/KJ1 incorporate two D/A converter channels (DAC0, DAC1). The D/A converter has the following functions. 8-bit resolution x 2 channels R-2R ladder string method Conversion time: 20 s (MAX.) (AVREF1 = 2.7 to 5.5 V) Analog output voltage: AVREF1 x m/256 (m = 0 to 255; value set to DACSn register) Operation modes: Normal mode, real-time output mode Caution The V850ES/KF1 does not have a D/A converter. Remark n = 0, 1 The D/A converter configuration is shown below. Figure 14-1. Block Diagram of D/A Converter
DACS0 write DAMD0
DACS0
INTTMH0 DACE0 AVREF1 AVSS Selector
ANO0
Selector DACE1 DACS1 write DAMD1 ANO1
INTTMH1
DACS1
Notes 1. DAC0 and DAC1 share the AVREF1 pin. 2. DAC0 and DAC1 share the AVSS pin. The AVSS pin is also shared by the A/D converter.
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14.2 Configuration
The D/A converter consists of the following hardware. Table 14-1. Configuration of D/A Converter
Item Control register Configuration D/A converter mode register (DAM) D/A conversion value setting registers 0 and 1 (DACS0, DACS1)
14.3 D/A Converter Control Register
The registers that control the D/A converter are as follows. * D/A converter mode register (DAM) * D/A conversion value setting registers 0 and 1 (DACS0, DACS1) (1) D/A converter mode register (DAM) This register controls the operation of the D/A converter. The DAM is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears DAM to 00H.
After reset: 00H
R/W
Address: FFFFF284H <> <> DAMD0 DACE0
DAM
0
0
0
0
DAMD1
DACE1
DAMDn 0 1
Selection of D/A converter operation mode (n = 0, 1) Normal mode Real-time output modeNote
DACEn 0 1
D/A converter operation enable/disable control (n = 0, 1) Disables operation Enables operation
Note The output trigger in the real-time output mode (DAMDn bit = 1) is as follows. * When n = 0: INTTMH0 signal * When n = 1: INTTMH1 signal
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(2) D/A conversion value setting registers 0 and 1 (DACS0, DACS1) These registers set the analog voltage value output to the ANO0 and ANO1 pins. These register are set by an 8-bit memory manipulation instruction. RESET input clears DACS0 and DACS1 to 00H.
After reset: 00H
R/W
Address: FFFFF280H
DACS0
DA07
DA06
DA05
DA04
DA03
DA02
DA01
DA00
After reset: 00H
R/W
Address: FFFFF282H
DACS1
DA17
DA16
DA15
DA14
DA13
DA12
DA11
DA10
Caution In the real-time output mode (DAMDn bit = 1), set the DACS0 and DACS1 registers before the INTTMH0/INTTMH1 signals are generated. D/A conversion starts when the INTTMH0/INTTMH1 signals are generated.
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14.4 Operation
14.4.1 Operation in normal mode D/A conversion is performed using a write operation to the D/A conversion value setting register (DACSn) as the trigger. The setting method is described below. <1> Set the DAMDn bit of the D/A converter mode register (DAM) to 0 (normal mode). <2> Set the analog voltage value to be output to the ANOn pin to the DACSn register. Steps <1> and <2> above constitute the initial settings. <3> Set the DACEn bit of the DAM register to 1 (D/A conversion enable). D/A conversion starts when this setting is performed. <4> To perform subsequent D/A conversions, write to the DACSn register. The previous D/A conversion result is held until the next D/A conversion is performed. 14.4.2 Operation in real-time output mode D/A conversion is performed using the interrupt request signals (INTTMH0, INTTMH1) of 8-bit timers H0 and H1 (TMH0, TMH1) as the trigger. The setting method is described below. <1> Set the DAMDn bit of the DAM register to 1 (real-time output mode). <2> Set the analog voltage value to be output to the ANOn pin to the DACSn register. <3> Set the DACEn bit of the DAM register to 1 (D/A conversion enable). Steps <1> to <3> above constitute the initial settings. <4> Operate 8-bit timers H0 and H1 (TMH0, TMH1). <5> D/A conversion starts when the INTTMH0 and INTTMH1 signals are generated. <6> The INTTMH0 and INTTMH1 signals are generated when subsequent D/A conversions are performed. Before performing the next D/A conversion (generation of INTTMH0, INTTMH1 signals), set the analog voltage value to be output to the ANOn pin to the DACSn register.
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14.4.3 Cautions Observe the following cautions when using the D/A converter of the V850ES/KG1 and V850ES/KJ1. * When using the D/A converter, set the port pins to the input mode (PM1n bit = 1; n = 0, 1) * When using the D/A converter, reading of the port is prohibited. * When using the D/A converter, use both P10 and P11 as D/A outputs. Using one of the port 1 for D/A output and the other as a port is prohibited. * In the real-time output mode, do not change the setting value of the DACSn register while the trigger signal is output. * Make sure that AVREF1 VDD and AVREF1 = 2.7 V to 5.5 V. The operation is not guaranteed if ranges other than the above are used.
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CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART)
The number of asynchronous serial interface (UART) channels incorporated differs as follows depending on the product.
Product Name Number of channels V850ES/KF1 V850ES/KG1 V850ES/KJ1 3 channels (UART0 to UART2)
2 channels (UART0, UART1)
15.1 Selecting UART2 or I C1 Mode
UART2 and I C1 of the V850ES/KJ1 share pins, and therefore these interfaces cannot be used at the same time. Select UART2 or I C1 in advance by using the port 8 mode control register (PMC8) and port 8 function control register (PFC8) (refer to 4.3.8 Port 8). Caution UART2 or I C1 transmission/reception operations are not guaranteed if the mode is changed during transmission or reception. Be sure to disable the operation of the unit that is not used. Figure 15-1. Selecting Mode of UART2 or I C1
2 2 2 2
2
After reset: 00H 7 PMC8 0
R/W 6 0
Address: FFFFF450H 5 0 4 0 3 0 2 0 1 PMC81 0 PMC80
After reset: 00H 7 PFC8 0
R/W 6 0
Address: FFFFF470H 5 0 4 0 3 0 2 0 1 PFC81 0 PFC80
PFC8n 0 0 1 1
PMC8n 0 1 0 1
Operation mode Port I/O mode UART2 mode Port I/O mode I2C1 mode
Remark
n = 0, 1
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15.2 Features
* Full-duplex communications On-chip reception buffer register n (RXBn) On-chip transmission buffer register n (TXBn) * Two-pin configuration
Note
TXDn: Transmit data output pin RXDn: Receive data input pin * Reception error detection functions * Parity error * Framing error * Overrun error * Interrupt sources: 3 types * Reception error interrupt (INTSREn): * Reception completion interrupt (INTSRn): Interrupt is generated according to the logical OR of the three types of reception errors Interrupt is generated when receive data is transferred from the shift register to reception buffer register n after serial transfer is completed during a reception enabled state * Transmission completion interrupt (INTSTn): Interrupt is generated when the serial transmission of transmit data (8 or 7 bits) from the shift register is completed * The character length of transmit/receive data is specified by to the ASIMn register * Character length: 7 or 8 bits * Parity functions: Odd, even, 0, or none * Transmission stop bits: 1 or 2 bits * On-chip dedicated baud rate generator Note The ASCK0 pin is available only for UART0.
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15.3 Configuration
UARTn is controlled by asynchronous serial interface mode register n (ASIMn), asynchronous serial interface status register n (ASISn), and asynchronous serial interface transmission status register n (ASIFn). Receive data is maintained in reception buffer register n (RXBn), and transmit data is written to transmission buffer register n (TXBn). Figure 15-2 shows the configuration of asynchronous serial interface n (UARTn). (1) Asynchronous serial interface mode register n (ASIMn) The ASIMn register is an 8-bit register for specifying the operation of the asynchronous serial interface. (2) Asynchronous serial interface status register n (ASISn) The ASISn register consists of a set of flags that indicate the error contents when a reception error occurs. The various reception error flags are set (1) when a reception error occurs and are reset (0) when the ASISn register is read. (3) Asynchronous serial interface transmission status register n (ASIFn) The ASIFn register is an 8-bit register that indicates the status when a transmit operation is performed. This register consists of a transmission buffer data flag, which indicates the hold status of TXBn data, and the transmission shift register data flag, which indicates whether transmission is in progress. (4) Reception control parity check The receive operation is controlled according to the contents set in the ASIMn register. A check for parity errors is also performed during a receive operation, and if an error is detected, a value corresponding to the error contents is set in the ASISn register. (5) Reception shift register This is a shift register that converts the serial data that was input to the RXDn pin to parallel data. One byte of data is received, and if a stop bit is detected, the receive data is transferred to the reception buffer register n (RXBn). This register cannot be directly manipulated. (6) Reception buffer register n (RXBn) RXBn is an 8-bit buffer register for holding receive data. When 7 characters are received, 0 is stored in the MSB. During a reception enabled state, receive data is transferred from the reception shift register to the RXBn, synchronized with the end of the shift-in processing of one frame. Also, the reception completion interrupt request (INTSRn) is generated by the transfer of data to the RXBn. (7) Transmission shift register This is a shift register that converts the parallel data that was transferred from the transmission buffer register n (TXBn) to serial data. When one byte of data is transferred from the TXBn, the shift register data is output from the TXDn pin. This register cannot be directly manipulated.
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(8) Transmission buffer register n (TXBn) TXBn is an 8-bit buffer for transmit data. A transmit operation is started by writing transmit data to TXBn. The transmission completion interrupt request (INTSTn) is generated synchronized with the completion of transmission of one frame. (9) Addition of transmission control parity A transmit operation is controlled by adding a start bit, parity bit, or stop bit to the data that is written to the TXBn register, according to the contents that were set in the ASIMn register. Figure 15-2. Block Diagram of Asynchronous Serial Interface n
Internal bus
Asynchronous serial interface mode register n (ASIMn)
Reception buffer register n (RXBn)
Transmission buffer register n (TXBn)
RXDn TXDn
Reception shift register
Transmission shift register
Reception control parity check Parity Framing Overrun
Addition of transmission control parity
INTSTn INTSRn
INTSREn BRGn
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15.4 Control Registers
(1) Asynchronous serial interface mode register n (ASIMn) The ASIMn register is an 8-bit register that controls the UARTn transfer operation. This register can be read/written in 8-bit or 1-bit units. Caution When using UARTn, be sure to set the external pins related to UARTn functions to the control made before setting clock select register n (CKSRn) and the baud rate generator control register n (BRGCn), and then set the UARTEn bit to 1. Then set the other bits. (1/3)
After reset: 01H <7> ASIMn UARTEn R/W <6> TXEn Address: FFFFFA00H, FFFFFA10H, FFFFFA20H <5> RXEn 4 PSn1 3 PSn0 2 CLn 1 SLn 0 ISRMn
UARTEn 0 1 Stops clock supply to UARTn. Supplies clock to UARTn.
Controls the operating clock
* If UARTEn = 0, UARTn is asynchronously reset. * If UARTEn = 0, UARTn is reset. To operate UARTn, first set UARTEn to 1. * If the UARTEn bit is changed from 1 to 0, all the registers of UARTn are initialized. To set UARTEn to 1 again, be sure to re-set the registers of UARTn.
The output of the TXDn pin goes high when transmission is disabled, regardless of the setting of the UARTEn bit.
TXEn 0 1 Disables transmission Enables transmission
Enables/disables transmission
* Set the TXEn bit to 1 after setting the UARTEn bit to 1 at startup. Set the UARTEn bit to 0 after setting the TXEn bit to 0 to stop. * To initialize the transmission unit, clear (0) the TXEn bit, and after letting 2 Clock cycles (base clock) elapse, set (1) the TXEn bit again. If the TXEn bit is not set again, initialization may not be successful. (For details about the base clock, refer to 15.7.1 (1) Base clock (Clock).)
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(2/3)
RXEn 0 1 Disables reception Enables reception
Note
Enables/disables reception
* Set the RXEn bit to 1 after setting the UARTEn bit to 1 at startup. Set the UARTEn bit to 0 after setting the RXEn bit to 0 to stop. * To initialize the reception unit status, clear (0) the RXEn bit, and after letting 2 Clock cycles (base clock) elapse, set (1) the RXEn bit again. If the RXEn bit is not set again, initialization may not be successful. (For details about the base clock, refer to 15.7.1 (1) Base clock (Clock).)
PSn1 0 0 1 1
PSn0 0 1 0 1
Transmit operation Don't output parity bit Output 0 parity Output odd parity Output even parity
Receive operation Receive with no parity Receive as 0 parity Judge as odd parity Judge as even parity
* To overwrite the PSn1 and PSn0 bits, first clear (0) the TXEn and RXEn bits. * If "0 parity" is selected for reception, no parity judgment is performed. Therefore, no error interrupt is generated because the PEn bit of the ASISn register is not set. * Even parity If the transmit data contains an odd number of bits with the value "1", the parity bit is set (1). If it contains an even number of bits with the value "1", the parity bit is cleared (0). This controls the number of bits with the value "1" contained in the transmit data and the parity bit so that it is an even number. During reception, the number of bits with the value "1" contained in the receive data and the parity bit is counted, and if the number is odd, a parity error is generated. * Odd parity In contrast to even parity, odd parity controls the number of bits with the value "1" contained in the transmit data and the parity bit so that it is an odd number. During reception, the number of bits with the value "1" contained in the receive data and the parity bit is counted, and if the number is even, a parity error is generated. * 0 parity During transmission, the parity bit is cleared (0) regardless of the transmit data. During reception, no parity error is generated because no parity bit is checked. * No parity No parity bit is added to transmit data. During reception, the receive data is considered to have no parity bit. No parity error is generated because there is no parity bit.
Note When reception is disabled, the reception shift register does not detect a start bit. No shift-in processing or transfer processing to reception buffer register n (RXBn) is performed, and the contents of the RXBn register are retained. When reception is enabled, the reception shift operation starts, synchronized with the detection of the start bit, and when the reception of one frame is completed, the contents of the reception shift register are transferred to the RXBn register. A reception completion interrupt (INTSRn) is also generated in synchronization with the transfer to the RXBn register.
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(3/3)
CLn 0 1 7 bits 8 bits Specifies character length of 1 frame of transmit/receive data
* To overwrite the CLn bit, first clear (0) the TXEn and RXEn bits.
SLn 0 1 1 bit 2 bits
Specifies stop bit length of transmit data
* To overwrite the SLn bit, first clear (0) the TXEn bit. * Since reception is always done with a stop bit length of 1, the SLn bit setting does not affect receive operations.
ISRMn 0 1
Enables/disables generation of reception completion interrupt requests when an error occurs Generate a reception error interrupt request (INTSREn) as an interrupt when an error occurs. In this case, no reception completion interrupt request (INTSRn) is generated. Generate a reception completion interrupt request (INTSRn) as an interrupt when an error occurs. In this case, no reception error interrupt request (INTSREn) is generated.
* To overwrite the ISRMn bit, first clear (0) the RXEn bit.
Remark
n = 0, 1 (V850ES/KF1, V850ES/KG1) n = 0 to 2 (V850ES/KJ1)
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(2) Asynchronous serial interface status register n (ASISn) The ASISn register, which consists of 3 error flag bits (PEn, FEn and OVEn), indicates the error status when UARTn reception is complete. The status flag, which indicates a reception error, always indicates the status of the error that occurred most recently. That is, if the same error occurred several times before the receive data was read, this flag would hold only the status of the error that occurred last. The ASISn register is cleared to 00H by a read operation. When a reception error occurs, reception buffer register n (RXBn) should be read and the error flag should be cleared after the ASISn register is read. This register is read-only in 8-bit units. Cautions 1. When the UARTEn bit or RXEn bit of the ASIMn register is set to 0, or when the ASISn register is read, the PEn, FEn, and OVEn bits of the ASISn register are cleared (0). 2. Operation using a bit manipulation instruction is prohibited.
After reset: 00H 7 ASISn 0
R 6 0
Address: FFFFFA03H, FFFFFA13H, FFFFFA23H 5 0 4 0 3 0 2 PEn 1 FEn 0 OVEn
PEn 0 1
Status flag indicating a parity error When the ASIMn register's UARTEn or RXEn bit is set to 0, or after the ASISn register has been read When reception was completed, the receive data parity did not match the parity bit
* The operation of the PEn bit differs according to the settings of the PSn1 and PSn0 bits of the ASIMn register.
FEn 0 1
Status flag indicating framing error When the ASIMn register's UARTEn or RXEn bit is set to 0, or after the ASISn register has been read When reception was completed, no stop bit was detected
* For receive data stop bits, only the first bit is checked regardless of the stop bit length.
OVEn 0 1
Status flag indicating an overrun error When the ASIMn register's UARTEn or RXEn bit is set to 0, or after the ASISn register has been read. UARTn completed the next receive operation before reading the RXBn receive data.
* When an overrun error occurs, the next receive data value is not written to the RXBn register and the data is discarded.
Remark
n = 0, 1 (V850ES/KF1, V850ES/KG1) n = 0 to 2 (V850ES/KJ1)
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(3) Asynchronous serial interface transmission status register n (ASIFn) The ASIFn register, which consists of 2 status flag bits, indicates the status during transmission. By writing the next data to the TXBn register after data is transferred from the TXBn register to the transmission shift register, transmit operations can be performed continuously without suspension even during an interrupt interval. When transmission is performed continuously, data should be written after referencing the TXBFn bit of the ASIFn register to prevent writing to the TXBn register by mistake. This register is read-only in 8-bit units.
After reset: 00H 7 ASIFn 0
R 6 0
Address: FFFFFA05H, FFFFFA15H, FFFFFA25H 5 0 4 0 3 0 2 0 <1> TXBFn <0> TXSFn
TXBFn 0
Transmission buffer data flag Data to be transferred next to TXBn register does not exist (When the ASIMn register's UARTEn or TXEn bits is 0, or when data has been transferred to the transmission shift register) Data to be transferred next exists in TXBn register (Data exists in TXBn register when the TXBn register has been written to)
1
* When transmission is performed continuously, data should be written to the TXBn register after confirming that this flag is 0. If writing to TXBn register is performed when this flag is 1, transmit data cannot be guaranteed.
TXSFn 0
Transmission shift register data flag (indicates the transmission status of UARTn) Initial status or a waiting transmission (When the ASIMn register's UARTEn or TXEn bits is set to 0, or when following transfer completion, the next data transfer from the TXBn register is not performed) Transmission in progress (When data has been transferred from the TXBn register)
1
* When the transmission unit is initialized, initialization should be executed after confirming that this flag is 0 following the occurrence of a transmission completion interrupt. If initialization is performed when this flag is 1, transmit data cannot be guaranteed.
Remark
n = 0, 1 (V850ES/KF1, V850ES/KG1) n = 0 to 2 (V850ES/KJ1)
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(4) Reception buffer register n (RXBn) The RXBn register is an 8-bit buffer register for storing parallel data that had been converted by the reception shift register. When reception is enabled (RXEn bit = 1 in the ASIMn register), receive data is transferred from the reception shift register to the RXBn register, synchronized with the completion of the shift-in processing of one frame. Also, a reception completion interrupt request (INTSRn) is generated by the transfer to the RXBn register. For information about the timing for generating this interrupt request, refer to 15.6.4 Receive operation. If reception is disabled (RXEn bit = 0 in the ASIMn register), the contents of the RXBn register are retained, and no processing is performed for transferring data to the RXBn register even when the shift-in processing of one frame is completed. Also, no reception completion interrupt is generated. When 7 bits is specified for the data length, bits 6 to 0 of the RXBn register are transferred for the receive data and the MSB (bit 7) is always 0. However, if an overrun error (OVEn bit = 1 in the ASISn register) occurs, the receive data at that time is not transferred to the RXBn register. Except when a reset is input, the RXBn register becomes FFH even when UARTEn bit = 0 in the ASIMn register. This register is read-only in 8-bit units.
After reset: FFH 7 RXBn RXBn7
R 6 RXBn6
Address: FFFFFA02H, FFFFFA12H, FFFFFA22H 5 RXBn5 4 RXBn4 3 RXBn3 2 RXBn2 1 RXBn1 0 RXBn0
Remark
n = 0, 1 (V850ES/KF1, V850ES/KG1) n = 0 to 2 (V850ES/KJ1)
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(5) Transmission buffer register n (TXBn) The TXBn register is an 8-bit buffer register for setting transmit data. When transmission is enabled (TXEn bit = 1 in the ASIMn register), the transmit operation is started by writing data to TXBn register. When transmission is disabled (TXEn bit = 0 in the ASIMn register), even if data is written to TXBn register, the value is ignored. The TXBn register data is transferred to the transmission shift register, and a transmission completion interrupt request (INTSTn) is generated, synchronized with the completion of the transmission of one frame from the transmission shift register. For information about the timing for generating this interrupt request, refer to 15.6.2 Transmit operation. When TXBFn bit = 1 in the ASIFn register, writing must not be performed to TXBn register. This register can be read or written in 8-bit units.
After reset: FFH 7 TXBn TXBn7
R/W 6 TXBn6
Address: FFFFFA04H, FFFFFA14H, FFFFFA24H 5 TXBn5 4 TXBn4 3 TXBn3 2 TXBn2 1 TXBn1 0 TXBn0
Remark
n = 0, 1 (V850ES/KF1, V850ES/KG1) n = 0 to 2 (V850ES/KJ1)
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15.5 Interrupt Requests
The following three types of interrupt requests are generated from UARTn. * Reception error interrupt (INTSREn) * Reception completion interrupt (INTSRn) * Transmission completion interrupt (INTSTn) The default priorities among these three types of interrupt requests is, from high to low, reception error interrupt, reception completion interrupt, and transmission completion interrupt. Table 15-1. Generated Interrupts and Default Priorities
Interrupt Reception error Reception completion Transmission completion Priority 1 2 3
(1) Reception error interrupt (INTSREn) When reception is enabled, a reception error interrupt is generated according to the logical OR of the three types of reception errors explained for the ASISn register. Whether a reception error interrupt (INTSREn) or a reception completion interrupt (INTSRn) is generated when an error occurs can be specified according to the ISRMn bit of the ASIMn register. When reception is disabled, no reception error interrupt is generated. (2) Reception completion interrupt (INTSRn) When reception is enabled, a reception completion interrupt is generated when data is shifted in to the reception shift register and transferred to reception buffer register n (RXBn). A reception completion interrupt request can be generated in place of a reception error interrupt according to the ISRMn bit of the ASIMn register even when a reception error has occurred. When reception is disabled, no reception completion interrupt is generated. (3) Transmission completion interrupt (INTSTn) A transmission completion interrupt is generated when one frame of transmit data containing 7-bit or 8-bit characters is shifted out from the transmission shift register.
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15.6 Operation
15.6.1 Data format Full-duplex serial data transmission and reception can be performed. The transmit/receive data format consists of one data frame containing a start bit, character bits, a parity bit, and stop bits as shown in Figure 15-3. The character bit length within one data frame, the type of parity, and the stop bit length are specified according to asynchronous serial interface mode register n (ASIMn). Also, data is transferred with LSB first. Figure 15-3. Format of Asynchronous Serial Interface Transmit/Receive Data
1 data frame
Start bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity bit
Stop bits
Character bits
* Start bit *** 1 bit * Character bits *** 7 bits or 8 bits * Parity bit *** Even parity, odd parity, 0 parity, or no parity * Stop bits *** 1 bit or 2 bits
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15.6.2 Transmit operation When the UARTEn bit is set to 1 in the ASIMn register, a high level is output from the TXDn pin. Then, when the TXEn bit is set to 1 in the ASIMn register, transmission is enabled, and the transmit operation is started by writing transmit data to transmission buffer register n (TXBn). (1) Transmission enabled state This state is set by the TXEn bit in the ASIMn register. * TXEn = 1: Transmission enabled state * TXEn = 0: Transmission disabled state Since UARTn does not have a CTS (transmission enabled signal) input pin, a port should be used to confirm whether the destination is in a reception enabled state. (2) Starting a transmit operation In the transmission enabled state, a transmit operation is started by writing transmit data to transmission buffer register n (TXBn). When a transmit operation is started, the data in TXBn is transferred to transmission shift register. automatically. (3) Transmission interrupt request When the transmission shift register becomes empty, a transmission completion interrupt request (INTSTn) is generated. The timing for generating the INTSTn interrupt differs according to the specification of the stop bit length. The INTSTn interrupt is generated at the same time that the last stop bit is output. If the data to be transmitted next has not been written to the TXBn register, the transmit operation is suspended. Caution Normally, when the transmission shift register becomes empty, a transmission completion interrupt (INTSTn) is generated. However, no transmission completion interrupt (INTSTn) is generated if the transmission shift register becomes empty due to the input of RESET. Then, the transmission shift register outputs data to the TXDn pin (the transmit data is The start bit, parity bit, and stop bits are added transferred sequentially starting with the start bit).
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Figure 15-4. Asynchronous Serial Interface Transmission Completion Interrupt Timing
(a) Stop bit length: 1
TXDn (output)
Start
D0
D1
D2
D6
D7
Parity
Stop
INTSTn (output)
(b) Stop bit length: 2
TXDn (output)
Start
D0
D1
D2
D6
D7
Parity
Stop
INTSTn (output)
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15.6.3 Continuous transmission operation UARTn can write the next transmit data to the TXBn register at the timing that the transmission shift register starts the shift operation. This enables an efficient transmission rate to be realized by continuously transmitting data even during the INTSTn interrupt service after the transmission of one data frame. In addition, reading the TXSFn bit of the ASIFn register after the occurrence of a transmission completion interrupt enables the TXBn register to be efficiently written twice (2 bytes) without waiting for the transmission of 1 data frame. When continuous transmission is performed, data should be written after referencing the ASIFn register to confirm the transmission status and whether or not data can be written to the TXBn register.
TXBFn 0 1 Whether or Not Writing to TXBn Register Is Enabled Writing is enabled Writing is not enabled
Caution
When transmission is performed continuously, write the first transmit data (first byte) to the TXBn register and confirm that the TXBFn bit is 0, and then write the next transmit data (second byte) to TXBn register. If writing to the TXBn register is performed when the TXBFn bit is 1, transmit data cannot be guaranteed.
While transmission is being performed continuously, whether writing to the TXBn register later is enabled can be judged by confirming the TXSFn bit after the occurrence of a transmission completion interrupt.
TXSFn 0 Transmission Status Transmission is completed. However, the cautions concerning the TXBFn bit must be observed. Writing transmit data can be performed twice (2 bytes). Under transmission. Transmit data can be written once (1 byte).
1
Cautions 1. When initializing the transmission unit when continuous transmission is completed, confirm that the TXSFn bit is 0 after the occurrence of the transmission completion interrupt, and then execute initialization. If initialization is performed when the TXSFn bit is 1, transmit data cannot be guaranteed. 2. While transmission is being performed continuously, an overrun error may occur if the next transmission is completed before the INTSTn interrupt servicing following the transmission of 1 data frame is executed. An overrun error can be detected by embedding a program that can count the number of transmit data and referencing TXSFn bit.
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Figure 15-5. Continuous Transmission Processing Flow
Set registers
Write transmit data to TXBn register
No
When reading ASIFn register, TXBFn = 0? Yes Interrupt occurrence
Required number of transfers performed? No
Yes
No
When reading ASIFn register, TXSFn = 1? Yes
When reading ASIFn register, TXSFn = 0? Yes
No
Write transmit data to TXBn register
Wait for interrupt
End of transmission processing
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(1) Starting procedure The procedure to start continuous transmission is shown below. Figure 15-6. Continuous Transmission Starting Procedure
TXDn (output) <1> INTSTn (output)
Start bit <2>
Data (1)
Stop bit <3>
Start bit <4>
Data (2)
Stop bit <5>
TXBn register
FFH
Data (1)
Data (2)
Data (3)
TXSn register ASIFn register (TXBFn, TXSFn bits)
FFH
Data (1)
Data (2)
Data (3)
00
10
11
01
11
01
11
01
11
Transmission Starting Procedure
Internal Operation
ASIFn Register TXBFn TXSFn 0 0 1 1 1 1 1
* Set transmission mode * Write data (1)
<1> Start transmission unit
0 1
<2> Generate start bit
1 0
Start data (1) transmission * Read ASIFn register (confirm that TXBFn bit = 0) * Write data (2) <> <3> INTSTn interrupt occurs * Read ASIFn register (confirm that TXBFn bit = 0) * Write data (3) <4> Generate start bit Start data (2) transmission <> <5> INTSTn interrupt occurs * Read ASIFn register (confirm that TXBFn bit = 0) * Write data (4)
0 0 1
0 0 1
1 1 1
0 0 1
1 1 1
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(2) Ending procedure The procedure for ending continuous transmission is shown below. Figure 15-7. Continuous Transmission End Procedure
TXDn (output) <6> INTSTn (output) <7>
Start bit <8>
Data (m - 1)
Stop bit <9>
Start bit <10>
Data (m) <11>
Stop bit
TXBn register
Data (m - 1) Data (m - 1)
Data (m)
TXSn register ASIFn register (TXBFn, TXSFn bits)
Data (m)
FFH
11
01
11
01
00
UARTEn bit or TXEn bit
Transmission End Procedure
Internal Operation
ASIFn Register TXBFn TXSFn 1
<6> Transmission of data (m - 2) is in progress <7> INTSTn interrupt occurs * Read ASIFn register (confirm that TXBFn bit = 0) * Write data (m) <8> Generate start bit Start data (m - 1) transmission <> <9> INTSTn interrupt occurs * Read ASIFn register (confirm that TXSFn bit = 1) There is no write data <10> Generate start bit Start data (m) transmission <> <11> Generate INTSTn interrupt * Read ASIFn register (confirm that TXSFn bit = 0) * Clear (0) the UARTEn bit or TXEn bit Initialize internal circuits
1
0 0 1
1 1 1
0 0
1 1
0 0
0 0
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15.6.4 Receive operation The awaiting reception state is set by setting the UARTEn bit to 1 in the ASIMn register and then setting the RXEn bit to 1 in the ASIMn register. To start the receive operation, first perform start bit detection. The start bit is detected by sampling the RXDn pin. When the receive operation begins, serial data is stored sequentially in the reception shift register according to the baud rate that was set. A reception completion interrupt (INTSRn) is generated each time the reception of one frame of data is completed. Normally, the receive data is transferred from reception buffer register n (RXBn) to memory by this interrupt servicing. (1) Reception enabled state The receive operation is set to the reception enabled state by setting the RXEn bit in the ASIMn register to 1. * RXEn bit = 1: Reception enabled state * RXEn bit = 0: Reception disabled state In reception disabled state, the reception hardware stands by in the initial state. At this time, the contents of reception buffer register n (RXBn) are retained, and no reception completion interrupt or reception error interrupt is generated. (2) Starting a receive operation A receive operation is started by the detection of a start bit. The RXDn pin is sampled using the serial clock from baud rate generator n (BRGn). (3) Reception completion interrupt When RXEn = 1 in the ASIMn register and the reception of one frame of data is completed (the stop bit is detected), a reception completion interrupt (INTSRn) is generated and the receive data within the reception shift register is transferred to RXBn at the same time. Also, if an overrun error (OVEn bit = 1 in the asynchronous serial interface status register (ASISn)) occurs, the receive data at that time is not transferred to reception buffer register n (RXBn), and either a reception completion interrupt (INTSRn) or a reception error interrupt (INTSREn) is generated according to the ISRMn bit setting in the ASIMn register. Even if a parity error (PEn bit = 1 in the ASISn register) or framing error (FEn bit = 1 in the ASISn register) occurs during a reception operation, the receive operation continues until stop bit is received, and after reception is completed, either a reception completion interrupt (INTSRn) or a reception error interrupt (INTSREn) is generated according to the ISRMn bit setting in the ASIMn register (the receive data within the reception shift register is transferred to RXBn). If the RXEn bit is reset (0) during a receive operation, the receive operation is immediately stopped. The contents of reception buffer register n (RXBn) and of the asynchronous serial interface status register (ASISn) at this time do not change, and no reception completion interrupt (INTSRn) or reception error interrupt (INTSREn) is generated. No reception completion interrupt is generated when RXEn = 0 (reception is disabled).
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Figure 15-8. Asynchronous Serial Interface Reception Completion Interrupt Timing
RXDn (input)
Start
D0
D1
D2
D6
D7
Parity
Stop
INTSRn (output)
RXBn register
Cautions 1. Be sure to read reception buffer register n (RXBn) even when a reception error occurs. If RXBn is not read, an overrun error will occur at the next data reception and the reception error status will continue infinitely. 2. Reception is always performed assuming a stop bit length of 1. A second stop bit is ignored.
15.6.5 Reception error The three types of errors that can occur during a receive operation are a parity error, framing error, and overrun error. As a result of data reception, the various flags of the ASISn register are set (1), and a reception error interrupt (INTSREn) or a reception completion interrupt (INTSRn) is generated at the same time. The ISRMn bit of the ASIMn register specifies whether INTSREn or INTSRn is generated. The type of error that occurred during reception can be detected by reading the contents of the ASISn register during the INTSREn or INTSRn interrupt servicing. The contents of the ASISn register are reset (0) by reading the ASISn register. Table 15-2. Reception Error Causes
Error Flag PEn Reception Error Parity error Cause The parity specification during transmission did not match the parity of the reception data No stop bit was detected The reception of the next data was completed before data was read from reception buffer register n (RXBn)
FEn OVEn
Framing error Overrun error
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(1) Separation of reception error interrupt A reception error interrupt can be separated from the INTSRn interrupt and generated as the INTSREn interrupt by clearing the ISRMn bit of the ASIMn register to 0. Figure 15-9. When Reception Error Interrupt Is Separated from INTSRn Interrupt (ISRMn Bit = 0)
(a) No error occurs during reception
(b) An error occurs during reception
INTSRn (output) (Reception completion interrupt) INTSREn (output) (Reception error interrupt)
INTSRn (output) (Reception completion interrupt) INTSREn (output) (Reception error interrupt)
INTSRn does not occur
Figure 15-10. When Reception Error Interrupt Is Included in INTSRn Interrupt (ISRMn Bit = 1)
(a) No error occurs during reception
(b) An error occurs during reception
INTSRn (output) (Reception completion interrupt) INTSREn (output) (Reception error interrupt)
INTSRn (output) (Reception completion interrupt) INTSREn (output) (Reception error interrupt)
INTSREn does not occur
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15.6.6 Parity types and corresponding operation A parity bit is used to detect a bit error in communication data. Normally, the same type of parity bit is used on the transmission and reception sides. (1) Even parity (i) During transmission The parity bit is controlled so that the number of bits with the value "1" within the transmit data including the parity bit is even. The parity bit value is as follows. * If the number of bits with the value "1" within the transmit data is odd: 1 * If the number of bits with the value "1" within the transmit data is even: 0 (ii) During reception The number of bits with the value "1" within the receive data including the parity bit is counted, and a parity error is generated if this number is odd. (2) Odd parity (i) During transmission In contrast to even parity, the parity bit is controlled so that the number of bits with the value "1" within the transmit data including the parity bit is odd. The parity bit value is as follows. * If the number of bits with the value "1" within the transmit data is odd: 0 * If the number of bits with the value "1" within the transmit data is even: 1 (ii) During reception The number of bits with the value "1" within the receive data including the parity bit is counted, and a parity error is generated if this number is even. (3) 0 parity During transmission the parity bit is set to "0" regardless of the transmit data. During reception, no parity bit check is performed. Therefore, no parity error is generated regardless of whether the parity bit is "0" or "1". (4) No parity No parity bit is added to the transmit data. During reception, the receive operation is performed as if there were no parity bit. Since there is no parity bit, no parity error is generated.
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15.6.7 Receive data noise filter The RXDn signal is sampled at the rising edge of the prescaler output base clock (Clock). If the same sampling value is obtained twice, the match detector output changes, and this output is sampled as input data. Therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (see Figure 15-12). Refer to 15.7.1 (1) Base clock (Clock) regarding the base clock. Also, since the circuit is configured as shown in Figure 15-11, internal processing during a receive operation is delayed by up to 2 clocks according to the external signal status. Figure 15-11. Noise Filter Circuit
Clock
RXDn
In
Q
Internal signal A
In LD_EN
Q
Internal signal B
Match detector
Figure 15-12. Timing of RXDn Signal Judged as Noise
Clock
RXDn (input)
Internal signal A
Match
Mismatch (judged as noise)
Match
Mismatch (judged as noise)
Internal signal B
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15.7 Dedicated Baud Rate Generator n (BRGn)
A dedicated baud rate generator, which consists of a source clock selector and an 8-bit programmable counter, generates serial clocks during transmission/reception by UARTn. The dedicated baud rate generator output can be selected as the serial clock for each channel. Separate 8-bit counters exist for transmission and for reception. 15.7.1 Baud rate generator n (BRGn) configuration Figure 15-13. Configuration of Baud Rate Generator n (BRGn)
UARTEn
fXXNote 1 fXX/2Note 2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 fXX/1,024 External input ASCK0Note 3 Match detector 1/2 Baud rate Selector Clock (fCLK) 8-bit counter UARTEn and TXEn (or RXEn)
CKSRn: TPSn3 to TPSn0
BRGCn: MDLn7 to MDLn0
Notes 1. 2. 3. Remark
VDD = 4.0 to 5.5 V: Selectable when fXX 12 MHz VDD = 2.7 to 4.0 V: Selectable when fXX 6 MHz VDD = 2.7 to 4.0 V: Selectable when fXX 12 MHz ASCK0 can be used only by UART0. fXX: Internal system clock
(1) Base clock (Clock) When the UARTEn bit = 1 in the ASIMn register, the clock selected according to the TPSn3 to TPSn0 bits of the CKSRn register is supplied to the transmission/reception unit. This clock is called the base clock (Clock), and its frequency is referred to as fCLK. When UARTEn = 0, Clock is fixed to low level.
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15.7.2 Serial clock generation A serial clock can be generated according to the settings of the CKSRn and BRGCn registers. The base clock to the 8-bit counter is selected by the TPSn3 to TPSn0 bits of the CKSRn register. The 8-bit counter divisor value can be set by the MDLn7 to MDLn0 bits of the BRGCn register. (1) Clock select register n (CKSRn) The CKSRn register is an 8-bit register for selecting the basic block using the TPSn3 to TPSn0 bits. The clock selected by the TPSn3 to TPSn0 bits becomes the base clock (Clock) of the transmission/ reception module. Its frequency is referred to as fCLK. This register can be read or written in 8-bit units. Caution Set the UARTEn bit of the ASIMn register to 0 before rewriting the TPSn3 to TPSn0 bits.
After reset: 00H 7 CKSRn 0
R/W 6 0
Address: FFFFFA06H, FFFFFA16H, FFFFFA26H 5 0 4 0 3 TPSn3 2 TPSn2 1 TPSn1 0 TPSn0
TPSn3 0 0 0 0 0 0 0 0 1 1 1 1
TPSn2 0 0 0 0 1 1 1 1 0 0 0 0
TPSn1 0 0 1 1 0 0 1 1 0 0 1 1
TPSn0 0 1 0 1 0 1 0 1 0 1 0 1 fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 fXX/1,024
Receive operation (fCLK)Note 1
ASCK0Note 2 (external input) Setting prohibited
Other than above
Notes 1. Set so as to satisfy the following conditions. VDD = 4.0 to 5.5 V: fCLK 12 MHz VDD = 2.7 to 4.0 V: fCLK 6 MHz 2. ASCK0 input clock can be used only by UART0. Setting of UART1 and UART2 is prohibited. Remark n: 0 to 2
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(2) Baud rate generator control register n (BRGCn) The BRGCn register is an 8-bit register that controls the baud rate (serial transfer speed) of UARTn. This register can be read or written in 8-bit units. Caution If the MDLn7 to MDLn0 bits are to be overwritten, the TXEn and RXEn bits should be set to 0 in the ASIMn register first.
After reset: FFH 7 BRGCn MDLn7
R/W 6 MDLn6
Address: FFFFFA07H, FFFFFA17H, FFFFFA27H 5 MDLn5 4 MDLn4 3 MDLn3 2 MDLn2 1 MDLn1 0 MDLn0
MDLn7 MDLn6 MDLn5 MDLn4 MDLn3 MDLn2 MDLn1 MDLn0 x 0 0 0 ... x 0 0 1 ... x 0 1 0 ...
Setting value (k) - 8 9 10 ...
Serial clock
0 0 0 0 ...
0 0 0 0 ...
0 0 0 0 ...
0 0 0 0 ...
0 1 1 1 ...
Setting prohibited fCLK/8 fCLK/9 fCLK/10 ... fCLK/250 fCLK/251 fCLK/252 fCLK/253 fCLK/254 fCLK/255
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
0 0 1 1 1 1
1 1 0 0 1 1
0 1 0 1 0 1
250 251 252 253 254 255
Remarks 1. fCLK: Frequency [Hz] of base clock (Clock) selected by TPSn3 to TPSn0 bits of CKSRn register 2. k: Value set by MDLn7 to MDLn0 bits (k = 8, 9, 10, ..., 255) 3. The baud rate is the output clock for the 8-bit counter divided by 2 4. x: Don't care
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(3) Baud rate The baud rate is the value obtained by the following formula.
Baud rate =
fCLK 2xk
[bps]
fCLK = Frequency [Hz] of base clock (Clock) selected by TPSn3 to TPSn0 bits of CKSRn register. k = Value set by MDLn7 to MDLn0 bits of BRGCn register (k = 8, 9, 10, ..., 255)
(4) Baud rate error The baud rate error is obtained by the following formula.
Actual baud rate (baud rate with error) Error (%) = Desired baud rate (normal baud rate) - 1 x 100 [%] Cautions 1. Make sure that the baud rate error during transmission does not exceed the allowable error of the reception destination. 2. Make sure that the baud rate error during reception is within the allowable baud rate range during reception, which is described in (4) Allowable baud rate during reception.
Example: Base clock frequency = 10 MHz = 10,000,000 Hz Setting of MDLn7 to MDLn0 bits in BRGCn register = 00100001B (k = 33) Target baud rate = 153,600 bps Baud rate = 10M/(2 x 33) = 10,000,000/(2 x 33) = 151,515 [bps] Error = (151,515/153,600 - 1) x 100 = -1.357 [%]
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15.7.3 Baud rate setting example Table 15-3. Baud Rate Generator Setting Data
fXX = 20 MHz fCLK fXX/512 fXX/256 fXX/128 fXX/64 fXX/32 fXX/16 fXX/64 fXX/8 fXX/32 fXX/32 fXX/2 fXX/4 fXX/16 fXX/2 fXX/16 fXX/2 fXX/2 fXX/2 fXX/4 k 41H (65) 41H (65) 41H (65) 41H (65) 41H (65) 41H (65) 0FH (15) 41H (65) 0DH (13) 0AH (10) 95H (149) 41H (65) 0DH (13) 59H (89) 0AH (10) 41H (65) 2BH (43) 21H (33) 08H (8) ERR 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -0.13 0.16 0.16 0.32 0.00 0.16 0.94 -1.36 0 fCLK fXX/1024 fXX/1024 fXX/512 fXX/256 fXX/128 fXX/64 fXX/64 fXX/32 fXX/2 fXX/32 fXX/2 fXX/16 fXX/2 fXX/2 fXX/16 fXX/8 fXX/2 fXX/4 fXX/2 fXX = 16 MHz k 1AH (26) 0DH (13) 0DH (13) 0DH (13) 0DH (13) 0DH (13) 0CH (12) 0DH (13) A7H (167) 08H (8) 77H (119) 0DH (13) 53H (83) 47H (71) 08H (8) 0DH (13) 23H (35) 0DH (13) 0DH (13) ERR 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -0.20 0.00 0.04 0.16 0.40 0.60 0.00 0.16 -0.79 0.16 -1.54 fCLK fXX/256 fXX/128 fXX/64 fXX/32 fXX/16 fXX/8 fXX/32 fXX/4 fXX/16 fXX/16 fXX fXX/2 fXX/8 fXX fXX/8 fXX fXX fXX fXX/2 fXX = 10 MHz k 41H (65) 41H (65) 41H (65) 41H (65) 41H (65) 41H (65) 0FH (15) 41H (65) 0DH (13) 0AH (10) 95H (149) 41H (65) 0DH (13) 59H (89) 0AH (10) 41H (65) 2BH (43) 21H (33) 08H (8) ERR 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0 -0.13 0.16 0.16 0.32 0.00 0.16 0.94 -1.36 0.00
Baud Rate (bps) 300 600 1200 2400 4800 9600 10400 19200 24000 31250 33600 38400 48000 56000 62500 76800 115200 153600 312500
Caution The maximum allowable frequency of the base clock (fCLK) is 12 MHz. Remark fXX: fCLK: k: ERR: Internal system clock frequency Base clock frequency Setting values of MDLn7 to MDLn0 bits in BRGCn register Baud rate error [%]
n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1)
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15.7.4 Allowable baud rate range during reception The degree to which a discrepancy from the transmission destination's baud rate is allowed during reception is shown below. Caution The equations described below should be used to set the baud rate error during reception so that it always is within the allowable error range. Figure 15-14. Allowable Baud Rate Range During Reception
Latch timing UARTn transfer rate
Start bit
Bit 0 FL
Bit 1
Bit 7
Parity bit
Stop bit
1 data frame (11 x FL)
Minimum allowable transfer rate
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FLmin
Maximum allowable transfer rate
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FLmax
As shown in Figure 15-14, after the start bit is detected, the receive data latch timing is determined according to the counter that was set by the BRGCn register. If all data up to the final data (stop bit) is in time for this latch timing, the data can be received normally. If this is applied to 11-bit reception, the following is theoretically true. FL = (Brate)
-1
Brate: UARTn baud rate k: FL: BRGCn register setting value 1-bit data length
When the latch timing margin is 2 base clocks (Clock), the minimum allowable transfer rate (FLmin) is as follows. FL min = 11x FL - k-2 2k x FL = 21k + 2 2k
FL
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Therefore, the transfer destination's maximum receivable baud rate (BRmax) is as follows.
BRmax = (FLmin/11)- =
1
22k 21k + 2 Brate
Similarly, the maximum allowable transfer rate (FLmax) can be obtained as follows. 21k - 2 k+2 10 FL x FL = x FL max = 11x FL - 2xk 2xk 11 21k - 2 FL x 11 FL max = 20k Therefore, the transfer destination's minimum receivable baud rate (BRmin) is as follows.
BRmin = (FLmax/11)- =
1
20k 21k - 2
Brate
The allowable baud rate error of UARTn and the transfer destination can be obtained as follows from the expressions described above for computing the minimum and maximum baud rate values. Table 15-4. Maximum and Minimum Allowable Baud Rate Error
Division Ratio (k) Maximum Allowable Baud Rate Error +3.53% +4.26% +4.56% +4.66% +4.72% Minimum Allowable Baud Rate Error -3.61% -4.31% -4.58% -4.67% -4.73%
8 20 50 100 255
Remarks 1. The reception precision depends on the number of bits in one frame, the base clock frequency, and the division ratio (k). The higher the base clock frequency and the larger the division ratio (k), the higher the precision. 2. k: BRGCn setting value
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15.7.5 Transfer rate during continuous transmission During continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks of the base clock (Clock) longer than normal. However, on the reception side, the transfer result is not affected since the timing is initialized by the detection of the start bit. Figure 15-15. Transfer Rate During Continuous Transmission
1 data frame
Start bit of second byte Bit 7 FL Parity bit FL Stop bit FLstp Start bit FL Bit 0 FL
Start bit FL
Bit 0 FL
Bit 1 FL
Representing the 1-bit data length by FL, the stop bit length by FLstp, and the base clock frequency by fCLK yields the following equation. FLstp = FL + 2/fCLK Therefore, the transfer rate during continuous transmission is as follows (when the stop bit length = 1). Transfer rate = 11 x FL = 2/fCLK
15.8 Cautions
Cautions to be observed when using UARTn are shown below. (1) When the supply of clocks to UARTn is stopped (for example, in IDLE or STOP mode), operation stops with each register retaining the value it had immediately before the supply of clocks was stopped. The TXDn pin output also holds and outputs the value it had immediately before the supply of clocks was stopped. However, operation is not guaranteed after the supply of clocks is restarted. Therefore, after the supply of clocks is restarted, the circuits should be initialized by setting UARTEn = 0, RXEn = 0, and TXEn = 0 in the ASIMn register. (2) UARTn has a 2-stage buffer configuration consisting of transmission buffer register n (TXBn) and the transmission shift register, and has status flags (the TXBFn and TXSFn bits of the ASIFn register) that indicate the status of each buffer. If the TXBFn and TXSFn bits are read in continuous transmission, the value changes 10 11 01. Read only the TXBFn bit during continuous transmission.
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The number of clocked serial interface 0 (CSI0) channels incorporated differs as follows depending on the product.
Product Name Number of channels V850ES/KF1 2 channels (CSI00, CSI01) V850ES/KG1 V850ES/KJ1 3 channels (CSI00 to CSI02)
16.1 Features
* * * * * *
Half-duplex communications Master mode/slave mode selectable Transmission data length: 8 bits or 16 bits can be set MSB/LSB-first selectable for transfer data Eight clock signals can be selected (7 master clocks and 1 slave clock) 3-wire type SO0n: SI0n: Serial transmit data output Serial receive data input
SCK0n: Serial clock I/O
* Interrupt sources: 1 type * Transmission/reception mode or reception-only mode selectable * Two transmission buffers (SOTBFn/SOTBFLn, SOTBn/SOTBLn) and two reception buffers (SIRBn/SIRBLn,
SIRBEn/SIRBELn) are provided on chip * Transmission/reception completion interrupt (INTCSI0n)
* Single transfer mode/repeat transfer mode selectable
Remark n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1)
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16.2 Configuration
CSI0n is controlled via clocked serial interface mode register 0n (CSIM0n). (1) Clocked serial interface mode register 0n (CSIM0n) The CSIM0n register is an 8-bit register that specifies the operation of CSI0n. (2) Clocked serial interface clock selection register n (CSICn) The CSICn register is an 8-bit register that controls the CSI0n serial transfer operation. (3) Serial I/O shift register 0n (SIO0n) The SIO0n register is a 16-bit shift register that converts parallel data into serial data. The SIO0n register is used for both transmission and reception. Data is shifted in (reception) and shifted out (transmission) from the MSB or LSB side. The actual transmission/reception operations are started up by accessing the buffer register. (4) Serial I/O shift register 0nL (SIO0nL) The SIO0nL register is an 8-bit shift register that converts parallel data into serial data. The SIO0nL register is used for both transmission and reception. Data is shifted in (reception) and shifted out (transmission) from the MSB or LSB side. The actual transmission/reception operations are started up by access of the buffer register . (5) Clocked serial interface reception buffer register n (SIRBn) The SIRBn register is a 16-bit buffer register that stores receive data. (6) Clocked serial interface reception buffer register nL (SIRBnL) The SIRBnL register is an 8-bit buffer register that stores receive data. (7) Clocked serial interface read-only reception buffer register n (SIRBEn) The SIRBEn register is a 16-bit buffer register that stores receive data. The SIRBEn register is the same as the SIRBn register. It is used to read the contents of the SIRBn register. (8) Clocked serial interface read-only reception buffer register nL (SIRBEnL) The SIRBEnL register is an 8-bit buffer register that stores receive data. The SIRBEnL register is the same as the SIRBnL register. It is used to read the contents of the SIRBnL register. (9) Clocked serial interface transmission buffer register n (SOTBn) The SOTBn register is a 16-bit buffer register that stores transmit data. (10) Clocked serial interface transmission buffer register nL (SOTBLnL) The SOTBnL register is an 8-bit buffer register that stores transmit data. (11) Clocked serial interface initial transmission buffer register n (SOTBFn) The SOTBFn register is a 16-bit buffer register that stores the initial transmit data in the repeat transfer mode.
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(12) Clocked serial interface initial transmission buffer register nL (SOTBFnL) The SOTBFnL register is an 8-bit buffer register that stores initial transmit data in the repeat transfer mode. (13) Selector The selector selects the serial clock to be used. (14) Serial clock controller Controls the serial clock supply to the shift register. Also controls the clock output to the SCK0n pin when the internal clock is used. (15) Serial clock counter Counts the serial clock output or input during transmission/reception operation, and checks whether 8-bit or 16-bit data transmission/reception has been performed. (16) Interrupt controller Controls the interrupt request timing. Remark n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1)
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Figure 16-1. Block Diagram of Clocked Serial Interface
fXX/26 fXX/25 fXX/24 fXX/23 fXX/22 fXX/2 TO50, TO51 External input SCK0n Selector
Serial clock controller Clock start/stop control & clock phase control SCK0n
Interrupt controller
INTCSI0n
Transmission control
Transmission data control
Initial transmit buffer register (SOTBFn/SOTBFnL)
Control signal
SO selection
SO0n
Transmit buffer register (SOTBn/SOTBnL)
SI0n
Shift register (SIOn/SIO0nL)
SO latch
Receive buffer register (SIRBn/SIRBnL)
Remarks 1. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) 2. fXX: Internal system clock
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16.3 Control Registers
(1) Clocked serial interface mode register 0n (CSIM0n) The CSIM0n register controls the CSI0n operation. These registers can be read/written in 8-bit or 1-bit units (however, bit 0 is read-only). Caution Overwriting the TRMDn, CCLn, DIRn, CSITn, and AUTOn bits of the CSIM0n register can be done only when the CSOTn bit = 0. If these bits are overwritten at any other time, the operation cannot be guaranteed.
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After reset: 00H <7> CSIM0n CSI0En
R/W <6> TRMDn
Address: FFFFFD00H, FFFFFD10H, FFFFFD20H 5 CCLn <4> DIRn 3 CSITn 2 AUTOn 1 0 <0> CSOTn
CSI0En 0 1 Enables CSI0n operation. Disables CSI0n operation.
Enables/disables CSI0n operation
The internal CSI0n circuit can be reset asynchronously by setting the CSI0En bit to 0. For the SCK0n and SO0n pin output status when the CSI0En bit = 0, refer to 16.5 Output Pins.
TRMDn 0 1 Receive-only mode Transmission/reception mode
Specifies transmission/reception mode
When the TRMDn bit = 0, receive-only transfer is performed and the SO0n pin output is fixed to low level. Data reception is started by reading the SIRBn register. When the TRMDn bit = 1, transmission/reception is started by writing data to the SOTBn register.
CCLn 0 1 8 bits 16 bits
Specifies data length
DIRn 0 1
Specifies transfer direction mode (MSB/LSB) First bit of transfer data is MSB First bit of transfer data is LSB
CSITn 0 1 No delay
Controls delay of interrupt request signal
Delay mode (interrupt request signal is delayed 1/2 cycle)
The delay mode (CSITn bit = 1) is valid only in the master mode (CKS0n2 to CSK0n0 bits of the CSICn register are not 111B). In the slave mode (CKS0n2 to CKS0n0 bits are 111B), do not set the delay mode.
AUTOn 0 1 Single transfer mode Repeat transfer mode
Specifies single transfer mode or repeat transfer mode
CSOTn 0 1 Idle status Transfer execution status
Flag indicating transfer status
The CSOTn bit is cleared (0) by writing 0 to the CSI0En bit.
Remark
n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1)
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(2) Clocked serial interface clock selection register n (CSICn) The CSICn register is an 8-bit register that controls the CSI0n transfer operation. These registers can be read/written in 8-bit or 1-bit units. Caution The CSICn register can be overwritten only when the CSI0En bit of the CSIM0n register = 0.
After reset: 00H 7 CSICn 0
R/W 6 0
Address: FFFFFD01H, FFFFFD11H, FFFFFD21H 5 0 4 CKPn 3 DAPn 2 CKS0n2 1 CKS0n1 0 CKS0n0
CKPn 0
DAPn 0
SCK0n (I/O) SO0n (output) SI0n (input)
Operation mode
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
0
1
SCK0n (I/O) SO0n (output) SI0n (input) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
1
0
SCK0n (I/O) SO0n (output) SI0n (input) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
1
1
SCK0n (I/O) SO0n (output) SI0n (input) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
CKS0n2 CKS0n1 CKS0n0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fXX/2 fXX/2 fXX/2 fXX/2
Note 1
Input clock Master mode Master mode Master mode Master mode Master mode Master mode
Note 2
Mode
2
3
4
fXX/25 fXX/2
6
Clock generated by TO50, TO51 External clock (SCK0n)
Master mode Slave mode
Notes 1. Selectable when fXX 10 MHz 2. CSI00: TO50 CSI01: TO51 CSI02: TO51 Remarks 1. fXX: Internal system clock frequency 2. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1)
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(3) Clocked serial interface reception buffer register n (SIRBn) The SIRBn register is a 16-bit buffer register that stores receive data. When the receive-only mode is set (TRMDn bit of CSIM0n register = 0), the reception operation is started by reading data from the SIRBn register. These registers are read-only, in 16-bit units. In addition to reset input, these registers can also be initialized by clearing (0) the CSI0En bit of the CSIM0n register. Cautions 1. Read the SIRBn register only when the 16-bit data length has been set (CCLn bit of CSIM0n register = 1). 2. When the single transfer mode has been set (AUTOn bit of CSIM0n register = 0), perform a read operation only in the idle state (CSOTn bit of CSIM0n register = 0). If the SIRBn register is read during data transfer, the data cannot be guaranteed.
After reset: 0000H 15 14 13
R 12
Address: FFFFFD02H, FFFFFD12H, FFFFFD22H 11 10 9 8 7 6 5 4 3 2 1 0
SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Remark
n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1)
(4) Clocked serial interface reception buffer register nL (SIRBnL) The SIRBnL register is an 8-bit buffer register that stores receive data. When the receive-only mode is set (TRMDn bit of CSIM0n register = 0), the reception operation is started by reading data from the SIRBnL register. These registers are read-only, in 8-bit or 1-bit units. In addition to reset input, these registers can also be initialized by clearing (0) the CSI0En bit of the CSIM0n register. The SIRBnL register is the same as the lower bytes of the SIRBn register. Cautions 1. Read the SIRBnL register only when the 8-bit data length has been set (CCLn bit of CSIM0n register = 0). 2. When the single transfer mode is set (AUTOn bit of CSIM0n register = 0), perform a read operation only in the idle state (CSOTn bit of CSIM0n register = 0). register is read during data transfer, the data cannot be guaranteed. If the SIRBnL
After reset: 00H 7 SIRBnL SIRBn7
R 6
Address: FFFFFD02H, FFFFFD12H, FFFFFD22H 5 SIRBn5 4 SIRBn4 3 SIRBn3 2 SIRBn2 1 SIRBn1 0 SIRBn0
SIRBn6
Remark
n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1)
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(5) Clocked serial interface read-only reception buffer register n (SIRBEn) The SIRBEn register is a 16-bit buffer register that stores receive data. These registers are read-only, in 16-bit units. In addition to reset input, this register can also be initialized by clearing (0) the CSI0En bit of the CSIM0n register. The SIRBEn register is the same as the SIRBn register. It is used to read the contents of the SIRBn register. Cautions 1. The receive operation is not started even if data is read from the SIRBEn register. 2. The SIRBEn register can be read only if the 16-bit data length is set (CCLn bit of CSIM0n register = 1).
After reset: 0000H 15 14
R 13
Address: FFFFFD06H, FFFFFD16H, FFFFFD26H 12 11 10 9 8 7 6 5 4 3 2 1 0
SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Remark
n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1)
(6) Clocked serial interface read-only reception buffer register nL (SIRBEnL) The SIRBEnL register is an 8-bit buffer register that stores receive data. These registers are read-only, in 8-bit or 1-bit units. In addition to reset input, this register can also be initialized by clearing (0) the CSI0En bit of the CSIM0n register. The SIRBEnL register is the same as the SIRBnL register. It is used to read the contents of the SIRBnL register. Cautions 1. The receive operation is not started even if data is read from the SIRBEnL register. 2. The SIRBEnL register can be read only if the 8-bit data length has been set (CCLn bit of CSIM0n register = 0).
After reset: 00H 7
R 6
Address: FFFFFD06H, FFFFFD16H, FFFFFD26H 5 4 3 2 1 0
SIRBEnL SIRBEn7 SIRBEn6 SIRBEn5 SIRBEn4 SIRBEn3 SIRBEn2 SIRBEn1 SIRBEn0
Remark
n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1)
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(7) Clocked serial interface transmission buffer register n (SOTBn) The SOTBn register is a 16-bit buffer register that stores transmit data. When the transmission/reception mode is set (TRMDn bit of CSIM0n register = 1), the transmission operation is started by writing data to the SOTBn register. This register can be read/written in 16-bit units. Cautions 1. Access the SOTBn register only when the 16-bit data length is set (CCLn bit of CSIM0n register = 1). 2. When the single transfer mode is set (AUTOn bit of CSIM0n register = 0), perform access only in the idle state (CSOTn bit of CSIM0n register = 0). If the SOTBn register is accessed during data transfer, the data cannot be guaranteed.
After reset: 0000H 15 14
R/W 13 12
Address: FFFFFD04H, FFFFFD14H, FFFFFD24H 11 10 9 8 7 6 5 4 3 2 1 0
SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Remark
n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1)
(8) Clocked serial interface transmission buffer register nL (SOTBnL) The SOTBnL register is an 8-bit buffer register that stores transmit data. When the transmission/reception mode is set (TRMDn bit of CSIM0n register = 1), the transmission operation is started by writing data to the SOTBnL register. These registers can be read/written in 8-bit or 1-bit units. The SOTBnL register is the same as the lower bytes of the SOTBn register. Cautions 1. Access the SOTBnL register only when the 8-bit data length has been set (CCLn bit of CSIM0n register = 0). 2. When the single transfer mode is set (AUTOn bit of CSIM0n register = 0), perform access only in the idle state (CSOTn bit of CSIM0n register = 0). If the SOTBnL register is accessed during data transfer, the data cannot be guaranteed.
After reset: 00H 7 SOTBnL
R/W 6
Address: FFFFFD04H, FFFFFD14H, FFFFFD24H 5 4 3 2 1 0
SOTBn7 SOTBn6 SOTBn5 SOTBn4 SOTBn3 SOTBn2 SOTBn1 SOTBn0
Remark
n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1)
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(9) Clocked serial interface initial transmission buffer register n (SOTBFn) The SOTBFn register is a 16-bit buffer register that stores initial transmission data in the repeat transfer mode. The transmission operation is not started even if data is written to the SOTBFn register. These registers can be read/written in 16-bit units. Caution Access the SOTBFn register only when the 16-bit data length has been set (CCLn bit of CSIM0n register = 1), and only in the idle state (CSOTn bit of CSIM0n register = 0). If the SOTBFn register is accessed during data transfer, the data cannot be guaranteed.
After reset: 0000H 15 14
R/W 13 12
Address: FFFFFD08H, FFFFFD18H, FFFFFD28H 11 10 9 8 7 6 5 4 3 2 1 0
SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Remark
n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1)
(10)
Clocked serial interface initial transmission buffer register nL (SOTBFnL) The SOTBFnL register is an 8-bit buffer register that stores initial transmission data in the repeat transfer mode. The transmission operation is not started even if data is written to the SOTBFnL register. These registers can be read/written in 8-bit or 1-bit units. The SOTBFnL register is the same as the lower bytes of the SOTBFn register. Caution Access the SOTBFnL register only when the 8-bit data length has been set (CCLn bit of CSIM0n register = 0), and only in the idle state (CSOTn bit of CSIM0n register = 0). If the SOTBFnL register is accessed during data transfer, the data cannot be guaranteed.
After reset: 00H 7
R/W 6
Address: FFFFFD08H, FFFFFD18H, FFFFFD28H 5 4 3 2 1 0
SOTBFnL SOTBFn7 SOTBFn6 SOTBFn5 SOTBFn4 SOTBFn3 SOTBFn2 SOTBFn1 SOTBFn0
Remark
n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1)
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(11)
Serial I/O shift register n (SIO0n) The SIO0n register is a 16-bit shift register that converts parallel data into serial data. The transfer operation is not started even if the SIO0n register is read. These registers are read-only, in 16-bit units. In addition to reset input, this register can also be initialized by clearing (0) the CSI0En bit of the CSIM0n register. Caution Access the SIO0n register only when the 16-bit data length has been set (CCLn bit of CSIM0n register = 1), and only in the idle state (CSOTn bit of CSIM0n register = 0). If the SIO0n register is accessed during data transfer, the data cannot be guaranteed.
After reset: 0000H 15 14 13
R 12
Address: FFFFFD0AH, FFFFFD1AH, FFFFFD2AH 11 10 9 8 7 6 5 4 3 2 1 0
SIO0n SIOn15 SIOn14 SIOn13 SIOn12 SIOn11 SIOn10 SIOn9 SIOn8 SIOn7 SIOn6 SIOn5 SIOn4 SIOn3 SIOn2 SIOn1 SIOn0
Remark
n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1)
(12)
Serial I/O shift register 0nL (SIO0nL) The SIO0nL register is an 8-bit shift register that converts parallel data into serial data. The transfer operation is not started even if the SIO0nL register is read. These registers are read-only, in 8-bit or 1-bit units. In addition to reset input, this register can also be initialized by clearing (0) the CSI0En bit of the CSIM0n register. The SIO0nL register is the same as the lower bytes of the SIO0n register. Caution Access the SIO0nL register only when the 8-bit data length has been set (CCLn bit of CSIM0n register = 0), and only in the idle state (CSOTn bit of CSIM0n register = 0). If the SIO0nL register is accessed during data transfer, the data cannot be guaranteed.
After reset: 00H 7 SIO0nL SIOn7
R 6 SIOn6
Address: FFFFFD0AH, FFFFFD1AH, FFFFFD2AH 5 SIOn5 4 SIOn4 3 SIOn3 2 SIOn2 1 SIOn1 0 SIOn0
Remark
n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1)
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16.4 Operation
16.4.1 Single transfer mode (1) Usage In the receive-only mode (TRMDn bit of CSIM0n register = 0), transfer is started by reading interface receive buffer registers n and nL (SIRBn/SIRBnL). In the transmission/reception mode n and nL (TRMDn bit of CSIM0n register = 1), transfer is started by writing
Note 2 Note 1
clocked serial
to clocked serial interface transmit buffer registers n and nL (SOTBn/SOTBnL).
In the slave mode, the operation must be enabled beforehand (CSI0En bit of CSIM0n register = 1). When transfer is started, the value of the CSOTn bit of the CSIM0n register becomes 1 (transmission execution status). Upon transfer completion, the transmission/reception completion interrupt (INTCSI0n) is set (1), and the CSOTn bit is cleared (0). The next data transfer request is then waited for. Notes 1. When the 16-bit data length (CCLn bit of CSIM0n register = 1) has been set, read the SIRBn register. When the 8-bit data length (CCLn bit of CSIM0n register = 0) has been set, read the SIRBnL register. 2. When the 16-bit data length (CCLn bit of CSIM0n register = 1) has been set, write to the SOTBn register. When the 8-bit data length (CCLn bit of CSIM0n register = 0) has been set, write to the SOTBnL register. Caution Remark When the CSOTn bit of the CSIM0n register = 1, do not manipulate the CSI0n register. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1)
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Figure 16-2. Timing Chart in Single Transfer Mode (1/2)
(a) In transmission/reception mode, data length: 8 bits, transfer direction: MSB first, no interrupt delay, single transfer mode, operation mode: CKPn bit = 0, DAPn bit = 0
SCK0n (I/O) SO0n (output) SI0n (input) 0 1 0 1 0 1 0 1 (55H)
1
0
1
0
1
0
1
0
(AAH)
Reg_R/W SOTBnL register SIO0nL register SIRBnL register CSOTn bit INTCSI0n interrupt
Write 55H to SOTBnL register
55H (transmit data)
ABH
56H
ADH
5AH
B5H
6AH
D5H
AAH
AAH
Remarks 1. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) 2. Reg_R/W: Internal signal. This signal indicates that a clocked serial interface receive buffer register n and nL (SIRBn/SIRBnL) read or clocked serial interface transmit buffer register n and nL (SOTBn/SOTBnL) write was performed.
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Figure 16-2. Timing Chart in Single Transfer Mode (2/2)
(b) In transmission/reception mode, data length: 8 bits, transfer direction: MSB first, no interrupt delay, single transfer mode, operation mode: CKPn bit = 0, DAPn bit = 1
SCK0n (I/O) SO0n (output) SI0n (input) Reg_R/W SOTBnL register SIO0nL register SIRBnL register CSOTn bit INTCSI0n interrupt ABH 56H 0 1 0 1 0 1 0 1 (55H)
1
0
1
0
1
0
1
0
(AAH)
Write 55H to SOTBnL register
55H (transmit data)
ADH
5AH
B5H
6AH
D5H
AAH
AAH
Remarks 1. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) 2. Reg_R/W: Internal signal. This signal indicates that a clocked serial interface receive buffer register n and nL (SIRBn/SIRBnL) read or clocked serial interface transmit buffer register n and nL (SOTBn/SOTBnL) write was performed.
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(2) Clock phase selection The following shows the timing when changing the conditions for clock phase selection (CKPn bit of CSICn register) and data phase selection (DAPn bit of CSICn register) under the following conditions. * Data length = 8 bits (CCLn bit of CSIM0n register = 0) * First bit of transfer data = MSB (DIRn bit of CSIM0n register = 0) * No interrupt request signal delay control (CSITn bit of CSIM0n register = 0) Figure 16-3. Timing Chart According to Clock Phase Selection (1/2)
(a) When CKPn bit = 0, DAPn bit = 0
SCK0n (I/O) SI0n (input) SO0n (output) Reg_R/W INTCSI0n interrupt CSOTn bit DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
(b) When CKPn bit = 1, DAPn bit = 0
SCK0n (I/O) SI0n (input) SO0n (output) Reg_R/W INTCSI0n interrupt CSOTn bit DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
Remarks 1. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) 2. Reg_R/W: Internal signal. This signal indicates that a clocked serial interface receive buffer register n and nL (SIRBn/SIRBnL) read or clocked serial interface transmit buffer register n and nL (SOTBn/SOTBnL) write was performed.
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Figure 16-3. Timing Chart According to Clock Phase Selection (2/2)
(c) When CKPn bit = 0, DAPn bit = 1
SCK0n (I/O) SI0n (input) SO0n (output) Reg_R/W INTCSI0n interrupt CSOTn bit DI7 DO7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
DO6 DO5 DO4 DO3 DO2 DO1 DO0
(d) When CKPn bit = 1, DAPn bit = 1
SCK0n (I/O) SI0n (input) SO0n (output) Reg_R/W INTCSI0n interrupt CSOTn bit DI7 DO7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
DO6 DO5 DO4 DO3 DO2 DO1 DO0
Remarks 1. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) 2. Reg_R/W: Internal signal. This signal indicates that a clocked serial interface receive buffer register n and nL (SIRBn/SIRBnL) read or clocked serial interface transmit buffer register n and nL (SOTBn/SOTBnL) write was performed.
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(3) Transmission/reception completion interrupt request signal (INTCSI0n) INTCSI0n is set (1) upon completion of data transmission/reception. INTCSI0n is cleared (0) by reading from clocked serial interface receive buffer registers n and nL (SIRBn, SIRBnL) or writing to clocked serial interface transmit buffer registers n and nL (SOTBn, SOTBnL). Writing to CSIM0n register also clears (0) INTCSI0n. Caution The delay mode (CSITn bit = 1) is valid only in the master mode (bits CKS0n2 to CKS0n0 of the CSICn register are not 111B). The delay mode cannot be set when the slave mode is set (bits CKS0n2 to CKS0n0 = 111B). Figure 16-4. Timing Chart of Interrupt Request Signal Output in Delay Mode (1/2)
(a) When CKPn bit = 0, DAPn bit = 0
Input clock
SCK0n (I/O)
SI0n (input)
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO0n (output)
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Reg_R/W
INTCSI0n interrupt
CSOTn bit Delay
Remarks 1. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) 2. Reg_R/W: Internal signal. This signal indicates that a clocked serial interface receive buffer register n and nL (SIRBn/SIRBnL) read or clocked serial interface transmit buffer register n and nL (SOTBn/SOTBnL) write was performed.
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Figure 16-4. Timing Chart of Interrupt Request Signal Output in Delay Mode (2/2)
(b) When CKPn bit = 1, DAPn bit = 1
Input clock
SCK0n (I/O)
SI0n (input)
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO0n (output)
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Reg_R/W
INTCSI0n interrupt
CSOTn bit Delay
Remarks 1. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) 2. Reg_R/W: Internal signal. This signal indicates that a clocked serial interface receive buffer register n and nL (SIRBn/SIRBnL) read or clocked serial interface transmit buffer register n and nL (SOTBn/SOTBnL) write was performed.
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16.4.2 Repeat transfer mode (1) Usage (receive-only) <1> Set the repeat transfer mode (AUTOn bit of CSIM0n register = 1) and the receive-only mode (TRMDn bit of CSIM0n register = 0). <2> Read the SIRBn register (start transfer with dummy read). <3> Wait for the transmission/reception completion interrupt request (INTCSI0n). <4> When the transmission/reception completion interrupt request (INTCSI0n) has been set (1), read the SIRBn register
Note
(reserve next transfer).
<5> Repeat steps <3> and <4> (N - 2) times. (N: Number of transfer data) <6> Following output of the last transmission/reception completion interrupt request (INTCSI0n), read the SIRBEn register and the SIO0n register
Note
.
Note When transferring N number of data, receive data is loaded by reading the SIRBn register from the first data to the (N - 2)th data. The (N - 1)th data is loaded by reading the SIRBEn register, and the Nth (last) data is loaded by reading the SIO0n register.
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Figure 16-5. Repeat Transfer (Receive-Only) Timing Chart
SCK0n (I/O) SI0n (input) SIO0nL register SIRBnL register Reg_RD CSOTn bit INTCSI0n interrupt SO0n (output) rq_clr trans_rq <1> <2> <3> <4> <3> <5> Period during which next transfer can be reserved <4> <3> <4> <6> L SIRBn (dummy) din-1 din-2 din-3 din-4 din-5 din-5 din-1 SIRBn (d1) din-2 din-3 SIRBn (d2) din-4 SIRBn (d3) SIRBEn (d4) SIO0n (d5)
Remarks 1. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) 2. Reg_RD: Internal signal. This signal indicates that clocked serial interface receive buffer registers n and nL (SIRBn/SIRBnL) have been read. rq_clr: Internal signal. Transfer request clear signal. trans_rq: Internal signal. Transfer request signal.
In the case of the repeat transfer mode, two transfer requests are set at the start of the first transfer. Following the transmission/reception completion interrupt request (INTCSI0n), transfer is continued if the SIRBn register can be read within the next transfer reservation period. If the SIRBn register cannot be read, transfer ends and the SIRBn register does not receive the new value of the SIO0n register. The last data can be obtained by reading the SIO0n register following completion of the transfer.
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(2) Usage (transmission/reception) <1> Set the repeat transfer mode (AUTOn bit of CSIM0n register = 1) and the transmission/reception mode (TRMDn bit of CSIM0n register = 1) <2> Write the first data to the SOTBFn register. <3> Write the 2nd data to the SOTBn register (start transfer). <4> Wait for the transmission/reception completion interrupt request (INTCSI0n). <5> When the transmission/reception completion interrupt request (INTCSI0n) has been set (1), write the next data to the SOTBn register (reserve next transfer), and read the SIRBn register to load the receive data. <6> Repeat steps <4> and <5> as long as data to be sent remains. <7> Wait for the INTCSI0n interrupt. When the interrupt request signal is set (1), read the SIRBn register to load the (N - 1)th receive data (N: Number of transfer data). <8> Following the last transmission/reception completion interrupt request (INTCSI0n), read the SIO0n register to load the Nth (last) receive data.
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Figure 16-6. Repeat Transfer (Transmission/Reception) Timing Chart
SCK0n (I/O) SO0n (output) SI0n (input) SOTBFnL register SOTBnL register SIO0nL register SIRBnL register dout-1 dout-2 dout-3 dout-4 dout-5 din-5 din-1 SOTBn (d3) SIRBn (d1) din-2 din-3 SOTBn (d4) SIRBn (d2) din-4 SOTBn (d5) SIRBn (d3) SIRBn (d4) SIOn (d5) dout-1 din-1 dout-2 din-2 dout-3 din-3 dout-4 din-4 dout-5 din-5
SOTBFn (d1) Reg_WR SOTBn (d2) Reg_RD
CSOTn bit INTCSI0n interrupt rq_clr trans_rq <1> <2> <3> <4> <5> <4> <6> Period during which next transfer can be reserved <5> <4> <5> <7> <8>
Remarks 1. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) 2. Reg_WR: Internal signal. Reg_RD: Internal signal. This signal indicates that clocked serial interface transmit buffer This signal indicates that clocked serial interface receive buffer registers n and nL (SOTBn/SOTBnL) have been written. registers n and nL (SIRBn/SIRBnL) have been read. rq_clr: Internal signal. Transfer request clear signal. trans_rq: Internal signal. Transfer request signal.
In the case of the repeat transfer mode, two transfer requests are set at the start of the first transfer. Following the transmission/reception completion interrupt request (INTCSI0n), transfer is continued if the SOTBn register can be written within the next transfer reservation period. If the SOTBn register cannot be written, transfer ends and the SIRBn register does not receive the new value of the SIO0n register. The last receive data can be obtained by reading the SIO0n register following completion of the transfer.
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(3) Next transfer reservation period In the repeat transfer mode, the next transfer must be prepared with the period shown in Figure 16-7. Figure 16-7. Timing Chart of Next Transfer Reservation Period (1/2)
(a) When data length: 8 bits, operation mode: CKPn bit = 0, DAPn bit = 0
SCK0n (I/O)
INTCSI0n interrupt Reservation period: 7 SCK0n cycles
(b) When data length: 16 bits, operation mode: CKPn bit = 0, DAPn bit = 0
SCK0n (I/O)
INTCSI0n interrupt Reservation period: 15 SCK0n cycles
Remark
n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1)
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Figure 16-7. Timing Chart of Next Transfer Reservation Period (2/2)
(c) When data length: 8 bits, operation mode: CKPn bit = 0, DAPn bit = 1
SCK0n (I/O) INTCSI0n interrupt Reservation period: 6.5 SCK0n cycles
(d) When data length: 16 bits, operation mode: CKPn bit = 0, DAPn bit = 1
SCK0n (I/O) INTCSI0n interrupt Reservation period: 14.5 SCK0n cycles
Remark
n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1)
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(4) Cautions To continue repeat transfers, it is necessary to either read the SIRBn register or write to the SOTBn register during the transfer reservation period. If access is performed to the SIRBn register or the SOTBn register when the transfer reservation period is over, the following occurs. (i) In case of conflict between transfer request clear and register access Since request cancellation has higher priority, the next transfer request is ignored. Therefore, transfer is interrupted, and normal data transfer cannot be performed. Figure 16-8. Transfer Request Clear and Register Access Conflict
Transfer reservation period SCK0n (I/O) INTCSI0n interrupt
rq_clr
Reg_R/W
Remarks 1. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) 2. rq_clr: Internal signal. Transfer request clear signal. Reg_R/W: Internal signal. This signal indicates that a clocked serial interface receive buffer register n and nL (SIRBn/SIRBnL) read or clocked serial interface transmit buffer register n and nL (SOTBn/SOTBnL) write was performed.
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(ii) In case of conflict between interrupt request and register access Since continuous transfer has stopped once, executed as a new repeat transfer. In the slave mode, a bit phase error transfer error results (refer to Figure 16-9). In the transmission/reception mode, the value of the SOTBFn register is retransmitted, and illegal data is sent. Figure 16-9. Interrupt Request and Register Access Conflict
Transfer reservation period SCK0n (I/O) INTCSI0n interrupt
0
1
2
3
4
rq_clr
Reg_R/W
Remarks 1. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) 2. rq_clr: Internal signal. Transfer request clear signal. Reg_R/W: Internal signal. This signal indicates that a clocked serial interface receive buffer register n and nL (SIRBn/SIRBnL) read or clocked serial interface transmit buffer register n and nL (SOTBn/SOTBnL) write was performed.
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16.5 Output Pins
(1) SCK0n pin When the CSI0n operation is disabled (CSI0En bit of CSIM0n register = 0), the SCK0n pin output status is as follows. Table 16-1. SCK0n Pin Output Status
CKPn 0 1 CKS0n2 Don't care 1 CKS0n1 Don't care 1 CKS0n0 Don't care 1 SCK0n Pin Output Fixed to high level Fixed to high level Fixed to low level
Other than above
Remarks 1. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) 2. When any of the CKPn and CKS0n2 to CKS0n0 bits of the CSICn register is overwritten, the SCK0n pin output changes. (2) SO0n pin When the CSI0n operation is disabled (CSI0En bit of CSIM0n register = 0), the SO0n pin output status is as follows. Table 16-2. SO0n Pin Output Status
TRMDn 0 1 DAPn Don't care 0 1 AUTOn Don't care Don't care 0 CCLn Don't care Don't care 0 DIRn Don't care Don't care 0 1 1 0 1 1 0 0 1 1 0 1 SO0n Pin Output Fixed to low level SO latch value (low level) SOTBn7 bit value SOTBn0 bit value SOTBn15 bit value SOTBn0 bit value SOTBFn7 bit value SOTBFn0 bit value SOTBFn15 bit value SOTBFn0 bit value
Remarks 1. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) 2. When any of the TRMDn, CCLn, DIRn, and AUTOn bits of the CSIM0n register or DAPn bit of the CSICn register is overwritten, the SO0n pin output changes.
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The number of CSIA channels incorporated differs as follows depending on the product.
Product Name Number of channels V850ES/KF1 1 channel (CSIA0) V850ES/KG1 2 channels (CSIA0, CSIA1) V850ES/KJ1
17.1 Functions
CSIAn has the following three modes. * Operation stop mode * 3-wire serial I/O mode * 3-wire serial I/O mode with automatic transmit/receive function (1) Operation stop mode This mode is used when serial transfer is not performed and can enable a reduction in the power consumption. (2) 3-wire serial I/O mode (MSB/LSB-first selectable) This mode is used to transfer 8-bit data using three lines: a serial clock pin (SCKAn) and two serial data pins (SIAn and SOAn). The processing time of data transfer can be shortened in the 3-wire serial I/O mode because transmission and reception can be simultaneously executed. In addition, whether 8-bit data is transferred MSB or LSB first can be specified, so this interface can be connected to any device. (3) 3-wire serial I/O mode with automatic transmit/receive function (MSB/LSB-first selectable) This mode is used to transfer 8-bit data using three lines: a serial clock pin (SCKAn) and two serial data pins (SIAn and SOAn). The processing time of data transfer can be shortened in the 3-wire serial I/O mode because transmission and reception can be simultaneously executed. In addition, whether 8-bit data is transferred MSB or LSB first can be specified, so this interface can be connected to any device. Data can be transferred to/from a display driver etc. without using software since a 32-byte transfer buffer RAM is incorporated. * Master mode/slave mode selectable * Transfer data length: 8 bits * MSB/LSB-first selectable for transfer data * Automatic transmit/receive function: Number of transfer bytes can be specified between 1 and 32 Transfer interval can be specified (0 to 63 clocks) Single transfer/repeat transfer selectable * On-chip dedicated baud rate generator (6/8/16/32 divisions)
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* 3-wire SOAn: Serial data output SIAn: Serial data input SCKAn: Serial clock I/O * Transmission/reception completion interrupt: INTCSIAn * Internal 32-byte buffer RAM Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
17.2 Configuration
CSIAn consists of the following hardware. Table 17-1. Configuration of CSIAn
Item Register Configuration Serial I/O shift register An (SIOAn) Automatic data transfer address count register n (ADTCn) CSIAn buffer RAM (CSIAnBm, CSIAnBmL, CSIAnBmH) (m = 0 to F) Serial operation mode specification register n (CSIMAn) Serial status register n (CSISn) Serial trigger register n (CSITn) Divisor selection register n (BRGCAn) Automatic data transfer address point specification register n (ADTPn) Automatic data transfer interval specification register n (ADTIn)
Control registers
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Figure 17-1. Block Diagram of CSIAn
CHAPTER 17 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION
Buffer RAM
Automatic data transfer address point specification register n (ADTPn)
Automatic data transfer address count register n (ADTCn)
Internal bus
DIRn ATMn SIAn
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Serial trigger register n (CSITn)
Divisor selection register n (BRGCAn)
Serial I/O shift register An (SIOAn)
ATSTPn ATSTAn Serial status register n (CSISn) CKSAn1 CKSAn0 TSFn
RXEn SOAn TXEn 2 2 Serial clock counter Serial transfer controller SCKAn Interrupt generator INTCSIAn
Selector
fXX/6 to fXX/256
Selector
fXX
Automatic data transfer interval specification register n (ADTIn)
6-bit counter
MASTERn
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(1) Serial I/O shift register An (SIOAn) This is an 8-bit register used to store transmit/receive data in 1-byte transfer mode (ATEn bit of serial operation mode specification register n (CSIMAn) = 0). Writing transmit data to SIOAn starts the transfer. In addition, after a transfer completion interrupt request signal (INTCSIAn) is output TSFn bit of serial status register n (CSISn) = 0), data can be received by reading data from SIOAn. This register can be written or read by an 8-bit memory manipulation instruction. However, writing to the SIOAn register is prohibited when TSFn bit of serial status register n (CSISn) = 1 RESET input sets this register 00H. Cautions 1. A transfer operation is started by writing to SIOAn register. Consequently, when
transmission is disabled (TXEn bit of CSIMAn register = 0), write dummy data to the SIOAn register to start the transfer operation, and then perform a receive operation. 2. Do not write data to SIOAn while the automatic transmit/receive function is operating. Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) (2) Automatic data transfer address count register n (ADTCn) This is a register used to indicate buffer RAM addresses during automatic transfer. When automatic transfer is stopped, the data position when transfer stopped can be ascertained by reading ADTCn register value. This register can be set by an 8-bit memory manipulation instruction. RESET input sets this register to 00H. However, reading from ADTCn register is prohibited when TSFn bit of serial status register n (CSISn) = 1.
After reset: 00H 7 ADTCn
R 6
Address: FFFFFD47H, FFFFD57H 5 4 3 2 1 0 ADTCn0
ADTCn7 ADTCn6
ADTCn5 ADTCn4
ADTCn3 ADTCn2 ADTCn1
Remark
n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
17.3 Control Registers
Serial interface CSIAn is controlled by the following six registers. * Serial operation mode specification register n (CSIMAn) * Serial status register n (CSISn) * Serial trigger register n (CSITn) * Divisor selection register n (BRGCAn) * Automatic data transfer address point specification register n (ADTPn) * Automatic data transfer interval specification register n (ADTIn)
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(1) Serial operation mode specification register n (CSIMAn) This is an 8-bit register used to control the serial transfer operation. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H.
After reset: 00H <7> CSIMAn CSIAEn
R/W 6 ATEn
Address: FFFFFD40H, FFFFD50H 5 ATMn 4 MASTERn 3 TXEn 2 RXEn 1 DIRn 0 0
CSIAEn 0 1
CSIAn operation enable/disable control Disable CSIAn operation (SOAn: Low level, SCKAn: High level) Enable CSIAn operation
* When CSIAEn = 0, the CSIAn unit is reset asynchronously. * When CSIAEn = 0, the CSIAn unit is reset, so to operate CSIAn, first set CSIAEn = 1. * If the CSIAEn bit is changed from 1 to 0, all the registers of the CSIAn unit are initialized. To set CSIAEn to 1 again, first re-set the registers of the CSIAn unit. * If the CSIAEn bit is changed from 1 to 0, the buffer RAM value is not held. Also, when the CSIAEn bit is 0, the buffer RAM cannot be accessed. ATEn 0 1 ATMn 0 1 Automatic transfer operation enable/disable control 1-byte transfer mode Automatic transfer mode Specification of automatic transfer mode Single transfer mode (stops at address specified with ADTPn register) Repeat transfer mode (Following transfer completion, the ADTCn register is cleared to 00H and transmission starts again.) MASTERn 0 1 TXEn 0 1 Specification of CSIAn master/slave mode Slave mode (synchronized with SCKAn input clock) Master mode (synchronized with internal clock) Transmission enable/disable control Disable transmission (SOAn: Low level) Enable transmission
* When the TXEn bit is 0, read from the transfer buffer RAM is not possible. RXEn 0 1 Disable reception Enable reception Reception enable/disable control
* When the RXEn bit is 0, write to the transfer buffer RAM is not possible. DIRn 0 1 MSB first LSB first Specification of transfer data direction
Remark
n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
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(2) Serial status register n (CSISn) This is an 8-bit register used to select the input clock and to control the transfer operation of CSIAn. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. However, rewriting the CSISn register is prohibited when TSFn bit is 1.
After reset: 00H 7 CSISn
R/W 6
Address: FFFFFD41H, FFFFD51H 5 0 4 0 3 0 2 0 1 0 0 TSFn
CKSAn1 CKSAn0
CKSAn1 CKSAn0
Serial clock (fSCKA) selectionNote 20 MHz 16 MHz 10 MHz 100 ns 200 ns 400 ns 800 ns
0 0 1 1
0 1 0 1
fXX fXX/2 fXX/4 fXX/8
Setting prohibited Setting prohibited 100 ns 200 ns 400 ns 125 ns 250 ns 500 ns
Rewriting CSISn is prohibited when the CSIAEn bit of the CSIMAn register is 1. TSFn 0 Transfer status CSIAEn bit of CSIMAn register = 0 At reset input At completion of specified transfer When transfer has been suspended by setting ATSTPn bit of CSITn register to 1 1 From transfer start to completion of specified transfer
Note Set fSCKA so as to satisfy the following conditions. VDD = 4.0 to 5.5 V: fSCKA 10 MHz VDD = 2.7 to 4.0: fSCKA 5 MHz Cautions 1. The TSFn bit is read-only. 2. When the TSFn bit = 1, rewriting the CSIMAn, CSISn, BRGCAn, ADTPn, ADTIn, SIOAn registers is prohibited. However, the transfer buffer RAM can be rewritten. 3. When writing to bits 1 to 5, always write 0. Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
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(3) Serial trigger register n (CSITn) This is an 8-bit register used to control execution/stop of automatic data transfer. This register can be set by an 8-bit or 1-bit memory manipulation instruction. RESET input sets this register to 00H. However, manipulate only when the ATEn bit of serial operation mode specification register n (CSIMAn) is 1 (manipulation prohibited when ATEn bit = 0).
After reset: 00H 7 CSITn 0
R/W 6 0
Address: FFFFFD42H, FFFFD52H 5 0 4 0 3 0 2 0 <1> ATSTPn <0> ATSTAn
ATSTPn 0 1 Normal mode
Automatic data transfer suspension
Stop automatic data transfer
Even when ATSTPn = 1 is set, transfer does not stop until 1 byte has been transferred. 1 is held until immediately before the INTCSIAn interrupt signal is generated. After transfer has been interrupted, the data address at which transfer stopped is stored in the ADTCn register. Moreover, transfer cannot be resumed from the point where it has been stopped. ATSTAn 0 1 Normal mode Start automatic data transfer Automatic data transfer start
Even when ATSTAn = 1, automatic data transfer does not start until 1 byte has been transferred. 1 is held until immediately before the INTCSIAn interrupt signal is generated.
Remark
n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
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(4) Divisor selection register n (BRGCAn) This is an 8-bit register used to control the serial transfer speed (divisor of CSIA clock). This register can be set by an 8-bit memory manipulation instruction. However, when the TSFn bit of serial status register n (CSISn) is 1, rewriting the BRGCAn register is prohibited.
After reset: 03H 7 BRGCAn 0
R/W 6 0
Address: FFFFFD43H, FFFFD53H 5 0 4 0 3 0 2 0 1 0
BRGCn1 BRGCn0
BRGCn1 BRGCn0 0 0 1 1 0 1 0 1
Selection of CSIAn serial clock (fSCKA division ratio) 6 (fSCKA/6) 8 (fSCKA/8) 16 (fSCKA/16) 32 (fSCKA/32)
Remark
n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
(5) Automatic data transfer address point specification register n (ADTPn) This is an 8-bit register used to specify the buffer RAM address that ends transfer during automatic data transfer the ATEn bit of serial operation mode specification register n (CSIMAn) = 1). This register can be set by an 8-bit memory manipulation instruction. However, when the TSFn bit of serial status register n (CSISn) is 1, rewriting the ADTPn register is prohibited. In the V850ES/KF1, V850ES/KG1, and V850ES/KJ1, 00H to 1FH can be specified because 32 bytes of buffer RAM are incorporated. Example When the ADTPn register is set to 07H 8 bytes of 00H to 07H are transferred. In repeat transfer mode (ATMn bit of CSIMAn register = 1), transfer is performed repeatedly up to the address value set in ADTPn. Example When 07H is transferred to ADTPn (repeat transfer mode) Transfer is repeated as 00H to 07H, 00H to 07H, ... .
After reset: 00H 7 ADTPn 0
R/W 6 0
Address: FFFFFD44H, FFFFD54H 5 0 4 ADTPn4 3 2 1 ADTPn1 0 ADTPn0
ADTPn3 ADTPn2
Caution Remark
Be sure to set bits 5 to 7 to 0. n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
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The relationship between buffer RAM address values and the ADTPn register setting values is shown below. Table 17-2. Relationship Between Buffer RAM Address Values and ADTP0 Register Setting Values
Buffer RAM Address Value FE00H FE01H FE02H FE03H FE04H FE05H FE06H FE07H FE08H FE09H FE0AH FE0BH FE0CH FE0DH FE0EH FE0FH ADTP0 Register Setting Value 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH Buffer RAM Address Value FE10H FE11H FE12H FE13H FE14H FE15H FE16H FE17H FE18H FE19H FE1AH FE1BH FE1CH FE1DH FE1EH FE1FH ADTP0 Register Setting Value 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH
Table 17-3. Relationship Between Buffer RAM Address Values and ADTP1 Register Setting Values
Buffer RAM Address Value FE20H FE21H FE22H FE23H FE24H FE25H FE26H FE27H FE28H FE29H FE2AH FE2BH FE2CH FE2DH FE2EH FE2FH ADTP1 Register Setting Value 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH Buffer RAM Address Value FE30H FE31H FE32H FE33H FE34H FE35H FE36H FE37H FE38H FE39H FE3AH FE3BH FE3CH FE3DH FE3EH FE3FH
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ADTP1 Register Setting Value 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH
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(6) Automatic data transfer interval specification register n (ADTIn) This is an 8-bit register used to specify the interval period between 1-byte transfers during automatic data transfer (ATEn bit of serial operation mode specification register n (CSIMAn) = 1). Set this register when in master mode (MASTERn bit of CSIMAn register = 1) (setting is unnecessary in slave mode). Setting in 1-byte transfer mode (ATEn bit of CSIMAn = 0) is also valid. When the interval time specified by the ADTIn register after the end of 1-byte transfer has elapsed, an interrupt request signal (INTCSIAn) is output. The number of clocks for the interval can be set to between 0 and 63 clocks. The specified interval time is the transfer clock (specified by divisor selection register n (BRGCAn)) multiplied by an integer value.
Example When ADTIn register = 03H
SCKAn
Interval time of 3 clocks
This register can be set by an 8-bit memory manipulation instruction. However, when the TSFn bit of serial status register n (CSISn) is 1, rewriting the ADTIn register is prohibited.
After reset: 00H 7 ADTIn 0
R/W 6 0
Address: FFFFFD45H, FFFFD55H 5 ADTIn5 4 ADTIn4 3 ADTIn3 2 ADTIn2 1 ADTIn1 0 ADTIn0
Remark
n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
(7) CSIAn buffer RAM (CSIAnBm) This area holds transmit/receive data (up to 32 bytes) in automatic transfer mode in 1-bit units. The CSIAnBm register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the CSIAnBm register are used as the CSIAnBmH register and CSIAnBmL register, respectively, these registers can be read/written in 8-bit units. After automatic transfer is started, only data of the number of ADTPn register bytes is transmitted/received in sequence from the CSIAmB0L register. Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) m = 0 to F
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Table 17-4. CSIA0 Buffer RAM
Manipulatable Bits 8 16
Address FFFFFE00H FFFFFE00H FFFFFE01H FFFFFE02H FFFFFE02H FFFFFE03H FFFFFE04H FFFFFE04H FFFFFE05H FFFFFE06H FFFFFE06H FFFFFE07H FFFFFE08H FFFFFE08H FFFFFE09H FFFFFE0AH FFFFFE0AH FFFFFE0BH FFFFFE0CH FFFFFE0CH FFFFFE0DH FFFFFE0EH FFFFFE0EH FFFFFE0FH FFFFFE10H FFFFFE10H FFFFFE11H FFFFFE12H FFFFFE12H FFFFFE13H FFFFFE14H FFFFFE14H FFFFFE15H FFFFFE16H FFFFFE16H FFFFFE17H FFFFFE18H FFFFFE18H FFFFFE19H FFFFFE1AH FFFFFE1AH FFFFFE1BH FFFFFE1CH FFFFFE1CH FFFFFE1DH FFFFFE1EH FFFFFE1EH FFFFFE1FH
Symbol CSIA0B0 CSIA0B0L CSIA0B0H CSIA0B1 CSIA0B1L CSIA0B1H CSIA0B2 CSIA0B2L CSIA0B2H CSIA0B3 CSIA0B3L CSIA0B3H CSIA0B4 CSIA0B4L CSIA0B4H CSIA0B5 CSIA0B5L CSIA0B5H CSIA0B6 CSIA0B6L CSIA0B6H CSIA0B7 CSIA0B7L CSIA0B7H CSIA0B8 CSIA0B8L CSIA0B8H CSIA0B9 CSIA0B9L CSIA0B9H CSIA0BA CSIA0BAL CSIA0BAH CSIA0BB CSIA0BBL CSIA0BBH CSIA0BC CSIA0BCL CSIA0BCH CSIA0BD CSIA0BDL CSIA0BDH CSIA0BE CSIA0BEL CSIA0BEH CSIA0BF CSIA0BFL CSIA0BFH R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W
After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
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Table 17-5. CSIA1 Buffer RAM
Manipulatable Bits 8 16
Address FFFFFE20H FFFFFE20H FFFFFE21H FFFFFE22H FFFFFE22H FFFFFE23H FFFFFE24H FFFFFE24H FFFFFE25H FFFFFE26H FFFFFE26H FFFFFE27H FFFFFE28H FFFFFE28H FFFFFE29H FFFFFE2AH FFFFFE2AH FFFFFE2BH FFFFFE2CH FFFFFE2CH FFFFFE2DH FFFFFE2EH FFFFFE2EH FFFFFE2FH FFFFFE30H FFFFFE30H FFFFFE31H FFFFFE32H FFFFFE32H FFFFFE33H FFFFFE34H FFFFFE34H FFFFFE35H FFFFFE36H FFFFFE36H FFFFFE37H FFFFFE38H FFFFFE38H FFFFFE39H FFFFFE3AH FFFFFE3AH FFFFFE3BH FFFFFE3CH FFFFFE3CH FFFFFE3DH FFFFFE3EH FFFFFE3EH FFFFFE3F
Symbol CSIA1B0 CSIA1B0L CSIA1B0H CSIA1B1 CSIA1B1L CSIA1B1H CSIA1B2 CSIA1B2L CSIA1B2H CSIA1B3 CSIA1B3L CSIA1B3H CSIA1B4 CSIA1B4L CSIA1B4H CSIA1B5 CSIA1B5L CSIA1B5H CSIA1B6 CSIA1B6L CSIA1B6H CSIA1B7 CSIA1B7L CSIA1B7H CSIA1B8 CSIA1B8L CSIA1B8H CSIA1B9 CSIA1B9L CSIA1B9H CSIA1BA CSIA1BAL CSIA1BAH CSIA1BB CSIA1BBL CSIA1BBH CSIA1BC CSIA1BCL CSIA1BCH CSIA1BD CSIA1BDL CSIA1BDH CSIA1BE CSIA1BEL CSIA1BEH CSIA1BF CSIA1BFL CSIA1BFH R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W
After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Remark
V850ES/KG1, V850ES/KJ1 only
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17.4 Operation
CSIAn can be used in the following three modes. * Operation stop mode * 3-wire serial I/O mode * 3-wire serial I/O mode with automatic transmit/receive function 17.4.1 Operation stop mode Serial transfer is not executed in this mode. Therefore, the power consumption can be reduced. (1) Register setting The operation stop mode is set by serial operation mode specification register n (CSIMAn). (a) Serial operation mode specification register n (CSIMAn) This is an 8-bit register used to control the serial transfer operation. This register can be set by an 8-bit or 1-bit memory manipulation instruction. RESET input sets this register to 00H.
After reset: 00H <7> CSIMAn CSIAEn
R/W 6 ATEn
Address: FFFFFD40H, FFFFD50H 5 ATMn 4 MASTERn 3 TXEn 2 RXEn 1 DIRn 0 0
CSIAEn 0 1
CSIAn operation enable/disable control Disable CSIAn operation (SOAn: Low level, SCKAn: High level) Enable CSIAn operation
17.4.2 3-wire serial I/O mode The one-byte data transmission/reception is executed in the mode in which the ATEn bit of serial operation mode specification register n (CSIMAn) is set to 0. In this mode, communication is executed by using three lines: serial clock (SCKAn), serial data output (SOAn), and serial data input (SIAn) pins. (1) Register setting CSIAn is controlled by the following three registers. * Serial operation mode specification register n (CSIMAn) * Serial status register n (CSISn) * Divisor selection register n (BRGCAn)
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(a) Serial operation mode specification register n (CSIMAn) This is an 8-bit register used to control the serial transfer operation. This register can be set by an 8-bit or 1-bit memory manipulation instruction. RESET input sets this register to 00H.
After reset: 00H <7> CSIMAn CSIAEn
R/W 6 ATEn
Address: FFFFFD40H, FFFFD50H 5 ATMn 4 MASTERn 3 TXEn 2 RXEn 1 DIRn 0 0
CSIAEn 0 1
CSIAn operation enable/disable control Disable CSIAn operation (SOAn: Low level, SCKAn: High level) Enable CSIAn operation
* When CSIAEn = 0, the CSIAn unit is reset asynchronously. * When CSIAEn = 0, the CSIAn unit is reset, so to operate CSIAn, first set CSIAEn = 1. * If the CSIAEn bit is changed from 1 to 0, all the registers of the CSIAn unit are initialized. To set CSIAEn to 1 again, first re-set the registers of the CSIAn unit. * If the CSIAEn bit is changed from 1 to 0, the buffer RAM value is not held. Also, when the CSIAEn bit is 0, the buffer RAM cannot be accessed. ATEn 0 1 ATMn 0 1 Automatic transfer operation enable/disable control 1-byte transfer mode Automatic transfer mode Specification of automatic transfer mode Single transfer mode (stops at address specified with ADTPn register) Repeat transfer mode (Following transfer completion, the ADTCn register is cleared to 00H and transmission starts again.) MASTERn 0 1 TXEn 0 1 Specification of CSIAn master/slave mode Slave mode (synchronized with SCKAn input clock) Master mode (synchronized with internal clock) Transmission enable/disable control Disable transmission (SOAn: Low level) Enable transmission
* When the TXEn bit is 0, read from the transfer buffer RAM is not possible. RXEn 0 1 Disable reception Enable reception Reception enable/disable control
* When the RXEn bit is 0, write to the transfer buffer RAM is not possible. DIRn 0 1 MSB first LSB first Specification of transfer data direction
Remark
n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
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(b) Serial status register n (CSISn) This is an 8-bit register used to select the input clock and to control the transfer operation of CSIAn. This register can be set by an 8-bit or 1-bit memory manipulation instruction. RESET input sets this register to 00H. However, rewriting the CSISn register is prohibited when the TSFn bit is 1.
After reset: 00H 7 CSISn
R/W 6
Address: FFFFFD41H, FFFFD51H 5 0 4 0 3 0 2 0 1 0 0 TSFn
CKSAn1 CKSAn0
CKSAn1 CKSAn0
Serial clock (fSCKA) selectionNote 20 MHz 16 MHz 10 MHz 100 ns 200 ns 400 ns 800 ns
0 0 1 1
0 1 0 1
fXX fXX/2 fXX/4 fXX/8
Setting prohibited Setting prohibited 100 ns 200 ns 400 ns 125 ns 250 ns 500 ns
Rewriting CSISn is prohibited when the CSIAEn bit of the CSIMAn register is 1. TSFn 0 Transfer status CSIAEn bit of CSIMAn register = 0 At reset input At completion of specified transfer When transfer has been suspended by setting ATSTPn bit of CSITn register to 1 1 From transfer start to completion of specified transfer
Note Set fSCKA so as to satisfy the following conditions. VDD = 4.0 to 5.5 V: fSCKA 10 MHz VDD = 2.7 to 4.0: fSCKA 5 MHz Cautions 1. The TSFn bit is read-only. 2. When the TSFn bit = 1, rewriting the CSIMAn, CSISn, BRGCAn, ADTPn, ADTIn, SIOAn registers is prohibited. However, the transfer buffer RAM can be rewritten. 3. When writing to bits 1 to 5, always write 0. Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
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(c) Divisor selection register n (BRGCAn) This is an 8-bit register used to control the serial transfer speed (divisor of CSIA input clock). This register can be set by an 8-bit memory manipulation instruction. However, when the TSFn bit of serial status register n (CSISn) is 1, rewriting the BRGCAn register is prohibited.
After reset: 03H 7 BRGCAn 0
R/W 6 0
Address: FFFFFD43H, FFFFD53H 5 0 4 0 3 0 2 0 1 0
BRGCn1 BRGCn0
BRGCn1 BRGCn0 0 0 1 1 0 1 0 1
Selection of CSIAn serial clock (fSCKA division ratio) 6 (fSCKA/6) 8 (fSCKA/8) 16 (fSCKA/16) 32 (fSCKA/32)
Remark
n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
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V850ES/KF1, V850ES/KG1, V850ES/KJ1
CSIAE0 MASTER0 P53 PM53 PFC53 PMC53 P54 PM54 PFC54 PF5Note 4 PMC54 P55 PM55 PFC55 PF55Note 4 PMC55 Serial I/O Shift Serial Clock Counter SIA0/P53 Pin Function P53/RTP03/ KR3 1 0 x
Note 3
SOA0/P54 Pin Function P54/RTP04/ KR4 SOA0
Note 3
SCKA0/P55 Pin Function P55/RTP05/ KR5 SCKA0 (input)
CHAPTER 17 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION
Register A0 Operation Operation Control 0Note 1 x x x x x x x x x x x x x x x x x x x x x x Operation stopped Clear
Note 3
0
Note 3
1
Note 3
Note 2
Note 2
0
Note 2
Note 2
1
Note 2
0
1
Operation enabled Count operation
SIA0
Note 2
1
SCKA0 (output)
V850ES/KG1, V850ES/KJ1
CSIAE1 MASTER1 P910 PM910 PFC910 PMC910 P911 PM911 PFC911 PF911Note 4 PMC911 P912 PM912 PFC912 PF912Note 4 PMC912 Serial I/O Shift Serial Clock Counter SIA1/P910 Pin Function P910/A10 SIA1
Note 2
SOA1/P911 Pin Function P911/A11 SOA1
Note 3
SCKA1/P912 Pin Function P912/A12 SCKA1 (input)
Register A1 Operation Operation Control 0Note 1 1 x 0 x x
Note 3
x x
Note 3
x 1
Note 3
x 1
Note 3
x x
Note 2
x x
Note 2
x 1
Note 2
x x
Note 2
x 1
Note 2
x x
x x
x 1
x x
x 1
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Operation stopped
Clear
Operation enabled Count operation
1
SCKA1 (output)
Notes 1. This pin can be used for a port function or an alternate function other than the serial communication pin. 2. This pin can be used for a port function or an alternate function other than the serial communication pin only during transmission (RXEn bit = 0, TXEn bit = 1). However, the P910 to P912 pins cannot be used as the A10 to A11 pins. 3. This pin can be used for a port function or an alternate function other than the serial communication pin only during reception (RXEn bit = 1, TXEn bit = 0). However, the P910 to P912 pins cannot be used as the A10 to A11 pins. 4. When this pin is used as an alternate function as an N-ch open-drain, set as follows. P5n: P5n bit = 1 PF5n bit = 1 PMC5n bit = 1 P9n: P9n bit = 1 PFC9n bit = 1 PF9n bit = 1 PMC9n bit = 1 Remark x: CSIAEn: Don't care Bit 7 of serial operation mode specification register n (CSIMAn)
MASTERn: Bit 4 of CSIMAn register PMxx: PMxx bit of port mode register PMCxx: PFCxx: Pxx: PMCxx bit of port mode control register PFCxx bit of port function control register Port output latch
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(3) 1-byte transmission/reception communication operation (a) 1-byte transmission/reception When the CSIAEn bit and ATEn bit of serial operation mode specification register n (CSIMAn) = 1, 0, respectively, if transfer data is written to serial I/O shift register An (SIOAn), the data is output via the SOA0 pin in synchronization with the SCKAn pin falling edge, and then input via the SIAn pin in synchronization with serial clock falling edge, and stored in the SIOAn register in synchronization with the rising edge 1 clock later. Data transmission and data reception can be performed simultaneously. If only reception is to be performed, transfer can only be started by writing a dummy value to the SIOAn register. When transfer of 1 byte is complete, an interrupt request signal (INTCSIAn) is generated. In 1-byte transmission/reception, the setting of the ATMn bit of CSIMAn is invalid. Be sure to read data after confirming that the TSFn bit of serial status register n (CSISn) = 0. Figure 17-2. 3-Wire Serial I/O Mode Timing
SCKAn
1
2
3
4
5
6
7
8
SIAn
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SOAn
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
CSIAFn End of transfer Transfer starts at falling edge of SCKAn pin SIOAn write
Caution
The SOAn pin becomes low level by an SIOAn write.
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(b) Data format In the data format, data is changed in synchronization with the SCKAn pin falling edge as shown below. The data length is fixed to 8 bits and the data transfer direction can be switched by the specification of the DIRn bit of serial operation mode specification register n (CSIMAn). Figure 17-3. Format of Transmit/Receive Data
(a) MSB-first (DIRn bit = 0)
SCKA0 SIA0 SOA0 DO7 DI7 DO6 DI6 DO5 DI5 DO4 DI4 DO3 DI3 DO2 DI2 DO1 DI1 DO0 DI0
(b) LSB-first (DIRn bit = 1)
SCKA0 SIA0 SOA0 DO0 DI0 DO1 DI1 DO2 DI2 DO3 DI3 DO4 DI4 DO5 DI5 DO6 DI6 DO7 DI7
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(c) Switching MSB/LSB as start bit Figure 17-4 shows the configuration of serial I/O shift register n (SIOAn) and the internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form. Switching MSB/LSB as the start bit can be specified using the DIRn bit of serial operation mode specification register n (CSIMAn). Start bit switching is realized by switching the bit order for data written to SIOAn. The SIOAn shift order remains unchanged. Thus, switching between MSB-first and LSB-first must be performed before writing data to the shift register. Figure 17-4. Transfer Bit Order Switching Circuit
7 6 Internal bus 1 0 LSB-first MSB-first Read/write gate Read/write gate
SOAn latch SIAn Shift register n (SIOAn) D Q
SOAn
SCKAn
(d) Transfer start Serial transfer is started by setting transfer data to serial I/O shift register n (SIOAn) when the following two conditions are satisfied. * Serial interface CSIAn operation control bit (CSIAEn) = 1 * Internal serial clock is stopped or SCKAn pin is high level after 8-bit serial transfer. Caution If CSIAEn is set to 1 after data is written to SIOAn, transfer does not start.
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request signal (INTCSIAn) is generated. Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
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17.4.3 3-wire serial I/O mode with automatic transmit/receive function Up to 32 bytes of data can be transmitted/received without using software in the mode in which the ATEn bit of serial operation mode specification register n (CSIMAn) is set to 1. After transfer is started, only data of the set number of bytes stored in RAM in advance can be transmitted, and only data of the set number of bytes can be received and stored in RAM. (1) Register setting Serial interface CSIAn is controlled by the following six registers. * Serial operation mode specification register n (CSIMAn) * Serial status register n (CSISn) * Serial trigger register n (CSITn) * Divisor selection register n (BRGCAn) * Automatic data transfer address point specification register n (ADTPn) * Automatic data transfer interval specification register n (ADTIn)
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(a) Serial operation mode specification register n (CSIMAn) This is an 8-bit register used to control the serial transfer operation. This register can be set by an 8-bit or 1-bit memory manipulation instruction. RESET input sets this register to 00H.
After reset: 00H <7> CSIMAn CSIAEn
R/W 6 ATEn
Address: FFFFFD40H, FFFFD50H 5 ATMn 4 MASTERn 3 TXEn 2 RXEn 1 DIRn 0 0
CSIAEn 0 1
CSIAn operation enable/disable control Disable CSIAn operation (SOAn: Low level, SCKAn: High level) Enable CSIAn operation
* When CSIAEn = 0, the CSIAn unit is reset asynchronously. * When CSIAEn = 0, the CSIAn unit is reset, so to operate CSIAn, first set CSIAEn = 1. * If the CSIAEn bit is changed from 1 to 0, all the registers of the CSIAn unit are initialized. To set CSIAEn to 1 again, first re-set the registers of the CSIAn unit. * If the CSIAEn bit is changed from 1 to 0, the buffer RAM value is not held. Also, when the CSIAEn bit is 0, the buffer RAM cannot be accessed. ATEn 0 1 ATMn 0 1 Automatic transfer operation enable/disable control 1-byte transfer mode Automatic transfer mode Specification of automatic transfer mode Single transfer mode (stops at address specified with ADTPn register) Repeat transfer mode (Following transfer completion, the ADTCn register is cleared to 00H and transmission starts again.) MASTERn 0 1 TXEn 0 1 Specification of CSIAn master/slave mode Slave mode (synchronized with SCKAn input clock) Master mode (synchronized with internal clock) Transmission enable/disable control Disable transmission (SOAn: Low level) Enable transmission
* When the TXEn bit is 0, read from the transfer buffer RAM is not possible. RXEn 0 1 Disable reception Enable reception Reception enable/disable control
* When the RXEn bit is 0, write to the transfer buffer RAM is not possible. DIRn 0 1 MSB first LSB first Specification of transfer data direction
Remark
n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
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(b) Serial status register n (CSISn) This is an 8-bit register used to select the input clock and to control the transfer operation of CSIAn. This register can be set by an 8-bit or 1-bit memory manipulation instruction. RESET input sets this register to 00H. However, rewriting the CSISn register is prohibited when the TSFn bit is 1.
After reset: 00H 7 CSISn
R/W 6
Address: FFFFFD41H, FFFFD51H 5 0 4 0 3 0 2 0 1 0 0 TSFn
CKSAn1 CKSAn0
CKSAn1 CKSAn0
Serial clock (fSCKA) selectionNote 20 MHz 16 MHz 10 MHz 100 ns 200 ns 400 ns 800 ns
0 0 1 1
0 1 0 1
fXX fXX/2 fXX/4 fXX/8
Setting prohibited Setting prohibited 100 ns 200 ns 400 ns 125 ns 250 ns 500 ns
Rewriting CSISn is prohibited when the CSIAEn bit of the CSIMAn register is 1. TSFn 0 Transfer status CSIAEn bit of CSIMAn register = 0 At reset input At completion of specified transfer When transfer has been suspended by setting ATSTPn bit of CSITn register to 1 1 From transfer start to completion of specified transfer
Note Set fSCKA so as to satisfy the following conditions. VDD = 4.0 to 5.5 V: fSCKA 10 MHz VDD = 2.7 to 4.0: fSCKA 5 MHz Cautions 1. The TSFn bit is read-only. 2. When the TSFn bit = 1, rewriting the CSIMAn, CSISn, BRGCAn, ADTPn, ADTIn, SIOAn registers is prohibited. However, the transfer buffer RAM can be rewritten. 3. When writing to bits 1 to 5, always write 0. Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
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(c) Serial trigger register n (CSITn) This is an 8-bit register used to control execution/stop of automatic data transfer. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. However, manipulate only when the ATEn bit of serial operation mode specification register n (CSIMAn) is 1 (manipulation prohibited when ATEn bit = 0).
After reset: 00H 7 CSITn 0
R/W 6 0
Address: FFFFFD42H, FFFFD52H 5 0 4 0 3 0 2 0 <1> ATSTPn <0> ATSTAn
ATSTPn 0 1 Normal mode
Automatic data transfer suspension
Stop automatic data transfer
Even when ATSTPn = 1 is set, transfer does not stop until 1 byte has been transferred. 1 is held until immediately before the INTCSIAn interrupt signal is generated. After transfer has been interrupted, the data address at which transfer stopped is stored in the ADTCn register. Moreover, transfer cannot be resumed from the point where it has been stopped. ATSTAn 0 1 Normal mode Start automatic data transfer Automatic data transfer start
Even when ATSTAn = 1, automatic data transfer does not start until 1 byte has been transferred. 1 is held until immediately before the INTCSIAn interrupt signal is generated.
Remark
n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
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(d) Divisor selection register n (BRGCAn) This is an 8-bit register used to control the serial transfer speed (divisor of CSIA input clock). This register can be set by an 8-bit memory manipulation instruction. However, when the TSFn bit of serial status register n (CSISn) is 1, rewriting the BRGCAn register is prohibited.
After reset: 03H 7 BRGCAn 0
R/W 6 0
Address: FFFFFD43H, FFFFD53H 5 0 4 0 3 0 2 0 1 0
BRGCn1 BRGCn0
BRGCn1 BRGCn0 0 0 1 1 0 1 0 1
Selection of CSIAn serial clock (fSCKA division ratio) 6 (fSCKA/6) 8 (fSCKA/8) 16 (fSCKA/16) 32 (fSCKA/32)
Remark
n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
(e) Automatic data transfer address point specification register n (ADTPn) This is an 8-bit register used to specify the buffer RAM address that ends transfer during automatic data transfer (ATEn bit of serial operation mode specification register n (CSIMAn) = 1). This register can be set by an 8-bit memory manipulation instruction. However, when the TSFn bit of serial status register n (CSISn) is 1, rewriting the ADTPn register is prohibited. In the V850ES/KF1, V850ES/KG1, and V850ES/KJ1, 00H to 1FH can be specified because 32 bytes of buffer RAM are incorporated. Example When the ADTPn register is set to 07H 8 bytes of 00H to 07H are transferred. In repeat transfer mode (ATMn bit of CSIMAn register = 1), transfer is performed repeatedly up to the address value set in ADTPn register. Example When 07H is transferred to the ADTPn register (repeat transfer mode) Transfer is repeated as 00H to 07H, 00H to 07H, ... .
After reset: 00H 7 ADTPn 0
R/W 6 0
Address: FFFFFD44H, FFFFD54H 5 0 4 ADTPn4 3 2 1 ADTPn1 0 ADTPn0
ADTPn3 ADTPn2
Caution Remark
Be sure to set bits 5 to 7 to 0. n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
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The relationship between buffer RAM address values and the ADTPn register setting values is shown below. Table 17-6. Relationship Between Buffer RAM Address Values and ADTP0 Register Setting Values
Buffer RAM Address Value FE00H FE01H FE02H FE03H FE04H FE05H FE06H FE07H FE08H FE09H FE0AH FE0BH FE0CH FE0DH FE0EH FE0FH ADTP0 Register Setting Value 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH Buffer RAM Address Value FE10H FE11H FE12H FE13H FE14H FE15H FE16H FE17H FE18H FE19H FE1AH FE1BH FE1CH FE1DH FE1EH FE1FH ADTP0 Register Setting Value 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH
Table 17-7. Relationship Between Buffer RAM Address Values and ADTP1 Register Setting Values
Buffer RAM Address Value FE20H FE21H FE22H FE23H FE24H FE25H FE26H FE27H FE28H FE29H FE2AH FE2BH FE2CH FE2DH FE2EH FE2FH ADTP1 Register Setting Value 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH Buffer RAM Address Value FE30H FE31H FE32H FE33H FE34H FE35H FE36H FE37H FE38H FE39H FE3AH FE3BH FE3CH FE3DH FE3EH FE3FH
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ADTP1 Register Setting Value 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH
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(f) Automatic data transfer interval specification register n (ADTIn) This is an 8-bit register used to specify the interval period between 1-byte transfers during automatic data transfer (ATEn bit of serial operation mode specification register n (CSIMAn) = 1). Set this register when in master mode (MASTERn bit of CSIMAn = 1) (setting is unnecessary in slave mode). Setting in 1-byte transfer mode (ATEn bit of CSIMAn = 0) is also valid. When the interval time specified by the ADTIn register after the end of 1-byte transfer has elapsed, an interrupt request signal (INTCSIAn) is output. The number of clocks for the interval can be set to between 0 and 63 clocks. The specified interval time is the transfer clock (specified by divisor selection register n (BRGCAn)) multiplied by an integer value.
Example When ADTIn register = 03H
SCKAn
Interval time of 3 clocks
This register can be set by an 8-bit memory manipulation instruction. However, when the TSFn bit of serial status register n (CSISn) is 1, rewriting the ADTIn register is prohibited.
After reset: 00H 7 ADTIn 0
R/W 6 0
Address: FFFFFD45H, FFFFD55H 5 ADTIn5 4 ADTIn4 3 ADTIn3 2 ADTIn2 1 ADTIn1 0 ADTIn0
Remark
n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
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(2) Automatic transmit/receive data setting (a) Transmit data setting <1> Write transmit data from the least significant address FA00H of buffer RAM (up to FA1FH at maximum). The transmit data should be in the order from lower address to higher address. <2> Set the automatic data transfer address point specification register n (ADTPn) to the value obtained by subtracting 1 from the number of transmit data bytes. (b) Automatic transmission/reception mode setting <1> Set the CSIAEn bit and ATEn bit of serial operating mode specification register n (CSIMAn) to 1. <2> Set the RXEn bit and TXEn bit of the CSIMAn register to 1. <3> Set a data transfer interval in automatic data transfer interval specification register n (ADTIn). <4> Set the ATSTAn bit of serial trigger register n (CSITn) to 1. The following operations are automatically carried out when (a) and (b) are carried out. * After the buffer RAM data indicated by automatic data transfer address count register n (ADTCn) is transferred to the SIOAn register, transmission is carried out (start of automatic transmission/reception). * The received data is written to the buffer RAM address indicated by the ADTCn register. * ADTCn register is incremented and the next data transmission/reception is carried out. Data transmission/reception continues until the ADTCn register incremental output matches the set value of automatic data transfer address point specification register n (ADTPn) (end of automatic transmission/reception). However, if the ATMn bit of CSIMAn is set to 1 (repeat mode), the ADTCn register is cleared after a match between the ADTPn and ADTCn registers, and then repeated transmission/reception is started. * When automatic transmission/reception is terminated, the TSFn bit is cleared to 0. Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) (3) Automatic transmission/reception communication operation (a) Automatic transmission/reception mode Automatic transmission/reception can be performed using buffer RAM. The data stored in the buffer RAM is output from the SOAn pin via the SIOAn register in synchronization with the SCKAn pin falling edge by performing (a) and (b) in (3) Automatic transmit/receive data setting. The data is then input from the SIAn pin via the SIOAn register in synchronization with the serial clock falling edge and the receive data is stored in the buffer RAM in synchronization with the rising edge 1 clock later. Data transfer ends if the TSFn bit of serial status register n (CSISn) is set to 1 when any of the following conditions is met.
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* Reset by setting the CSIAEn bit of the CSIMAn register to 0 * Transfer of 1 byte is complete by setting the ATSTPn bit of the CSITn register to 1 * Transfer of the range specified by the ADTPn register is complete At this time, an interrupt request signal (INTCSIAn) is generated except when the CSIAEn bit = 0. If a transfer is terminated in the middle, transfer starting from the remaining data is not possible. Read automatic data transfer address count register n (ADTCn) to confirm how much of the data has already been transferred, set the transfer data again, and then re-execute transfer. Figure 17-5 shows the operation timing in automatic transmission/reception mode and Figure 17-6 shows the operation flowchart. Figure 17-7 shows the operation of internal buffer RAM when 6 bytes of data are transmitted/received. Figure 17-5. Automatic Transmission/Reception Mode Operation Timings
Interval SCKAn SOAn SIAn D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
CSIAFn TSFn
Cautions 1. Because, in the automatic transmission/reception mode, the automatic transmit/receive function writes/reads data to/from the internal buffer RAM after 1-byte transmission/reception, an interval is inserted until the next transmission/reception. As the buffer RAM write/read is performed at the same time as CPU processing, the interval is dependent upon the value of automatic data transfer interval specification register n (ADTIn) (see (4) Automatic transmit/receive interval time). 2. When the TSFn bit is cleared, the SOAn pin becomes low level. Remarks 1. CSIAFn: Interrupt request flag TSFn: Bit n of serial status register n (CSISn) 2. n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
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Figure 17-6. Automatic Transmission/Reception Mode Flowchart
Start
Write transmit data in internal buffer RAM
Set ADTPn to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes
Software execution
Set the transmission/reception operation interval time in ADTIn
Set ATSTAn to 1
Write transmit data from internal buffer RAM to SIOAn
Transmission/reception operation
Increment pointer value
Hardware execution Write receive data from SIOAn to internal buffer RAM
ADTPn = ADTCn
No
Yes
TSFn = 0
No Software execution
Yes End
ADTPn: ADTIn: ATSTAn: SIOAn: ADTCn: TSFn:
Automatic data transfer address point specification register n Automatic data transfer interval specify register n Bit 0 of serial trigger register n (CSITn) Serial I/O shift register n Automatic data transfer address count register n Bit 0 of serial status register n (CSISn)
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In 6-byte transmission/reception (ATMn bit = 0, RXEn bit = 1, TXEn bit = 1 in the CSIMAn register) in automatic transmission/reception mode, internal buffer RAM operates as follows. (i) Before transmission/reception (see Figure 17-7 (a).) When the ATSTAn bit of serial trigger register n (CSITn) is set to 1, transmit data 1 (T1) is transferred from the internal buffer RAM to SIOAn. When transmission of the first byte is completed, receive data 1 (R1) is transferred from SIOAn to the buffer RAM, and automatic data transfer address count register n (ADTCn) is incremented. Then transmit data 2 (T2) is transferred from the internal buffer RAM to SIOAn. (ii) 4th byte transmission/reception point (see Figure 17-7 (b).) Transmission/reception of the third byte is completed, and transmit data 4 (T4) is transferred from the internal buffer RAM to the SIOAn register. When transmission of the fourth byte is completed, the receive data 4 (R4) is transferred from the SIOAn register to the internal buffer RAM, and the ADTCn register is incremented. (iii) Completion of transmission/reception (see Figure 17-7 (c).) When transmission of the sixth byte is completed, receive data 6 (R6) is transferred from SIOAn register to the internal buffer RAM, and the interrupt request flag (CSIAFn) is set (INTCSIAn generation). Figure 17-7. Internal Buffer RAM Operation in 6-Byte Transmission/Reception (in Automatic Transmission/Reception Mode) (1/2)
(a) Before transmission/reception
FA1FH
FA05H
Transmit data 6 (T6) Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) Transmit data 2 (T2) +1
Receive data 1 (R1)
SIOAn
5
ADTPn
0
ADTCn
FA00H
Transmit data 1 (T1)
0
CSIAFn
Remark
n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
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Figure 17-7. Internal Buffer RAM Operation in 6-Byte Transmission/Reception (in Automatic Transmission/Reception Mode) (2/2)
(b) 4th byte transmission/reception
FA1FH
FA05H
Receive data 6 (R6) Receive data 5 (R5) Receive data 4 (R4) Transmit data 3 (T3) Transmit data 2 (T2) +1
Receive data 4 (R4)
SIOAn
5
ADTPn
3
ADTCn
FA00H
Transmit data 1 (T1)
0
CSIAFn
(c) Completion of transmission/reception
FA1FH
FA05H
Receive data 6 (R6) Receive data 5 (R5) Receive data 4 (R4) Receive data 3 (R3) Receive data 2 (R2) 5
SIOAn ADTPn
5
ADTCn
FA00H
Receive data 1 (R1)
1
CSIAFn
Remark
n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
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(b) Automatic transmission mode In this mode, the specified number of 8-bit unit data are transmitted. Serial transfer is started when the ATSTAn bit of serial trigger register n (CSITn) is set to 1 while the CSIAEn, ATEn, and TXEAn bits of serial operating mode specification register n (CSIMAn) are set to 1. When the final byte has been transmitted, an interrupt request flag (CSIAFn) is set. However, judge the termination of automatic transmission and reception, not by the INTCSIAn signal but by the TSFn bit of serial status register n (CSISn). Figure 17-8 shows the automatic transmission mode operation timing, and Figure 17-9 shows the operation flowchart. Figure 17-10 shows the operation of the internal buffer RAM when 6 bytes of data are transmitted or received. Figure 17-8. Automatic Transmission Mode Operation Timing
Interval SCKAn SOAn CSIAFn TSFn D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Cautions 1. Because, in the automatic transmission mode, the automatic transmit/receive function reads data from the internal buffer RAM after 1-byte transmission, an interval is inserted until the next transmission. As the buffer RAM read is performed at the same time as CPU processing, the interval is dependent upon the value of automatic data transfer interval specification register n (ADTIn) (see (6) Automatic transmit/receive interval time). 2. When the TSFn bit is cleared, the SOAn pin becomes low level. Remarks 1. CSIAFn: Interrupt request flag TSFn: Bit 0 of serial status register n (CSISn) 2. n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
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Figure 17-9. Automatic Transmission Mode Flowchart
Start
Write transmit data in internal buffer RAM
Set ADTPn to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes
Software execution
Set the transmission/reception operation interval time in ADTIn
Set ATSTAn to 1
Write transmit data from internal buffer RAM to SIOAn
Increment pointer value
Transmission operation Hardware execution
ADTPn = ADTCn
No
Yes
TSFn = 0
No Software execution
Yes End
ADTPn: ADTIn: ATSTAn: SIOAn: ADTCn: TSFn: Remark
Automatic data transfer address point specification register n Automatic data transfer interval specification register n Bit 0 of serial trigger register n (CSITn) Serial I/O shift register n Automatic data transfer address count register n Bit 0 of serial status register n (CSISn)
n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
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In 6-byte transmission (ATMn = 0, RXEn bit = 0, TXEn bit = 1, ATE0 bit = 1) in automatic transmission mode, internal buffer RAM operates as follows. (i) Before transmission (see Figure 17-10 (a).) When the ATSTAn bit of serial trigger register n (CSITn) is set to 1, transmit data 1 (T1) is transferred from the internal buffer RAM to SIOAn. When transmission of the first byte is completed, automatic data transfer address count register n (ADTCn) is incremented. Then transmit data 2 (T2) is transferred from the internal buffer RAM to the SIOAn register. (ii) 4th byte transmission point (see Figure 17-10 (b).) Transmission of the third byte is completed, and transmit data 4 (T4) is transferred from the internal buffer RAM to the SIOAn register. When transmission of the fourth byte is completed, the ADTCn register is incremented. (iii) Completion of transmission (see Figure 17-10 (c).) When transmission of the sixth byte is completed, the interrupt request flag (CSIAFn) is set (INTCSIAn signal generation). Figure 17-10. Internal Buffer RAM Operation in 6-Byte Transmission (in Automatic Transmission Mode) (1/2)
(a) Before transmission
FA1FH
FA05H
Transmit data 6 (T6) Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) Transmit data 2 (T2) +1 5
SIOAn
ADTPn
0
ADTCn
FA00H
Transmit data 1 (T1)
0
CSIAFn
Remark
n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
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Figure 17-10. Internal Buffer RAM Operation in 6-Byte Transmission (in Automatic Transmission Mode) (2/2)
(b) 4th byte transmission point
FA1FH
FA05H
Transmit data 6 (T6) Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) Transmit data 2 (T2) +1 5
SIOAn
ADTPn
3
ADTCn
FA00H
Transmit data 1 (T1)
0
CSIAFn
(c) Completion of transmission
FA1FH
FA05H
Transmit data 6 (T6) Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) Transmit data 2 (T2) 5
SIOAn ADTPn
5
ADTCn
FA00H
Transmit data 1 (T1)
1
CSIAFn
Remark
n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
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(c) Repeat transmission mode In this mode, data stored in the internal buffer RAM is transmitted repeatedly. Serial transfer is started when the ATSTAn bit of serial trigger register n (CSITn) is set to 1 while the CSIAEn, ATEn, ATMn, and TXEn bits of serial operating mode specification register n (CSIMAn) are set to 1. Unlike the basic transmission mode, after the final byte (data in address FA1FH) has been transmitted, the interrupt request signal (INTCSIAn) is not generated, the automatic data transfer address count register n (ADTCn) is reset to 0, and the internal buffer RAM contents are transmitted again. The repeat transmission mode operation timing is shown in Figure 17-11, and the operation flowchart in Figure 17-12. Figure 17-13 shows the operation of the internal buffer RAM when 6 bytes of data are transmitted in the repeat transmission mode. Figure 17-11. Repeat Transmission Mode Operation Timing
Interval SCKAn SOAn D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Interval
D7 D6 D5
Caution
Because, in the repeat transmission mode, a read is performed on the buffer RAM after the transmission of one byte, the interval is included in the period up to the next transmission. As the buffer RAM read is performed at the same time as CPU processing, the interval is dependent upon automatic data transfer interval specification register n (ADTIn) (see (4) Automatic transmit/receive interval time).
Remark
n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
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Figure 17-12. Repeat Transmission Mode Flowchart
Start
Write transmit data in internal buffer RAM
Set ADTPn to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes
Software execution
Set the transmission/reception operation interval time in ADTIn
Set ATSTAn to 1
Write transmit data from internal buffer RAM to SIOAn
Increment pointer value
Transmission operation
Hardware execution ADTPn = ADTCn No
Yes
Reset ADTCn to 0
ADTPn: ADTIn: ATSTAn: SIOAn: ADTCn: Remark
Automatic data transfer address point specification register n Automatic data transfer interval specification register n Bit 0 of serial trigger register n (CSITn) Serial I/O shift register n Automatic data transfer address count register n n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
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In 6-byte transmission (ATMn bit = 1, RXEAn bit = 0, TXEAn bit = 1, ATEn bit = 1) in repeat transmission mode, internal buffer RAM operates as follows. (i) Before transmission (see Figure 17-13 (a).) When the ATSTAn bit of serial trigger register n (CSITn) is set to 1, transmit data 1 (T1) is transferred from the internal buffer RAM to the SIOAn register. When transmission of the first byte is completed, automatic data transfer address count register n (ADTCn) is incremented. Then transmit data 2 (T2) is transferred from the internal buffer RAM to the SIOAn register. (ii) Upon completion of transmission of 6 bytes (see Figure 17-13 (b).) When transmission of the sixth byte is completed, the interrupt request signal (INTCSIAn) is not generated. The ADTCn register is reset to 0. (iii) 7th byte transmission point (see Figure 17-13 (c).) Transmit data 1 (T1) is transferred from the internal buffer RAM to SIOAn register again. When transmission of the first byte is completed, the ADTCn register is incremented. Then transmit data 2 (T2) is transferred from the internal buffer RAM to the SIOAn register. Figure 17-13. Internal Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmission Mode) (1/2)
(a) Before transmission
FA1FH
FA05H
Transmit data 6 (T6) Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) Transmit data 2 (T2) +1 5
SIOAn ADTPn
0
ADTCn
FA00H
Transmit data 1 (T1)
0
CSIAFn
Remark
n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
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Figure 17-13. Internal Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmission Mode) (2/2)
(b) Upon completion of transmission of 6 bytes
FA1FH
FA05H
Transmit data 6 (T6) Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) Transmit data 2 (T2) 5
SIOAn ADTPn
5
ADTCn
FA00H
Transmit data 1 (T1)
0
CSIAFn
(c) 7th byte transmission point
FA1FH
FA05H
Transmit data 6 (T6) Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) Transmit data 2 (T2) +1 5
SIOAn ADTPn
0
ADTCn
FA00H
Transmit data 1 (T1)
0
CSIAFn
Remark
n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
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(d) Data format In the data format, data is changed in synchronization with the SCKAn pin falling edge as shown below. The data length is fixed to 8 bits and the data transfer direction can be switched by the specification of the DIRn bit of serial operation mode specification register n (CSIMAn). Figure 17-14. Format of CSIAn Transmit/Receive Data
(a) MSB-first (DIRn bit = 0)
SCKAn SIAn SOAn DO7 DI7 DO6 DI6 DO5 DI5 DO4 DI4 DO3 DI3 DO2 DI2 DO1 DI1 DO0 DI0
(b) LSB-first (DIRn bit = 1)
SCKAn SIAn SOAn DO0 DI0 DO1 DI1 DO2 DI2 DO3 DI3 DO4 DI4 DO5 DI5 DO6 DI6 DO7 DI7
Remark
n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
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(e) Automatic transmission/reception suspension and restart Automatic transmission/reception can be temporarily suspended by setting the ATSTPn bit of serial trigger register n (CSITn) to 1. During 8-bit data transfer, the transmission/reception is not suspended. It is suspended upon completion of 8-bit data transfer. When suspended, the TSFn bit of serial status register n (CSISn) is set to 0 after transfer of the 8th bit, and all the port pins that function alternately as serial interface pins are set to the port mode. To restart automatic transmission/reception, set the ATSTAn bit of the CSITn register to 1. remaining data can be transmitted in this way. Cautions 1. If the HALT instruction is executed during automatic transmission/reception, transfer is suspended and the HALT mode is set if during 8-bit data transfer. When the HALT mode is cleared, automatic transmission/reception is restarted from the suspended point. 2. When suspending automatic transmission/reception, do not change the operating mode to 3-wire serial I/O mode while the TSFn bit = 1. Figure 17-15. Automatic Transmission/Reception Suspension and Restart The
ATSTPn = 1 (Suspend command)
Suspend Restart command ATSTAn = 1
SCKAn SOAn SIAn D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
ATSTPn: Bit 1 of serial trigger register n (CSITn) ATSTAn: Bit 0 of CSITn Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
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(4) Automatic transmit/receive interval time When using the automatic transmit/receive function, the read/write operations from/to the internal buffer RAM are performed after transmitting/receiving one byte. transmit/receive operation. Since the read/write operations from/to the buffer RAM are performed in parallel with the CPU processing when using the automatic transmit/receive function by the internal clock, the interval depends on the value which is set in the automatic data transfer interval specification register n (ADTIn). Figure 17-16. Automatic Data Transmit/Receive Interval Time Therefore, an interval is inserted before the next
Interval SCKAn SOAn SIAn D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
CSIAFn
ACSIIF: Remark
Interrupt request flag
n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1)
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CHAPTER 18 I C BUS
2
To use the I C bus function, set the P38/SDA0, P39/SCL0, P80/SDA1, and P81/SCL1 pins to N-ch open drain output. The number of I C bus channels incorporated differs as follows depending on the product.
Product Name Number of channels V850ES/KF1 1 channel (I C0)
2
2
2
V850ES/KG1
V850ES/KJ1 2 channels (I2C0, I2C1)
The products with an on-chip I C bus are shown below. * V850/KF1: PD703208Y, 703209Y, 703210Y, 70F3210Y * V850/KG1: PD703212Y, 703213Y, 703214Y, 70F3214Y * V850/KJ1: PD703216Y, 703217Y, 70F3217Y
2
18.1 Selecting UART2 or I C1 Mode
UART2 and I C1 of the V850ES/KJ1 share pins, and therefore these interfaces cannot be used at the same time. Select UART2 or I C1 in advance by using the port 8 mode control register (PMC8) and port 8 function control register (PFC8) (refer to 4.3.8 Port 8). Caution UART2 or I C1 transmission/reception operations are not guaranteed if the mode is changed during transmission or reception. Be sure to disable the operation of the unit that is not used. Figure 18-1. Selecting Mode of UART2 or I C1
2 2 2 2
2
After reset: 00H 7 PMC8 0
R/W 6 0
Address: FFFFF450H 5 0 4 0 3 0 2 0 1 PMC81 0 PMC80
After reset: 00H 7 PFC8 0
R/W 6 0
Address: FFFFF470H 5 0 4 0 3 0 2 0 1 PFC81 0 PFC80
PFC8n 0 0 1 1
PMC8n 0 1 0 1
Operation mode Port I/O mode UART2 mode Port I/O mode I2C1 mode
Remark
n = 0, 1
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18.2 Features
The I C0 and I C1 have the following two modes. * Operation stop mode * I C (Inter IC) bus mode (multimaster supported) (1) Operation stop mode This mode is used when serial transfers are not performed. consumption. (2) I C bus mode (multimaster support) This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCLn) line and a serial data bus (SDAn) line. This mode complies with the I C bus format and the master device can output "start condition", "data", and "stop condition" data to the slave device, via the serial data bus. The slave device automatically detects these
2 2 2 2 2 2 2
It can therefore be used to reduce power
received data by hardware. This function can simplify the part of application program that controls the I C bus. Since the SCLn and SDAn pins are N-ch open drain outputs, the I Cn requires pull-up resistors for the serial clock line and the serial data bus line. Remark n = 0 (V850ES/KF1, V850ES/KG1) n = 0, 1 (V850ES/KJ1)
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Figure 18-2. Block Diagram of I Cn
2
Internal bus IIC status register n (IICSn)
MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn
IIC control register n (IICCn) SDAn Noise eliminator Slave address register n (SVAn) Match signal
IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn
SET CLEAR SO latch DQ CLn1, CLn0
IIC shift register n (IICn)
Start condition generator
N-ch opendrain output
Data hold time correction circuit
ACK output circuit
Wakeup controller ACK detector
Start condition detector
SCLn Noise eliminator
Stop condition detector Interrupt request signal generator
Serial clock counter
INTIICn
Serial clock controller N-ch opendrain output fXX Prescaler
Serial clock wait controller Bus status detector
CLDn DADn SMCn DFCn CLn1 CLn0 IIC clock selection register n (IICCLn)
CLXn
STCFn IICBSYn STCENn IICRSVn IIC flag register n (IICFn)
IIC function expansion register n (IICXn)
Internal bus
Remark
n = 0 (V850ES/KF1, V850ES/KG1) n = 0, 1 (V850ES/KJ1)
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A serial bus configuration example is shown below. Figure 18-3. Serial Bus Configuration Example Using I C Bus
2
+VDD +VDD
Master CPU1 Slave CPU1 Address 1
SDA SCL
Serial data bus Serial clock
SDA SCL
Master CPU2 Slave CPU2 Address 2
SDA SCL
Slave CPU3 Address 3
SDA SCL
Slave IC Address 4
SDA SCL
Slave IC Address N
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18.3 Configuration
I Cn includes the following hardware. Table 18-1. Configuration of I Cn
Item Registers Configuration IIC shift registers 0 and 1 (IIC0, IIC1) Slave address registers 0 and 1 (SVA0, SVA1) IIC control registers 0 and 1 (IICC0, IICC1) IIC status registers 0 and 1 (IICS0, IICS1) IIC flag registers 0, 1 (IICCF0, IICCF1) IIC clock selection registers 0 and 1 (IICCL0, IICCL1) IIC function expansion registers 0 and 1 (IICX0, IICX1)
2 2
Control registers
Remark
n = 0 (V850ES/KF1, V850ES/KG1) n = 0, 1 (V850ES/KJ1)
(1)
IIC shift registers 0 and 1 (IIC0, IIC1) IICn is used to convert 8-bit serial data to 8-bit parallel data and to convert 8-bit parallel data to 8-bit serial data. IICn can be used for both transmission and reception. Write and read operations to IICn are used to control the actual transmit and receive operations. IICn is set by an 8-bit memory manipulation instruction. RESET input clears IIC0 and IIC1 to 00H.
(2)
Slave address registers 0 and 1 (SVA0, SVA1) SVAn sets local addresses when in slave mode. SVAn is set by an 8-bit memory manipulation instruction. RESET input clears SVA0 and SVA1 to 00H.
(3)
SO latch The SO latch is used to retain the SDAn pin's output level.
(4)
Wakeup controller This circuit generates an interrupt request when the address received by this register matches the address value set to slave address register n (SVAn) or when an extension code is received.
(5)
Clock selector This selects the sampling clock to be used.
(6)
Serial clock counter This counter counts the serial clocks that are output and the serial clocks that are input during transmit/receive operations and is used to verify that 8-bit data was sent or received.
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(7) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIICn). An I C interrupt is generated following either of two triggers. * Eighth or ninth clock of the serial clock (set by WTIMn bit
Note 2
)
Note
* Interrupt request generated when a stop condition is detected (set by SPIEn bit Note WTIMn bit: Bit 3 of IIC control register n (IICCn) SPIEn bit: Bit 4 of IIC control register n (IICCn)
)
(8) Serial clock controller In master mode, this circuit generates the clock output via the SCLn pin from a sampling clock. (9) Serial clock wait controller This circuit controls the wait timing. (10) ACK output circuit, stop condition detector, start condition detector, and ACK detector These circuits are used to output and detect various control signals. (11) Data hold time correction circuit This circuit generates the hold time for data corresponding to the falling edge of the serial clock. (12) Start condition generator This circuit generates a start condition when the STTn bit is set. However, in the communication reservation disabled status (IICRSVn = 1), when the bus is not released (IICBSYn = 1), start condition requests are ignored and the STCFn flag is set. (13) Bus status detector This circuit detects whether or not the bus is released by detecting start conditions and stop conditions. However, as the bus status cannot be detected immediately following operation, the initial status is set by the STCENn bit.
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18.4 Control Registers
I C0 and I C1 are controlled by the following registers. * IIC control registers 0, 1 (IICC0, IICC1) * IIC status registers 0, 1 (IICS0, IICS1) * IIC flag registers 0, 1 (IICF0, IICF1) * IIC clock selection registers 0, 1 (IICCL0, IICCL1) * IIC function expansion registers 0, 1 (IICX0, IICX1) The following registers are also used. * IIC shift registers 0, 1 (IIC0, IIC1) * Slave address registers 0, 1 (SVA0, SVA1) (1) IIC control registers 0, 1 (IICC0, IICC1) IICCn is used to enable/disable I Cn operations, set wait timing, and set other I C operations. IICCn can be set by an 8-bit or 1-bit memory manipulation instruction (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). RESET input clears IICCn to 00H. Caution In I C0, I C1 bus mode, set the port 3 mode register (PM3) and port 8 mode register (PM8) as follows. In addition, set each output latch to 0. * Set P38 (SDA0) to output mode (PM38 = 0) * Set P39 (SCL0) to output mode (PM39 = 0) * Set P80 (SDA1) to output mode (PM80 = 0) * Set P81 (SCL1) to output mode (PM81 = 0)
2 2 2 2 2 2
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After reset: 00H <7> IICCn (n = 0, 1) IICEn 0 1 I2Cn operation enable/disable specification Stops operation. Presets IIC status register n (IICSn). Stops internal operation. Enables operation. Condition for setting (IICEn = 1) * Set by instruction IICEn R/W <6> LRELn 5 WRELn Address: FFFFFD82H, FFFFFD92H 4 SPIEn 3 WTIMn 2 ACKEn 1 STTn 0 SPTn
Condition for clearing (IICEn = 0) * Cleared by instruction * When RESET is input
LRELn 0 1 Normal operation
Exit from communications
This exits from the current communications operation and sets standby mode. This setting is automatically cleared after being executed. Its uses include cases in which a locally irrelevant extension code has been received. The SCLn and SDAn lines are set to high impedance. The following flags are cleared. * STDn * ACKDn * TRCn * COIn * EXCn * MSTSn * STTn * SPTn
The standby mode following exit from communications remains in effect until the following communications entry conditions are met. * After a stop condition is detected, restart is in master mode. * An address match or extension code reception occurs after the start condition. Condition for clearing (LRELn = 0)
Note
Condition for setting (LRELn = 1) * Set by instruction
* Automatically cleared after execution * When RESET is input
Note
This flag's signal is invalid when IICEn = 0. STDn: ACKDn: TRCn: COIn: EXCn: MSTSn: Bit 1 of IIC status register n (IICSn) Bit 2 of IIC status register n (IICSn) Bit 3 of IIC status register n (IICSn) Bit 4 of IIC status register n (IICSn) Bit 5 of IIC status register n (IICSn) Bit 7 of IIC status register n (IICSn)
Remark
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WRELn 0 1 Does not cancel wait Cancels wait. This setting is automatically cleared after wait is canceled.
Note
Wait cancellation control
Condition for clearing (WRELn = 0)
Condition for setting (WRELn = 1) * Set by instruction
* Automatically cleared after execution * When RESET is input
SPIEn 0 1 Disable Enable
Enable/disable generation of interrupt request when stop condition is detected
Condition for clearing (SPIEn = 0) * Cleared by instruction * When RESET is input
Note
Condition for setting (SPIEn = 1) * Set by instruction
WTIMn 0
Control of wait and interrupt request generation Interrupt request is generated at the eighth clock's falling edge. Master mode: After output of eight clocks, clock output is set to low level and wait is set. Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device. Interrupt request is generated at the ninth clock's falling edge. Master mode: After output of nine clocks, clock output is set to low level and wait is set. Slave mode: After input of nine clocks, the clock is set to low level and wait is set for master device.
1
This bit's setting is invalid during an address transfer and is valid as the transfer is completed. When in master mode, a wait is inserted at the falling edge of the ninth clock during address transfers. For a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an ACK signal is issued. When the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. Condition for clearing (WTIMn = 0) * Cleared by instruction * When RESET is input
Note
Condition for setting (WTIMn = 1) * Set by instruction
Note This flag's signal is invalid when IICEn = 0.
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ACKEn 0 1 Disable acknowledge. Enable acknowledge. During the ninth clock period, the SDAn line is set to low level. However, the ACK is invalid during address transfers and is valid when EXCn = 1.
Note
Acknowledge control
Condition for clearing (ACKEn = 0) * Cleared by instruction * When RESET is input
Condition for setting (ACKEn = 1) * Set by instruction
STTn 0 1 Does not generate a start condition.
Start condition trigger
When bus is released (in STOP mode): Generates a start condition (for starting as master). The SDAn line is changed from high level to low level and then the start condition is generated. Next, after the rated amount of time has elapsed, SCLn is changed to low level. When bus is not used: * When communication reservation function is enabled (IICRSVn = 0) Functions as the start condition reservation flag. When set, automatically generates a start condition after the bus is released. * When communication reservation function is disabled (IICRSVn = 1) The STCFn flag is set. No start condition is generated. In the wait state (when master device): Generates a restart condition after releasing the wait.
Cautions concerning set timing For master reception: Cannot be set during transfer. Can be set only when ACKEn has been set to 0 and slave has been notified of final reception. For master transmission: A start condition cannot be generated normally during the ACKn period. Set during the wait period. * Cannot be set at the same time as SPTn Condition for clearing (STTn = 0) * Cleared by instruction * Cleared by loss in arbitration * Cleared after start condition is generated by master device * When LRELn = 1 * When IICEn = 0 * Cleared when RESET is input Condition for setting (STTn = 1) * Set by instruction
Note This flag's signal is invalid when IICEn = 0. Remarks 1. Bit 1 (STTn) is 0 if it is read after data setting. 2. IICRSVn: Bit 0 of IIC flag register n (IICFn) STCFn: IICRSVn: Bit 7 of IIC flag register n (IICFn)
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SPTn 0 1 Stop condition is not generated. Stop condition is generated (termination of master device's transfer). After the SDAn line goes to low level, either set the SCLn line to high level or wait until it goes to high level. Next, after the rated amount of time has elapsed, the SDAn line is changed from low level to high level and a stop condition is generated. Stop condition trigger
Cautions concerning setting timing For master reception: Cannot be set during transfer. Can be set only when ACKEn has been set to 0 and during the wait period after slave has been notified of final reception. For master transmission: A stop condition cannot be generated normally during the ACKn period. Set during the wait period. * Cannot be set at the same time as STTn. * SPTn can be set only when in master modeNote * When WTIMn has been set to 0, if SPTn is set during the wait period that follows output of eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock. When a ninth clock must be output, WTIMn should be changed from 0 to 1 during the wait period following output of eight clocks, and SPTn should be set during the wait period that follows output of the ninth clock. Condition for clearing (SPTn = 0) * Cleared by instruction * Cleared by loss in arbitration * Automatically cleared after stop condition is detected * When LRELn = 1 * When IICEn = 0 * Cleared when RESET is input Condition for setting (SPTn = 1) * Set by instruction
Note Set SPTn only in master mode. However, SPTn must be set and a stop condition generated before the first stop condition is detected following the switch to operation enable status. For details, see 18.5 Cautions. Caution When bit 3 (TRCn) of IIC status register n (IICSn) is set to 1, WRELn is set during the ninth clock and wait is canceled, after which TRCn is cleared and the SDAn line is set to high impedance. Remark Bit 0 (SPTn) is 0 if it is read after data setting.
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(2) IIC status registers 0, 1 (IICS0, IICS1) IICSn indicates the status of the I Cn bus. IICSn can be set by an 8-bit or 1-bit memory manipulation instruction. IICSn is a read-only register (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). RESET input sets IICSn to 00H. (1/3)
After reset: 00H 7 IICSn (n = 0, 1) MSTSn R 6 ALDn 5 EXCn Address: FFFFFD86H, FFFFFD96H 4 COIn 3 TRCn 2 ACKDn 1 STDn 0 SPDn
2
MSTSn 0 1
Master device status Slave device status or communication standby status Master device communication status Condition for setting (MSTSn = 1) * When a start condition is generated
Condition for clearing (MSTSn = 0) * When a stop condition is detected * When ALDn = 1 * Cleared by LRELn = 1 * When IICEn changes from 1 to 0 * When RESET is input
ALDn 0 1
Detection of arbitration loss This status means either that there was no arbitration or that the arbitration result was a "win". This status indicates the arbitration result was a "loss". MSTSn is cleared. Condition for setting (ALDn = 1)
Note
Condition for clearing (ALDn = 0) * Automatically cleared after IICSn is read * When IICEn changes from 1 to 0 * When RESET is input
* When the arbitration result is a "loss".
Note This register is also cleared when a bit manipulation instruction is executed for bits other than IICSn. Remark LRELn: Bit 6 of IIC control register n (IICCn) IICEn: Bit 7 of IIC control register n (IICCn)
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EXCn 0 1 Extension code was not received. Extension code was received. Condition for setting (EXCn = 1) * When the higher four bits of the received address data is either "0000" or "1111" (set at the rising edge of the eighth clock). Detection of extension code reception
Condition for clearing (EXCn = 0) * When a start condition is detected * When a stop condition is detected * Cleared by LRELn = 1 * When IICEn changes from 1 to 0 * When RESET is input
COIn 0 1 Addresses do not match. Addresses match.
Detection of matching addresses
Condition for clearing (COIn = 0) * When a start condition is detected * When a stop condition is detected * Cleared by LRELn = 1 * When IICEn changes from 1 to 0 * When RESET is input
Condition for setting (COIn = 1) * When the received address matches the local address (SVAn) (set at the rising edge of the eighth clock).
TRCn 0 1
Detection of transmit/receive status Receive status (other than transmit status). The SDAn line is set for high impedance. Transmit status. The value in the SO latch is enabled for output to the SDAn line (valid starting at the falling edge of the first byte's ninth clock). Condition for setting (TRCn = 1) Master * When a start condition is generated Slave * When "1" is input by the first byte's LSB (transfer direction specification bit)
Condition for clearing (TRCn = 0) * When a stop condition is detected * Cleared by LRELn = 1 * When IICEn changes from 1 to 0 * Cleared by WRELn = 1Note * When ALDn changes from 0 to 1 * When RESET is input Master * When "1" is output to the first byte's LSB (transfer direction specification bit) Slave * When a start condition is detected When not used for communication
Note TRCn is cleared and SDAn line become high impedance when bit 5 (WRELn) of IIC control register n (IICCn) is set and wait state is released at ninth clock with bit 3 (TRCn) of IIC status register n (IICSn) = 1. Remark WRELn: Bit 5 of IIC control register n (IICCn) LRELn: IICEn: Bit 6 of IIC control register n (IICCn) Bit 7 of IIC control register n (IICCn)
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ACKDn 0 1 ACK was not detected. ACK was detected. Condition for setting (ACKDn = 1) * After the SDAn line is set to low level at the rising edge of the SCLn's ninth clock Detection of ACK
Condition for clearing (ACKDn = 0) * When a stop condition is detected * At the rising edge of the next byte's first clock * Cleared by LRELn = 1 * When IICEn changes from 1 to 0 * When RESET is input
STDn 0 1 Start condition was not detected.
Detection of start condition
Start condition was detected. This indicates that the address transfer period is in effect Condition for setting (STDn = 1) When a start condition is detected
Condition for clearing (STDn = 0) * When a stop condition is detected * At the rising edge of the next byte's first clock following address transfer * Cleared by LRELn = 1 * When IICEn changes from 1 to 0 * When RESET is input
SPDn 0 1 Stop condition was not detected.
Detection of stop condition
Stop condition was detected. The master device's communication is terminated and the bus is released. Condition for setting (SPDn = 1) When a stop condition is detected
Condition for clearing (SPDn = 0) * At the rising edge of the address transfer byte's first clock following setting of this bit and detection of a start condition * When IICEn changes from 1 to 0 * When RESET is input
Remark
LRELn: Bit 6 of IIC control register n (IICCn) IICEn: Bit 7 of IIC control register n (IICCn)
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(3) IIC flag registers 0, 1 (IICF0, IICF1) IICFn is used for I Cn control and as flags. IICFn is set with an 8-bit or 1-bit memory manipulation instruction (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). RESET input sets IICFn to 00H. (1/2)
After reset: 00H 7 IICFn (n = 0, 1) STCFn 0 1 Generate start condition Clear STTn flag Condition for setting (STCFn = 1) * Clearing of STTn when communication reservation is disabled (IICRSVn = 1). STTn clear flag STCFn R/WNote 6 IICBSYn Address: FFFFFD8AH, FFFFFD9AH 5 0 4 0 3 0 2 0 1 0
2
STCENn IICRSVn
Condition for clearing (STCFn = 0) * Clearing by setting STTn = 1 * RESET input
IICBSYn 0 1 Bus release status Bus communication status
I2Cn bus status flag
Condition for clearing (IICBSYn = 0) * Detection of stop condition * RESET input
Setting conditions (IICBSYn = 1) * Detection of start condition * Setting of IICEn when STCENn = 0
Note Bits 6 and 7 are read-only bits. Remark STTn: Bit 1 of IIC control register n (IICCn) IICEn: Bit 7 of IIC control register n (IICCn)
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STCENn 0 1 Initial start enable trigger After operation is enabled (IICEn = 1), generates a start condition upon detection of a stop condition. After operation is enabled (IICEn = 1), generates a start condition without detecting a stop condition. Condition for setting (STCEn = 1) * Setting by instruction
Condition for clearing (STCEn = 0) * Detection of start condition * RESET input
Cautions 1. Write to the STCENn bit only when the operation is stopped (IICEn = 0). 2. As the bus release status (IICBSY = 0) is recognized regardless of the actual bus status when STCENn = 1, when generating the first start condition (STTn = 1), it is necessary to verify that no third party communications are in progress in order to prevent such communications from being destroyed. Remark STTn: Bit 1 of IIC control register n (IICCn) IICEn: Bit 7 of IIC control register n (IICCn)
IICRSVn 0 1 Communication reservation function disable bit Enable communication reservation Disable communication reservation Condition for setting (IICRSVn = 1) * Setting by instruction
Condition for clearing (IICRSVn = 0) * Clearing by instruction * RESET input
Caution
Write to the IICRSVn bit only when the operation is stopped (IICEn = 0).
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(4) IIC clock selection registers 0, 1 (IICCL0, IICCL1) IICCLn is used to set the transfer clock for the I Cn bus. IICCLn can be set by an 8-bit or 1-bit memory manipulation instruction. Bits SMCn, CLn1 and CLn0 are set in combination with CLXn bit of IIC function expansion register n (IICXn) (see 18.4 (6) I Cn transfer clock setting method) (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). RESET input clears IICCLn to 00H.
2 2
After reset: 00H 7 IICCLn (n = 0, 1) 0
R/W
Note
Address: FFFFFD84H, FFFFFD94H 5 CLDn 4 DADn 3 SMCn 2 DFCn 1 CLn1 0 CLn0
6 0
CLDn 0 1
Detection of SCLn line level (valid only when IICEn = 1) SCLn line was detected at low level. SCLn line was detected at high level. Condition for setting (CLDn = 1) * When the SCLn line is at high level
Condition for clearing (CLDn = 0) * When the SCLn line is at low level * When IICEn = 0 * When RESET is input
DADn 0 1
Detection of SDAn line level (valid only when IICEn = 1) SDAn line was detected at low level. SDAn line was detected at high level. Condition for setting (DADn = 1) * When the SDAn line is at high level
Condition for clearing (DADn = 0) * When the SDAn line is at low level * When IICEn = 0 * When RESET is input
SMCn 0 1 Operates in standard mode. Operates in high-speed mode.
Operation mode switching
DFCn 0 1 Digital filter off. Digital filter on.
Digital filter operation control
Digital filter can be used only in high-speed mode. In high-speed mode, the transfer clock does not vary regardless of DFCn switching (on/off).
Note Bits 4 and 5 are read only bits. Remark IICEn: Bit 7 of IIC control register n (IICCn)
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(5) IIC function expansion registers 0, 1 (IICX0, IICX1) These registers set the function expansion of I Cn (valid only in high-speed mode). IICXn is set with a 1-bit or 8-bit memory manipulation instruction. Set the CLXn bit in combination with the SMCn, CLn1, and CLn0 bits of IIC clock selection register n (IICCLn) (see 18.4 (6) I Cn transfer clock setting method) (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). RESET input clears these registers to 00H.
After reset: 00H 7 IICXn (n = 0, 1) 0 R/W 6 0 Address: FFFFFD85H, FFFFFD95H 5 0 4 0 3 0 2 0 1 0 0 CLXn
2 2
(6) I Cn transfer clock setting method The I Cn transfer clock frequency (fSCL) is calculated using the following expression (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). fSCL = 1/(m x T + tR + tF) m = 12, 24, 48, 54, 86, 88, 172, 198 (see Table 18-2 Selection Clock Setting.) T: tR: tF: 1/fXX SCLn rise time SCLn fall time
2 2
2
For example, the I Cn transfer clock frequency (fSCL) when fXX = 20 MHz, m = 198, tR = 200 ns, and tF = 50 ns is calculated using following expression. fSCL = 1/(198 x 50 ns + 200 ns + 50 ns) 98.5 kHz
m x T + tR + tF tR m/2 x T tF m/2 x T
SCLn
SCLn inversion
SCLn inversion
SCLn inversion
The selection clock is set using a combination of the SMCn, CLn1, and CLn0 bits of IIC clock selection register n (IICCLn) and the CLXn bit of IIC function expansion register n (IICXn).
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Table 18-2. Selection Clock Setting
IICXn Bit 0 CLXn 0 0 0 0 0 0 0 1 1 1 1 Bit 3 SMCn 0 0 0 0 1 1 1 0 1 1 1
IICCLn Bit 1 CLn1 0 0 1 1 0 1 1 x 0 1 1 Bit 0 CLn0 0 1 0 1 x 0 1 x x 0 1
Selection Clock
Transfer clock (fXX/m)
Settable Internal System Clock Frequency (fXX) Range 4.0 MHz to 8.38 MHz 8.38 MHz to 16.76 MHz 4.19 MHz to 8.38 MHz 16.0 MHz to 19.8 MHz 8 MHz to 16.76 MHz 4 MHz to 8.38 MHz 16 MHz to 20 MHz
Operation Mode
fXX/2 fXX/2 fXX fXX/3 fXX/2 fXX fXX/3 Setting prohibited fXX/2 fXX Setting prohibited
fXX/88 fXX/172 fXX/86 fXX/198 fXX/48 fXX/24 fXX/54
Normal mode (SMCn = 0)
High-speed mode (SMCn = 1)
fXX/24 fXX/12
8.00 MHz to 8.38 MHz 4.00 MHz to 4.19 MHz
Normal mode (SMCn = 0)
Remarks 1. n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) 2. x: Don't care
(7) IIC shift registers 0, 1 (IIC0, IIC1) IICn is used for serial transmission/reception (shift operations) that is synchronized with the serial clock. It can be read from or written to in 8-bit units, but data should not be written to IICn during a data transfer (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)).
After reset: 00H 7 IICn (n = 0, 1)
R/W 6
Address: FFFFFD80H, FFFFFD90H 5 4 3 2 1 <0>
(8) Slave address registers 0, 1 (SVA0, SVA1) SVAn holds the I C bus's slave addresses. It can be read from or written to in 8-bit units, but bit 0 should be fixed as 0.
2
After reset: 00H 7 SVAn (n = 0, 1)
R/W 6
Address: FFFFFD83H, FFFFFD93H 5 4 3 2 1 0 0
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18.5 Functions
18.5.1 Pin configuration The serial clock pin (SCLn) and serial data bus pin (SDAn) are configured as follows (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). SCLn .............. This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. SDAn .............. This pin is used for serial data input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. Since outputs from the serial clock line and the serial data bus line are N-ch open-drain outputs, an external pullup resistor is required. Figure 18-4. Pin Configuration Diagram
VDD
Slave device
Master device SCLn Clock output VDD (Clock input) SDAn Data output SDAn Data output Clock input SCLn (Clock output)
Data input
Data input
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18.6 I C Bus Definitions and Control Methods
The following section describes the I C bus's serial data communication format and the signals used by the I C bus. The transfer timing for the "start condition", "data", and "stop condition" output via the I C bus's serial data bus is shown below. Figure 18-5. I C Bus's Serial Data Transfer Timing
2 2 2 2
2
SCLn
1 to 7
8
9
1 to 7
8
9
1 to 7
8
9
SDAn Start Address condition R/W ACK Data ACK Data ACK Stop condition
The master device outputs the start condition, slave address, and stop condition. The acknowledge signal (ACK) can be output by either the master or slave device (normally, it is output by the device that receives 8-bit data). The serial clock (SCLn) is continuously output by the master device. However, in the slave device, the SCLn's low-level period can be extended and a wait can be inserted (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). 18.6.1 Start condition A start condition is met when the SCLn pin is at high level and the SDAn pin changes from high level to low level. The start conditions for the SCLn pin and SDAn pin are signals that the master device outputs to the slave device when starting a serial transfer. The slave device includes hardware for detecting start conditions (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). Figure 18-6. Start Conditions
H SCLn
SDAn
A start condition is output when bit 1 (STTn) of IIC control register n (IICCn) is set to 1 after a stop condition has been detected (SPDn: Bit 0 = 1 in the IIC status register n (IICSn)). When a start condition is detected, bit 1 of IICSn (STDn) is set to 1.
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18.6.2 Addresses The 7 bits of data that follow the start condition are defined as an address. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via bus lines. Therefore, each slave device connected via the bus lines must have a unique address. The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data matches the data values stored in slave address register n (SVAn). If the address data matches the SVAn values, the slave device is selected and communicates with the master device until the master device transmits a start condition or stop condition (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). Figure 18-7. Address
SCLn
1
2
3
4
5
6
7
8
9
SDAn
AD6
AD5
AD4
AD3 Address
AD2
AD1
AD0
R/W
Note
INTIICn
Note The interrupt request signal (INTIICn) is generated if a local address or extension code is received during slave device operation. Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
The slave address and the eighth bit, which specifies the transfer direction as described in (3) Transfer direction specification below, are together written to the IIC shift register (IICn) and are then output. Received addresses are written to IICn. The slave address is assigned to the higher 7 bits of IICn.
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18.6.3 Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device. When the transfer direction specification bit has a value of 1, it indicates that the master device is receiving data from a slave device. Figure 18-8. Transfer Direction Specification
SCLn
1
2
3
4
5
6
7
8
9
SDAn
AD6
AD5
AD4
AD3
AD2
AD1
AD0
R/W
Transfer direction specification Note INTIICn
Note The interrupt request signal (INTIICn) is generated if a local address or extension code is received during slave device operation. Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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18.6.4 Acknowledge signal (ACK) The acknowledge signal (ACK) is used by the transmitting and receiving devices to confirm serial data reception. The receiving device returns one ACK signal for each 8 bits of data it receives. The transmitting device The normally receives an ACK signal after transmitting 8 bits of data. However, when the master device is the receiving device, it does not output an ACK signal after receiving the final data to be transmitted. transmitting device detects whether or not an ACK signal is returned after it transmits 8 bits of data. When an ACK signal is returned, the reception is judged as normal and processing continues. If the slave device does not return an ACK signal, the master device outputs either a stop condition or a restart condition and then stops the current transmission. Failure to return an ACK signal may be caused by the following two factors. (a) Reception was not performed normally. (b) The final data was received. When the receiving device sets the SDAn line to low level during the ninth clock, the ACK signal becomes active (normal receive response). When bit 2 (ACKEn) of IIC control register n (IICCn) is set to 1, automatic ACK signal generation is enabled (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). Transmission of the eighth bit following the 7 address data bits causes bit 3 (TRCn) of IIC status register n (IICSn) to be set. When this TRCn bit's value is 0, it indicates receive mode. Therefore, ACKEn should be set to 1 (n = 0, 1). When the slave device is receiving (when TRCn = 0), if the slave device does not need to receive any more data after receiving several bytes, setting ACKEn to 0 will prevent the master device from starting transmission of the subsequent data. Similarly, when the master device is receiving (when TRCn = 0) and the subsequent data is not needed and when either a restart condition or a stop condition should therefore be output, setting ACKEn to 0 will prevent the ACK signal from being returned. This prevents the MSB data from being output via the SDAn line (i.e., stops transmission) during transmission from the slave device. Figure 18-9. ACK Signal
SCLn
1
2
3
4
5
6
7
8
9
SDAn
AD6
AD5
AD4
AD3
AD2
AD1
AD0
R/W ACK
Remark
n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
When the local address is received, an ACK signal is automatically output in synchronization with the falling edge of the SCLn's eighth clock regardless of the ACKEn value. No ACK signal is output if the received address is not a local address (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). The ACK signal output method during data reception is based on the wait timing setting, as described below. When 8-clock wait is selected: ACK signal is output at the falling edge of the SCLn's eighth clock if ACKEn is set to 1 before wait cancellation. When 9-clock wait is selected: ACK signal is automatically output at the falling edge of the SCLn's eighth clock if ACKEn has already been set to 1.
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18.6.5 Stop condition When the SCLn pin is at high level, changing the SDAn pin from low level to high level generates a stop condition (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). A stop condition is a signal that the master device outputs to the slave device when serial transfer has been completed. The slave device includes hardware that detects stop conditions. Figure 18-10. Stop Condition
H SCLn
SDAn
Remark
n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
A stop condition is generated when bit 0 (SPTn) of IIC control register n (IICCn) is set to 1. When the stop condition is detected, bit 0 (SPDn) of IIC status register n (IICSn) is set to 1 and INTIICn is generated when bit 4 (SPIEn) of IICCn is set to 1.
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18.6.6 Wait signal (WAIT) The wait signal (WAIT) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCLn pin to low level notifies the communication partner of the wait status. When wait status has been canceled for both the master and slave devices, the next data transfer can begin (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). Figure 18-11. Wait Signal (1/2)
(a) When master device has a nine-clock wait and slave device has an eight-clock wait (master: transmission, slave: reception, and ACKEn = 1)
Master Master returns to high Wait after output impedance but slave is in wait state (low level). of ninth clock. IICn data write (cancel wait)
IICn
SCLn
6
7
8
9
1
2
3
Slave Wait after output of eighth clock. FFH is written to IICn or WRELn is set to 1. IICn SCLn
ACKEn
H
Transfer lines
SCLn
6
7
8
9
1
2
3
SDAn
D2
D1
D0
ACK
D7
D6
D5
Remark
n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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Figure 18-11. Wait Signal (2/2)
(b) When master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and ACKEn = 1)
Master IICn
Master and slave both wait after output of ninth clock. IICn data write (cancel wait)
SCLn Slave IICn SCLn
6
7
8
9
1
2
3
FFH is written to IICn or WRELn is set to 1.
ACKEn Transfer lines SCLn
H
6
7
8
9
1
2
3
SDAn
D2
D1
D0
ACK
D7
D6
D5
Output according to previously set ACKEn value
Remarks 1. ACKEn: WRELn:
Bit 2 of IIC control register n (IICCn) Bit 5 of IIC control register n (IICCn)
2. n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
A wait may be automatically generated depending on the setting for bit 3 (WTIMn) of IIC control register n (IICCn). Normally, when bit 5 (WRELn) of IICCn is set to 1 or when FFH is written to IIC shift register n (IICn), the wait status is canceled and the transmitting side writes data to IICn to cancel the wait status. The master device can also cancel the wait status via either of the following methods. * By setting bit 1 (STTn) of IICCn to 1 * By setting bit 0 (SPTn) of IICCn to 1
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18.7 I C Interrupt Requests (INTIICn)
The following shows the value of IIC status register n (IICSn) at the INTIICn interrupt request generation timing and at the INTIICn interrupt timing (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). 18.7.1 Master device operation (1) Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) <1> When WTIMn = 0
SPTn = 1 ST AD6 to AD0 RW AK L1 L1: IICSn = 10XXX110B L2: IICSn = 10XXX000B L3: IICSn = 10XXX000B (WTIMn = 0) L4: IICSn = 10XXXX00B 5: IICSn = 00000001B D7 to D0 L2 AK D7 to D0 L3 AK L4 SP 5
2
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
<2> When WTIMn = 1
SPTn = 1 ST AD6 to AD0 RW AK L1 L1: IICSn = 10XXX110B L2: IICSn = 10XXX100B L3: IICSn = 10XXXX00B 4: IICSn = 00000001B D7 to D0 AK L2 D7 to D0 AK L3 SP 4
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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(2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) <1> When WTIMn = 0
STTn = 1 ST AD6 to AD0 RW AK L1 D7 to D0 L2 AK L3 ST AD6 to AD0 RW AK L4 D7 to D0 L5 SPTn = 1 AK L6 SP 7
L1: IICSn = 10XXX110B L2: IICSn = 10XXX000B (WTIMn = 1) L3: IICSn = 10XXXX00B (WTIMn = 0) L4: IICSn = 10XXX110B (WTIMn = 0) L5: IICSn = 10XXX000B (WTIMn = 1) L6: IICSn = 10XXXX00B 7: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
<2> When WTIMn = 1
STTn = 1 ST AD6 to AD0 RW AK L1 D7 to D0 AK L2 ST AD6 to AD0 RW AK L3 D7 to D0 SPTn = 1 AK L4 SP 5
L1: IICSn = 10XXX110B L2: IICSn = 10XXXX00B L3: IICSn = 10XXX110B L4: IICSn = 10XXXX00B 5: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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(3) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIMn = 0
SPTn = 1 ST AD6 to AD0 RW AK L1 L1: IICSn = 1010X110B L2: IICSn = 1010X000B L3: IICSn = 1010X000B (WTIMn = 1) L4: IICSn = 1010XX00B 5: IICSn = 00000001B D7 to D0 L2 AK D7 to D0 L3 AK L4 SP 5
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
<2> When WTIMn = 1
SPTn = 1 ST AD6 to AD0 RW AK L1 L1: IICSn = 1010X110B L2: IICSn = 1010X100B L3: IICSn = 1010XX00B 4: IICSn = 00000001B D7 to D0 AK L2 D7 to D0 AK L3 SP 4
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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18.7.2 Slave device operation (when receiving slave address data (match with SVAn)) (1) Start ~ Address ~ Data ~ Data ~ Stop <1> When WTIMn = 0
ST AD6 to AD0 RW AK L1 L1: IICSn = 0001X110B L2: IICSn = 0001X000B L3: IICSn = 0001X000B 4: IICSn = 00000001B D7 to D0 L2 AK D7 to D0 L3 AK SP 4
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
<2> When WTIMn = 1
ST AD6 to AD0 RW AK L1 L1: IICSn = 0001X110B L2: IICSn = 0001X100B L3: IICSn = 0001XX00B 4: IICSn = 00000001B D7 to D0 AK L2 D7 to D0 AK L3 SP 4
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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(2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, match with SVAn)
ST AD6 to AD0 RW AK L1 D7 to D0 L2 AK ST AD6 to AD0 RW AK L3 D7 to D0 L4 AK SP 5
L1: IICSn = 0001X110B L2: IICSn = 0001X000B L3: IICSn = 0001X110B L4: IICSn = 0001X000B 5: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
<2> When WTIMn = 1 (after restart, match with SVAn)
ST AD6 to AD0 RW AK L1 D7 to D0 AK L2 ST AD6 to AD0 RW AK L3 D7 to D0 AK L4 SP 5
L1: IICSn = 0001X110B L2: IICSn = 0001XX00B L3: IICSn = 0001X110B L4: IICSn = 0001XX00B 5: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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(3) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn = 0 (after restart, extension code reception)
ST AD6 to AD0 RW AK L1 D7 to D0 L2 AK ST AD6 to AD0 RW L3 AK D7 to D0 L4 AK SP 5
L1: IICSn = 0001X110B L2: IICSn = 0001X000B L3: IICSn = 0010X010B L4: IICSn = 0010X000B 5: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
<2> When WTIMn = 1 (after restart, extension code reception)
ST AD6 to AD0 RW AK L1 D7 to D0 AK L2 ST AD6 to AD0 RW L3 AK L4 D7 to D0 AK L5 SP 6
L1: IICSn = 0001X110B L2: IICSn = 0001XX00B L3: IICSn = 0010X010B L4: IICSn = 0010X110B L5: IICSn = 0010XX00B 6: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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(4) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, mismatch with address (= not extension code))
ST AD6 to AD0 RW AK L1 D7 to D0 L2 AK ST AD6 to AD0 RW AK L3 D7 to D0 AK SP 4
L1: IICSn = 0001X110B L2: IICSn = 0001X000B L3: IICSn = 00000X10B 4: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
<2> When WTIMn = 1 (after restart, mismatch with address (= not extension code))
ST AD6 to AD0 RW AK L1 D7 to D0 AK L2 ST AD6 to AD0 RW AK L3 D7 to D0 AK SP 4
L1: IICSn = 0001X110B L2: IICSn = 0001XX00B L3: IICSn = 00000X10B 4: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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18.7.3 Slave device operation (when receiving extension code) (1) Start ~ Code ~ Data ~ Data ~ Stop <1> When WTIMn = 0
ST AD6 to AD0 RW L1 L1: IICSn = 0010X010B L2: IICSn = 0010X000B L3: IICSn = 0010X000B 4: IICSn = 00000001B AK D7 to D0 L2 AK D7 to D0 L3 AK SP 4
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
<2> When WTIMn = 1
ST AD6 to AD0 RW L1 L1: IICSn = 0010X010B L2: IICSn = 0010X110B L3: IICSn = 0010X100B L4: IICSn = 0010XX00B 5: IICSn = 00000001B AK L2 D7 to D0 AK L3 D7 to D0 AK L4 SP 5
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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(2) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, match with SVAn)
ST AD6 to AD0 RW L1 AK D7 to D0 L2 AK ST AD6 to AD0 RW AK L3 D7 to D0 L4 AK SP 5
L1: IICSn = 0010X010B L2: IICSn = 0010X000B L3: IICSn = 0001X110B L4: IICSn = 0001X000B 5: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
<2> When WTIMn = 1 (after restart, match with SVAn)
ST AD6 to AD0 RW L1 AK L2 D7 to D0 AK L3 ST AD6 to AD0 RW AK L4 D7 to D0 AK L5 SP 6
L1: IICSn = 0010X010B L2: IICSn = 0010X110B L3: IICSn = 0010XX00B L4: IICSn = 0001X110B L5: IICSn = 0001XX00B 6: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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(3) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn = 0 (after restart, extension code reception)
ST AD6 to AD0 RW L1 AK D7 to D0 L2 AK ST AD6 to AD0 RW L3 AK D7 to D0 L4 AK SP 5
L1: IICSn = 0010X010B L2: IICSn = 0010X000B L3: IICSn = 0010X010B L4: IICSn = 0010X000B 5: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
<2> When WTIMn = 1 (after restart, extension code reception)
ST AD6 to AD0 RW L1 AK L2 D7 to D0 AK L3 ST AD6 to AD0 RW L4 AK L5 D7 to D0 AK L6 SP 7
L1: IICSn = 0010X010B L2: IICSn = 0010X110B L3: IICSn = 0010XX00B L4: IICSn = 0010X010B L5: IICSn = 0010X110B L6: IICSn = 0010XX00B 7: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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(4) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, mismatch with address (= not extension code))
ST AD6 to AD0 RW L1 AK D7 to D0 L2 AK ST AD6 to AD0 RW AK L3 D7 to D0 AK SP 4
L1: IICSn = 0010X010B L2: IICSn = 0010X000B L3: IICSn = 00000X10B 4: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
<2> When WTIMn = 1 (after restart, mismatch with address (= not extension code))
ST AD6 to AD0 RW L1 AK L2 D7 to D0 AK L3 ST AD6 to AD0 RW AK L4 D7 to D0 AK SP 5
L1: IICSn = 0010X010B L2: IICSn = 0010X110B L3: IICSn = 0010XX00B L4: IICSn = 00000X10B 5: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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18.7.4 Operation without communication (1) Start ~ Code ~ Data ~ Data ~ Stop
ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 1: IICSn = 00000001B
Remark
:
Generated only when SPIEn = 1
n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
18.7.5 Arbitration loss operation (operation as slave after arbitration loss) (1) When arbitration loss occurs during transmission of slave address data <1> When WTIMn = 0
ST AD6 to AD0 RW AK L1 D7 to D0 L2 AK D7 to D0 L3 AK SP 4
L1: IICSn = 0101X110B (Example: when ALDn is read during interrupt servicing) L2: IICSn = 0001X000B L3: IICSn = 0001X000B 4: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
<2> When WTIMn = 1
ST AD6 to AD0 RW AK L1 D7 to D0 AK L2 D7 to D0 AK L3 SP 4
L1: IICSn = 0101X110B (Example: when ALDn is read during interrupt servicing) L2: IICSn = 0001X100B L3: IICSn = 0001XX00B 4: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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(2) When arbitration loss occurs during transmission of extension code <1> When WTIMn = 0
ST AD6 to AD0 RW L1 AK D7 to D0 L2 AK D7 to D0 L3 AK SP 4
L1: IICSn = 0110X010B (Example: when ALDn is read during interrupt servicing) L2: IICSn = 0010X000B L3: IICSn = 0010X000B 4: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
<2> When WTIMn = 1
ST AD6 to AD0 RW L1 AK L2 D7 to D0 AK L3 D7 to D0 AK L4 SP 5
L1: IICSn = 0110X010B (Example: when ALDn is read during interrupt servicing) L2: IICSn = 0010X110B L3: IICSn = 0010X100B L4: IICSn = 0010XX00B 5: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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18.7.6 Operation when arbitration loss occurs (no communication after arbitration loss) (1) When arbitration loss occurs during transmission of slave address data
ST AD6 to AD0 RW AK L1 D7 to D0 AK D7 to D0 AK SP 2
L1: IICSn = 01000110B (Example: when ALDn is read during interrupt servicing) 2: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
(2) When arbitration loss occurs during transmission of extension code
ST AD6 to AD0 RW L1 AK D7 to D0 AK D7 to D0 AK SP 2
L1:
IICSn = 0110X010B (Example: when ALDn is read during interrupt servicing)
IICCn's LRELn is set to 1 by software 2: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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(3) When arbitration loss occurs during data transfer <1> When WTIMn = 0
ST
AD6 to AD0
RW
AK L1
D7 to D0 L2
AK
D7 to D0
AK
SP 3
L1: IICSn = 10001110B L2: IICSn = 01000000B (Example: when ALDn is read during interrupt servicing) 3: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
<2> When WTIMn = 1
ST AD6 to AD0 RW AK L1 D7 to D0 AK L2 D7 to D0 AK SP 3
L1: IICSn = 10001110B L2: IICSn = 01000100B (Example: when ALDn is read during interrupt servicing) 3: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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(4) When loss occurs due to restart condition during data transfer <1> Not extension code (Example: mismatches with SVAn)
ST AD6 to AD0 RW AK L1 D7 to Dn ST AD6 to AD0 RW AK L2 D7 to D0 AK SP 3
L1: IICSn = 1000X110B L2: IICSn = 01000110B (Example: when ALDn is read during interrupt servicing) 3: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care Dn = D6 to D0 n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
<2> Extension code
ST AD6 to AD0 RW AK L1 D7 to Dn ST AD6 to AD0 RW L2 AK D7 to D0 AK SP 3
L1: IICSn = 1000X110B L2: IICSn = 0110X010B (Example: when ALDn is read during interrupt servicing) IICCn's LRELn is set to 1 by software 3: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care Dn = D6 to D0 n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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(5) When loss occurs due to stop condition during data transfer
ST AD6 to AD0 RW AK L1 L1: IICSn = 1000X110B 2: IICSn = 01000001B D7 to Dn SP 2
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care Dn = D6 to D0 n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
(6) When arbitration loss occurs due to low-level data when attempting to generate a restart condition When WTIMn = 1
STTn = 1 ST AD6 to AD0 RW AK L1 D7 to D0 AK L2 D7 to D0 AK L3 D7 to D0 AK SP 4
L1: IICSn = 1000X110B L2: IICSn = 1000XX00B L3: IICSn = 01000100B (Example: when ALDn is read during interrupt servicing) 4: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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(7) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition When WTIMn = 1
STTn = 1 ST AD6 to AD0 RW AK L1 L1: IICSn = 1000X110B L2: IICSn = 1000XX00B 3: IICSn = 01000001B D7 to D0 AK L2 SP 3
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
(8) When arbitration loss occurs due to low-level data when attempting to generate a stop condition When WTIMn = 1
SPTn = 1 ST AD6 to AD0 RW AK L1 D7 to D0 AK L2 D7 to D0 AK L3 D7 to D0 AK SP 4
L1: IICSn = 1000X110B L2: IICSn = 1000XX00B L3: IICSn = 01000000B (Example: when ALDn is read during interrupt servicing) 4: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: Don't care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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18.8 Interrupt Request (INTIICn) Generation Timing and Wait Control
The setting of bit 3 (WTIMn) in IIC control register n (IICCn) determines the timing by which INTIICn is generated and the corresponding wait control, as shown below. Table 18-3. INTIICn Generation Timing and Wait Control
WTIMn During Slave Device Operation Address 0 1 9 9
Notes 1, 2 Notes 1, 2
During Master Device Operation Address 9 9 Data Reception 8 9 Data Transmission 8 9
Data Reception 8 9
Note 2 Note 2
Data Transmission 8 9
Note 2 Note 2
Notes 1.
The slave device's INTIICn signal and wait period occurs at the falling edge of the ninth clock only when there is a match with the address set to slave address register n (SVAn). At this point, ACK is output regardless of the value set to IICCn's bit 2 (ACKEn). For a slave device that has received an extension code, INTIICn occurs at the falling edge of the eighth clock.
2.
If the received address does not match the contents of slave address register n (SVAn), neither INTIICn nor a wait occurs.
Remarks 1. The numbers in the table indicate the number of the serial clock's clock signals. Interrupt requests and wait control are both synchronized with the falling edge of these clock signals. 2. n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
(1) During address transmission/reception * Slave device operation: Interrupt and wait timing are determined regardless of the WTIMn bit. the WTIMn bit. (2) During data reception * Master/slave device operation: Interrupt and wait timing are determined according to the WTIMn bit. (3) During data transmission * Master/slave device operation: Interrupt and wait timing are determined according to the WTIMn bit. (4) Wait cancellation method The four wait cancellation methods are as follows. * By setting bit 5 (WRELn) of IIC control register n (IICCn) to 1 * By writing to IIC shift register n (IICn) * By start condition setting (bit 1 (STTn) of IIC control register n (IICCn) = 1) * By step condition setting (bit 0 (SPTn) of IIC control register n (IICCn) = 1) When an 8-clock wait has been selected (WTIMn = 0), the output level of ACK must be determined prior to wait cancellation. Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) * Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of
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(5)
Stop condition detection INTIICn is generated when a stop condition is detected. Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
18.9 Address Match Detection Method
When in I C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match detection is performed automatically by hardware. An interrupt request (INTIICn) occurs when a local address has been set to slave address register n (SVAn) and when the address set to SVAn matches the slave address sent by the master device, or when an extension code has been received (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)).
2
18.10 Error Detection
In I C bus mode, the status of the serial data bus (SDAn) during data transmission is captured by IIC shift register n (IICn) of the transmitting device, so the IICn data prior to transmission can be compared with the transmitted IICn data to enable detection of transmission errors. A transmission error is judged as having occurred when the compared data values do not match (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)).
2
18.11 Extension Code
(1) When the higher 4 bits of the receive address are either 0000 or 1111, the extension code flag (EXCn) is set for extension code reception and an interrupt request (INTIICn) is issued at the falling edge of the eighth clock. The local address stored in slave address register n (SVAn) is not affected. (2) If 11110xx0 is set to SVAn by a 10-bit address transfer and 11110xx0 is transferred from the master device, the results are as follows. Note that INTIICn occurs at the falling edge of the eighth clock. * Higher 4 bits of data match: EXCn = 1 * 7 bits of data match: COIn = 1
Note Note
Note EXCn: Bit 5 of IIC status register n (IICSn) COIn: Bit 4 of IIC status register n (IICSn) (3) Since the processing after the interrupt request occurs differs according to the data that follows the extension code, such processing is performed by software. For example, when operation as a slave is not desired after the extension code is received, set bit 6 (LRELn) of IIC control register n (IICCn) to 1 and the CPU will enter the next communication wait state. Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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Table 18-4. Extension Code Bit Definitions
Slave Address 0000 0000 0000 0000 1111 000 000 001 010 0xx R/W Bit 0 1 X X X General call address Start byte CBUS address Address that is reserved for different bus format 10-bit slave address specification Description
18.12 Arbitration
When several master devices simultaneously output a start condition (when STTn is set to 1 before STDn is set to 1
Note
), communication among the master devices is performed as the number of clocks is adjusted until the data
differs. This kind of operation is called arbitration (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). When one of the master devices loses in arbitration, an arbitration loss flag (ALDn) in IIC status register n (IICSn) is set via the timing by which the arbitration loss occurred, and the SCLn and SDAn lines are both set for high impedance, which releases the bus. The arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a stop condition is detected, etc.) and the ALDn = 1 setting that has been made by software. For details of interrupt request timing, see 18.7 I C Interrupt Requests (INTIICn). Note STDn: Bit 1 of IIC status register n (IICSn) STTn: Bit 1 of IIC control register n (IICCn) Figure 18-12. Arbitration Timing Example
2
Master 1 SCLn Hi-Z
SDAn Master 2 SCLn
Hi-Z Master 1 loses arbitration
SDAn Transfer lines SCLn
SDAn
Remark
n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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Table 18-5. Status During Arbitration and Interrupt Request Generation Timing
Status During Arbitration During address transmission Read/write data after address transmission During extension code transmission Read/write data after extension code transmission During data transmission During ACK signal transfer period after data reception When restart condition is detected during data transfer When stop condition is detected during data transfer When data is at low level while attempting to output a restart condition When stop condition is detected while attempting to output a restart condition When data is at low level while attempting to output a stop condition When SCLn is at low level while attempting to output a restart condition
Interrupt Request Generation Timing At falling edge of eighth or ninth clock following byte transfer
Note 1
When stop condition is output (when SPIEn = 1)
Note 2 Note 1
At falling edge of eighth or ninth clock following byte transfer
Note 2
When stop condition is output (when SPIEn = 1)
At falling edge of eighth or ninth clock following byte transfer
Note 1
Notes 1.
When WTIMn (bit 3 of the IIC control register n (IICCn)) = 1, an interrupt request occurs at the falling edge of the ninth clock. When WTIMn = 0 and the extension code's slave address is received, an interrupt request occurs at the falling edge of the eighth clock.
2.
When there is a possibility that arbitration will occur, set SPIEn = 1 for master device operation.
Remarks 1. SPIEn: Bit 5 of IIC control register n (IICCn) 2. n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
18.13 Wakeup Function
The I C bus slave function is a function that generates an interrupt request (INTIICn) when a local address or extension code has been received. This function makes processing more efficient by preventing unnecessary interrupt requests from occurring when addresses do not match. When a start condition is detected, wakeup standby mode is set. This wakeup standby mode is in effect while addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has output a start condition) to a slave device. However, when a stop condition is detected, bit 5 (SPIEn) of IIC control register n (IICCn) is set regardless of the wake up function, and this determines whether interrupt requests are enabled or disabled (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)).
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18.14 Communication Reservation
To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used. * When arbitration results in neither master nor slave operation * When an extension code is received and slave operation is disabled (ACK is not returned and the bus was released when bit 6 (LRELn) of IIC control register n (IICCn) was set to "1"). If bit 1 (STTn) of IICCn is set while the bus is not used, a start condition is automatically generated and wait status is set after the bus is released (after a stop condition is detected). When the bus release is detected (when a stop condition is detected), writing to IIC shift register n (IICn) causes the master's address transfer to start. At this point, IICCn's bit 4 (SPIEn) should be set. When STTn has been set, the operation mode (as start condition or as communication reservation) is determined according to the bus status. If the bus has been released ............................................. a start condition is generated If the bus has not been released (standby mode) ............. communication reservation To detect which operation mode has been determined for STTn, set STTn, wait for the wait period, then check the MSTSn (bit 7 of IIC status register n (IICSn)). Wait periods, which should be set via software, are listed in Table 18-6. These wait periods can be set via the settings for bits 3, 1, and 0 (SMCn, CLn1, and CLn0) in IIC clock selection register n (IICCLn). Table 18-6. Wait Periods
SMCn 0 0 0 0 1 1 1 1
CLn1 0 0 1 1 0 0 1 1
CLn0 0 1 0 1 0 1 0 1
Wait Period 26 clocks 46 clocks 92 clocks 37 clocks 16 clocks
32 clocks 13 clocks
Remark
n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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The communication reservation timing is shown below. Figure 18-13. Communication Reservation Timing
Program processing
STTn =1
Write to IICn
Hardware processing
Communication reservation
Set SPDn and INTIICn
Set STDn
SCLn
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
SDAn
Output by master with bus access
IICn: STTn: STDn: SPDn: Remark
IIC shift register n Bit 1 of IIC control register n (IICCn) Bit 1 of IIC status register n (IICSn) Bit 0 of IIC status register n (IICSn) n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
Communication reservations are accepted via the following timing. After bit 1 (STDn) of IIC status register n (IICSn) is set to 1, a communication reservation can be made by setting bit 1 (STTn) of IIC control register n (IICCn) to 1 before a stop condition is detected (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). Figure 18-14. Timing for Accepting Communication Reservations
SCLn
SDAn
STDn
SPDn
Standby mode
Remark
n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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The communication reservation flowchart is illustrated below. Figure 18-15. Communication Reservation Flowchart
DI
SET1 STTn
; Sets STTn flag (communication reservation).
Define communication reservation
; Defines that communication reservation is in effect (defines and sets user flag to any part of RAM).
Wait
; Gets wait period set by software (see Table 18-6).
Note
(Communication reservation) Yes MSTSn = 0?
; Confirmation of communication reservation
No (Generate start condition) Cancel communication reservation ; Clear user flag.
IICn xxH
; IICn write operation
EI
Note The communication reservation operation executes a write to IIC shift register n (IICn) when a stop condition interrupt request occurs. Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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18.15 Cautions
After a reset, when changing from a mode in which no stop condition has been detected (the bus has not been released) to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication. When using multiple masters, it is not possible to perform master device communication when the bus has not been released (when a stop condition has not been detected). Use the following sequence for generating a stop condition. (a) Set IIC clock selection register n (IICCLn). (b) Set bit 7 (IICEn) of IIC control register n (IICCn). (c) Set bit 0 of IICCn. Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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18.16 Communication Operations
18.16.1 Master operations The following is a flowchart of the master operations. Figure 18-16. Master Operation Flowchart (1)
START
IICCLn xxH Select transfer clock.
IICCn xxH IICEn = SPIEn = WTIMn = 1 SPTn = 1
; IICCn initial setting
INTIICn = 1? Yes Start IICn write transfer.
No
; Stop condition detection
INTIICn = 1? Yes ACKDn = 1? Yes TRCn = 1? Yes (transmit) Start IICn write transfer.
No
No Generate stop condition. (no slave with matching address) No (receive) ; Address transfer completion WTIMn = 0 ACKEn = 1
WRELn = 1 Start reception. INTIICn = 1? No No
INTIICn = 1? Data processing Yes Data processing ACKDn = 1? No Yes
Transfer completed? Yes ACKEn = 0
No
Generate restart condition or stop condition.
Remark
n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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Figure 18-17. Master Operation Flowchart (2)
START IICCLn XXH IICFn XXH IICCn XXH IICEn = SPIEn = WTIMn = 1 Transfer clock selection IICFn register setting
IICCn register initial setting
IICBSYn = 1? Yes
No STTn = 1 3 clocks input No STCFn = 1? No
INTIICn = 1? Yes
Yes IICn write Transfer start
INTIICn = 1?
No
Yes (address transfer end) No ACKDn = 1? Yes TRCn = 1? Yes (transmission) IICn write Start transfer WRELn = 1 Reception start INTIICn = 1? Yes Data processing No INTIICn = 1? Yes Data processing ACKDn = 1? Yes No Reception completed? Yes ACKEn = 0 No No No (reception) WTIMn = 0 ACKEn = 1
Transfer completed? Yes SPTn = 1 Stop condition generated
No (Restart)
Remark
n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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18.16.2 Slave operation An example of slave operation is shown below. Figure 18-18. Slave Operation Flowchart
START
IICCn xxH IICEn = 1
INTIICn = 1? Yes EXCn = 1? No No COIn = 1? Yes TRCn = 1? Yes WTIMn = 1 Start IICn write transfer.
No
Yes
Communicate? Yes
No
LRELn = 1
No
WTIMn = 0 ACKEn = 1
WRELn = 1 Start reception. INTIICn = 1? Yes Data processing No INTIICn = 1? Yes Data processing ACKDn = 1? No Yes Transfer completed? Yes Detect restart condition or stop condition. ACKEn = 0 No No
Remark
n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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18.17 Timing of Data Communication
When using I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRCn bit (bit 3 of IIC status register n (IICSn)) that specifies the data transfer direction and then starts serial communication with the slave device. IIC shift register n (IICn)'s shift operation is synchronized with the falling edge of the serial clock (SCLn). The transmit data is transferred to the SO latch and is output (MSB first) via the SDAn pin. Data input via the SDAn pin is captured by IICn at the rising edge of SCLn. The data communication timing is shown below. Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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Figure 18-19. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ address
Processing by master device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn H Transmit L L H H IICn address IICn data
Transfer lines SCLn SDAn 1 2 3 4 5 6 7 8 W 9 ACK 1 D7 2 D6 3 D5 4 D4
AD6 AD5 AD4 AD3 AD2 AD1 AD0 Start condition
Processing by slave device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn (When EXCn = 1) TRCn L Receive H H L L L Note IICn FFH Note
Note To cancel slave wait, write FFH to IICn or set WRELn. Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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Figure 18-19. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data
Processing by master device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn H Transmit L L H H H L L L IICn data IICn data
Transfer lines SCLn SDAn 8 D0 9 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 1 D7 2 D6 3 D5
Processing by slave device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn L Receive L L H H L L L Note Note IICn FFH Note IICn FFH Note
Note To cancel slave wait, write FFH to IICn or set WRELn. Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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Figure 18-19. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition
Processing by master device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn (When SPIEn = 1) TRCn H Transmit L H H IICn data IICn address
Transfer lines SCLn SDAn 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 Stop condition IICn FFH Note 9 1 2
AD6 AD5 Start condition
Processing by slave device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn H H L L L Note IICn FFH Note
Note
(When SPIEn = 1) TRCn L Receive
Note To cancel slave wait, write FFH to IICn or set WRELn. Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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Figure 18-20. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ address
Processing by master device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn Transfer lines SCLn SDAn 1 2 3 4 5 6 7 8 R 9 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 L Note H H IICn address IICn FFH Note
AD6 AD5 AD4 AD3 AD2 AD1 AD0 Start condition
Processing by slave device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn H H L L L L IICn data
Note To cancel master wait, write FFH to IICn or set WRELn. Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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Figure 18-20. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data
Processing by master device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn L Receive L L H H H L L Note Note IICn FFH Note IICn FFH Note
Transfer lines SCLn SDAn 8 D0 9 ACK 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 D5
Processing by slave device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn H Transmit L L H H L L L L IICn data IICn data
Note To cancel master wait, write FFH to IICn or set WRELn. Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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Figure 18-20. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition
Processing by master device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn (When SPIEn = 1) TRCn Transfer lines SCLn SDAn 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 N-ACK Stop condition Processing by slave device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn (When SPIEn = 1) TRCn H H L L L IICn data 1 2 Note H H IICn FFH Note IICn address
AD6 AD5 Start condition
Note Remark
To cancel master wait, write FFH to IICn or set WRELn. n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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19.1 Overview
The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 are provided with a dedicated interrupt controller (INTC) for interrupt servicing and realize a high-powered interrupt function that can service interrupt requests from a total of 33 to 45 sources. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution. The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 can process interrupt requests from the on-chip peripheral hardware and external sources. Moreover, exception processing can be started by the TRAP instruction (software exception) or by generation of an exception event (fetching of an illegal op code) (exception trap). 19.1.1 Features
Interrupt Source Interrupt function Non-maskable interrupt Maskable interrupt External Internal External Internal WDT1 TM0 TMH TM5 WT BRG UART CSI0 CSIA IIC KR AD Total Exception function Software exception V850ES/KF1 1 channel (NMI pin) 2 channels (WDT1, WDT2) 7 channels (all edge detection interrupts) 1 channel 4 channels 2 channels 2 channels 2 channels 1 channel 6 channels 2 channels 1 channel 1 channel 1 channel 1 channel 24 channels 1 channel 8 channels 2 channels 2 channels 2 channels 1 channel 6 channels 2 channels 2 channels 1 channel 1 channel 1 channel 29 channels 1 channel 12 channels 2 channels 2 channels 2 channels 1 channel 9 channels 3 channels 2 channels 2 channels 1 channel 1 channel 38 channels V850ES/KG1 V850ES/KJ1
16 channels (TRAP00H to TRAP0FH) 16 channels (TRAP10H to TRAP1FH)
Exception trap
2 channels (ILGOP/DBG0)
Tables 19-1 to 19-3 list the interrupt/exception sources.
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Table 19-1. Interrupt Source List (V850ES/KF1) (1/2)
Type Classification Default Priority Name Trigger Interrupt Exception S o urce C ode Handler Address Restored Interrupt PC Control Register U ndefined -
Reset
Interrupt
-
RESET
RESET pin input Internal reset input from WDT1, WDT2
Pin WDT1, WDT2 Pin WDT1
0000H
00000000H
Nonmaskable
Interrupt
- -
NMI INTWDT1
NMI pin valid edge input WDT1 overflow (when nonmaskable interrupt selected) WDT2 overflow (when nonmaskable interrupt selected)
0010H 0020H
00000010H 00000020H
Note 1 Note 1
- -
- Exc eption
INTWDT2
WDT2
0030H
00000030H
nextPC
-
Software exception
- - -
TRAP0nNote 2 TRAP instruction TRAP1n ILGOP/ DBG0
Note 2
- - -
004nHNote 2 00000040H 005nH
Note 2
nextPC nextPC nextPC
- - -
TRAP instruction Illegal op code/DBTRAP instruction
00000050H 00000060H
Exception Exc eption trap Maskable Interrupt
0060H
0
INTWDTM1 WDT1 overflow (when interval WDT1 timer selected) INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTTM000 INTTM001 INTTM010 INTTM011 INTTM50 INTTM51 INTCSI00 INTCSI01 INTSRE0 INTP0 pin valid edge input INTP1 pin valid edge input INTP2 pin valid edge input INTP3 pin valid edge input INTP4 pin valid edge input INTP5 pin valid edge input INTP6 pin valid edge input TM00 and CR000 match TM00 and CR001 match TM01 and CR010 match TM01 and CR011 match TM50 and CR50 match TM51 and CR51 match CSI00 transfer completion CSI01 transfer completion UART0 reception error occurrence UART0 reception completion Pin Pin Pin Pin Pin Pin Pin TM00 TM00 TM01 TM01 TM50 TM51 CSI00 CSI01 UART0
0080H
00000080H
nextPC
WDT1IC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0090H 00A0H 00B0H 00C0H 00D0H 00E0H 00F0H 0100H 0110H 0120H 0130H 0140H 0150H 0160H 0170H 0180H
00000090H
nextPC
PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 TM0IC00 TM0IC01 TM0IC10 TM0IC11 TM5IC0 TM5IC1 CSI0IC0 CSI0IC1 SREIC0
000000A0H nextPC 000000B0H nextPC 000000C0H nextPC 000000D0H nextPC 000000E0H nextPC 000000F0H nextPC 00000100H 00000110H 00000120H 00000130H 00000140H 00000150H 00000160H 00000170H 00000180H nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC
17
INTSR0
UART0
0190H
00000190H
nextPC
SRIC0
Notes 1. In the case of INTWDT1 and INTWDT2, restoration through the RETI instruction is not possible, so perform system reset following completion of interrupt servicing. 2. n = 0 to FH
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Table 19-1. Interrupt Source List (V850ES/KF1) (2/2)
Type Classification Default Priority Name Trigger Interrupt Exception S o urce C ode Handler Address Restored Interrupt PC Control Register nextPC STIC0
Maskable
Interrupt
18
INTST0
UART0 transmission completion UART1 reception error occurrence UART1 reception completion UART1 transmission completion TMH0 and CMP00/CMP01 match TMH1 and CMP10/CMP11 match CSIA0 transfer completion I C0 transfer completion A/D conversion completion Key return interrupt Watch timer interval Watch timer reference time Watch counter BRG and PRSCM match
2
UART0
01A0H
000001AH
19
INTSRE1
UART1
01B0H
000001B0H nextPC
SREIC1
20 21
INTSR1 INTST1
UART1 UART1
01C0H 01D0H
000001C0H nextPC 000001D0H nextPC
SRIC1 STIC1
22
INTTMH0
TMH0
01E0H
000001E0H nextPC
TMHIC0
23
INTTMH1
TMH1
01F0H
000001F0H nextPC
TMHIC1
24 25 26 27 28 29 30
INTCSIA0 INTIIC0 INTAD INTKR INTWTI INTWT INTBRG
Note
CSIA0 I C0 A/D KR WT WT BRG
2
0200H 0210H 0220H 0230H 0240H 0250H 0260H
00000200H 00000210H 00000220H 00000230H 00000240H 00000250H 00000260H
nextPC nextPC nextPC nextPC nextPC nextPC nextPC
CSIAIC0 IICIC0 ADIC KRIC WTIIC WTIC BRGIC
Note Only for the PD703208Y, 703209Y, 703210Y, and 70F3210Y Remarks 1. Default priority: The priority order when two or more maskable interrupt requests with the same priority level are generated at the same time. The highest priority is 0. Restored PC: The value of the program counter (PC) saved to EIPC or FEPC when interrupt/exception processing is started. The restored PC when a non-maskable or maskable interrupt is acknowledged while either of the following instructions is being executed does not become nextPC (when an interrupt is acknowledged during the execution of an instruction, the execution of that instruction is stopped and is resumed following completion of interrupt servicing). * Load instructions (SLD.B, SLD.BU, SLD.H, SLD.HU, SLD.W) * Divide instructions (DIV, DIVH, DIVU, DIVHU) * PREPARE, DISPOSE instructions (only when an interrupt occurs before stack pointer update) nextPC: The PC value at which processing is started following interrupt/exception processing. 2. The execution address of the illegal op code when an illegal op code exception occurs is calculated with (Restored PC - 4).
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Table 19-2. Interrupt Source List (V850ES/KG1) (1/2)
Type Classification Default Priority Name Trigger Interrupt Exception S o urce C ode Handler Address Restored Interrupt PC Control Register U ndefined -
Reset
Interrupt
-
RESET
RESET pin input Internal reset input from WDT1, WDT2
Pin WDT1, WDT2 Pin WDT1
0000H
00000000H
Nonmaskable
Interrupt
- -
NMI INTWDT1
NMI pin valid edge input WDT1 overflow (when nonmaskable interrupt selected) WDT2 overflow (when nonmaskable interrupt selected)
0010H 0020H
00000010H 00000020H
nextPC Note 1
- -
-
INTWDT2
WDT2
0030H
00000020H
Note 1
-
Software exception
Exception
- - -
TRAP0nNote 2 TRAP instruction TRAP1n ILGOP/ DBG0
Note 2
- - -
004nHNote 2 00000040H 005nH
Note 2
nextPC nextPC nextPC
- - -
TRAP instruction Illegal op code/DBTRAP instruction
00000050H 00000060H
Exception Exception trap Maskable Interrupt
0060H
0
INTWDTM1 WDT1 overflow (when interval WDT1 timer selected) INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTTM000 INTTM001 INTTM010 INTTM011 INTTM50 INTTM51 INTCSI00 INTCSI01 INTSRE0 INTP0 pin valid edge input INTP1 pin valid edge input INTP2 pin valid edge input INTP3 pin valid edge input INTP4 pin valid edge input INTP5 pin valid edge input INTP6 pin valid edge input TM00 and CR000 match TM00 and CR001 match TM01 and CR010 match TM01 and CR011 match TM50 and CR50 match TM51 and CR51 match CSI00 transfer completion CSI01 transfer completion UART0 reception error occurrence UART0 reception completion Pin Pin Pin Pin Pin Pin Pin TM00 TM00 TM01 TM01 TM50 TM51 CSI00 CSI01 UART0
0080H
00000080H
nextPC
WDT1IC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0090H 00A0H 00B0H 00C0H 00D0H 00E0H 00F0H 0100H 0110H 0120H 0130H 0140H 0150H 0160H 0170H 0180H
00000090H
nextPC
PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 TM0IC00 TM0IC01 TM0IC10 TM0IC11 TM5IC0 TM5IC1 CSI0IC0 CSI0IC1 SREIC0
000000A0H nextPC 000000B0H nextPC 000000C0H nextPC 000000D0H nextPC 000000E0H nextPC 000000F0H nextPC 00000100H 00000110H 00000120H 00000130H 00000140H 00000150H 00000160H 00000170H 00000180H nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC
17
INTSR0
UART0
0190H
00000190H
nextPC
SRIC0
Notes 1. In the case of INTWDT1 and INTWDT2, restoration through the RETI instruction is not possible, so perform system reset following completion of interrupt servicing. 2. n = 0 to FH
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Table 19-2. Interrupt Source List (V850ES/KG1) (2/2)
Type Classification Default Priority Name Trigger Interrupt Exception S o urce C ode Handler Address Restored Interrupt PC Control Register nextPC STIC0
Maskable
Interrupt
18
INTST0
UART0 transmission completion UART1 reception error occurrence UART1 reception completion UART1 transmission completion TMH0 and CMP00/CMP01 match TMH1 and CMP10/CMP11 match CSIA0 transfer completion I C0 transfer completion A/D conversion completion Key return interrupt Watch timer interval Watch timer reference time Watch counter BRG and PRSCM match TM02 and CR020 match TM02 and CR021 match TM03 and CR030 match TM03 and CR031 match CSIA1 transfer completion
2
UART0
01A0H
000001AH
19
INTSRE1
UART1
01B0H
000001B0H nextPC
SREIC1
20 21
INTSR1 INTST1
UART1 UART1
01C0H 01D0H
000001C0H nextPC 000001D0H nextPC
SRIC1 STIC1
22
INTTMH0
TMH0
01E0H
000001E0H nextPC
TMHIC0
23
INTTMH1
TMH1
01F0H
000001F0H nextPC
TMHIC1
24 25 26 27 28 29 30
INTCSIA0 INTIIC0 INTAD INTKR INTWTI INTWT INTBRG
Note 1
CSIA0 I C0 A/D KR WT WT BRG
2
0200H 0210H 0220H 0230H 0240H 0250H 0260H
00000200H 00000210H 00000220H 00000230H 00000240H 00000250H 00000260H
nextPC nextPC nextPC nextPC nextPC nextPC nextPC
CSIAIC0 IICIC0 ADIC KRIC WTIIC WTIC BRGIC
31 32 33 34 35
INTTM020 INTTM021 INTTM030 INTTM031 INTCSIA1
TM02 TM02 TM03 TM03 CSIA1
0270H 0280H 0290H 02A0H 02B0H
00000270H 00000280H 00000290H
nextPC nextPC nextPC
TM0IC20 TM0IC21 TM0IC30 TM0IC31 CSIAIC1
000002A0H nextPC 000002B0H nextPC
Note Only for the PD703212Y, 703213Y, 703214Y, and 70F3214Y Remarks 1. Default priority: The priority order when two or more maskable interrupt requests with the same priority level are generated at the same time. The highest priority is 0. Restored PC: The value of the program counter (PC) saved to EIPC or FEPC when interrupt/exception processing is started. The restored PC when a non-maskable or maskable interrupt is acknowledged while either of the following instructions is being executed does not become nextPC (when an interrupt is acknowledged during the execution of an instruction, the execution of that instruction is stopped and is resumed following completion of interrupt servicing). * Load instructions (SLD.B, SLD.BU, SLD.H, SLD.HU, SLD.W) * Divide instructions (DIV, DIVH, DIVU, DIVHU) * PREPARE, DISPOSE instructions (only when an interrupt occurs before stack pointer update) nextPC: The PC value at which processing is started following interrupt/exception processing. 2. The execution address of the illegal op code when an illegal op code exception occurs is calculated with (Restored PC - 4).
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Table 19-3. Interrupt Source List (V850ES/KJ1) (1/2)
Type Classification Default Priority Name Trigger Interrupt Exception S o urce C ode Handler Address Restored Interrupt PC Control Register U ndefined -
Reset
Interrupt
-
RESET
RESET pin input Internal reset input from WDT1, WDT2
Pin WDT1 WDT2 Pin WDT1
0000H
00000000H
Nonmaskable
Interrupt
- -
NMI INTWDT1
NMI pin valid edge input WDT1 overflow (when nonmaskable interrupt selected) WDT2 overflow (when nonmaskable interrupt selected)
0010H 0020H
00000010H 00000020H
nextPC Note 1
- -
-
INTWDT2
WDT2
0030H
00000020H
Note 1
-
Software exception
Exception
- - -
TRAP0nNote 2 TRAP instruction TRAP1n ILGOP/ DBG0
Note 2
- - -
004nHNote 2 00000040H 005nH
Note 2
nextPC nextPC nextPC
- - -
TRAP instruction Illegal op code/DBTRAP instruction
00000050H 00000060H
Exception Exception trap Maskable Interrupt
0060H
0
INTWDTM1 WDT1 overflow (when interval WDT1 timer selected) INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTTM000 INTTM001 INTTM010 INTTM011 INTTM50 INTTM51 INTCSI00 INTCSI01 INTSRE0 INTP0 pin valid edge input INTP1 pin valid edge input INTP2 pin valid edge input INTP3 pin valid edge input INTP4 pin valid edge input INTP5 pin valid edge input INTP6 pin valid edge input TM00 and CR000 match TM00 and CR001 match TM01 and CR010 match TM01 and CR011 match TM50 and CR50 match TM51 and CR51 match CSI00 transfer completion CSI01 transfer completion UART0 reception error occurrence UART0 reception completion UART0 transmission completion Pin Pin Pin Pin Pin Pin Pin TM00 TM00 TM01 TM01 TM50 TM51 CSI00 CSI01 UART0
0080H
00000080H
nextPC
WDT1IC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0090H 00A0H 00B0H 00C0H 00D0H 00E0H 00F0H 0100H 0110H 0120H 0130H 0140H 0150H 0160H 0170H 0180H
00000090H
nextPC
PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 TM0IC00 TM0IC01 TM0IC10 TM0IC11 TM5IC0 TM5IC1 CSI0IC0 CSI0IC1 SREIC0
000000A0H nextPC 000000B0H nextPC 000000C0H nextPC 000000D0H nextPC 000000E0H nextPC 000000F0H nextPC 00000100H 00000110H 00000120H 00000130H 00000140H 00000150H 00000160H 00000170H 00000180H nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC
17 18
INTSR0 INTST0
UART0 UART0
0190H 01A0H
00000190H 000001AH
nextPC nextPC
SRIC0 STIC0
Notes 1. In the case of INTWDT1 and INTWDT2, restoration through the RETI instruction is not possible, so perform system reset following completion of interrupt servicing. 2. n = 0 to FH
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Table 19-3. Interrupt Source List (V850ES/KJ1) (2/2)
Type Classification Default Priority Interrupt 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Name Trigger Interrupt Exception S o urce C ode UART1 UART1 UART1 TMH0 TMH1 CSIA0 I2C0 A/D KR WT WT BRG TM02 TM02 TM03 TM03 CSIA1 TM04 TM04 TM05 TM05 CSI02 UART2 UART2 UART2 I2C1 01B0H 01C0H 01D0H 01E0H 01F0H 0200H 0210H 0220H 0230H 0240H 0250H 0260H 0270H 0280H 0290H 02A0H 02B0H 02C0H 02D0H 02E0H 02F0H 0300H 0310H 0320H 0330H 0340H Handler Address Restored Interrupt PC Control Register SREIC1 SRIC1 STIC1 TMHIC0 TMHIC1 CSIAIC0 IICIC0 ADIC KRIC WTIIC WTIC BRGIC TM0IC20 TM0IC21 TM0IC30 TM0IC31 CSIAIC1 TM0IC40 TM0IC41 TM0IC50 TM0IC51 CSI0IC2 SREIC2 SRIC2 STIC2 IICIC1
Maskable
INTSRE1 INTSR1 INTST1 INTTMH0 INTTMH1 INTCSIA0 INTIIC0Note INTAD INTKR INTWTI INTWT INTBRG INTTM020 INTTM021 INTTM030 INTTM031 INTCSIA1 INTTM040 INTTM041 INTTM050 INTTM051 INTCSI02 INTSRE2 INTSR2 INTST2 INTIIC1Note
UART1 reception error occurrence UART1 reception completion UART1 transmission completion TMH0 and CMP00/CMP01 match TMH1 and CMP10/CMP11 match CSIA0 transfer completion I2C0 transfer completion A/D conversion completion Key return interrupt Watch timer interval Watch timer reference time Watch counter BRG and PRSCM match TM02 and CR020 match TM02 and CR021 match TM03 and CR030 match TM03 and CR031 match CSIA1 transfer completion TM04 and CR040 match TM04 and CR041 match TM05 and CR050 match TM05 and CR051 match CSI02 transfer completion UART2 reception error occurrence UART2 reception completion UART2 transmission completion I2C1 transfer completion
000001B0H nextPC 000001C0H nextPC 000001D0H nextPC 000001E0H nextPC 000001F0H nextPC 00000200H 00000210H 00000220H 00000230H 00000240H 00000250H 00000260H 00000270H 00000280H 00000290H 000002A0H 000002B0H 000002C0H 000002D0H 000002E0H 000002F0H 00000300H 00000310H 00000320H 00000330H 00000340H nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC
Note Only for the PD703216Y, 703217Y, and 70F3217Y Remarks 1. Default priority: The priority order when two or more maskable interrupt requests with the same priority level are generated at the same time. The highest priority is 0. Restored PC: The value of the program counter (PC) saved to EIPC or FEPC when interrupt/exception processing is started. The restored PC when a non-maskable or maskable interrupt is acknowledged while either of the following instructions is being executed does not become nextPC (when an interrupt is acknowledged during the execution of an instruction, the execution of that instruction is stopped and is resumed following completion of interrupt servicing). * Load instructions (SLD.B, SLD.BU, SLD.H, SLD.HU, SLD.W) * Divide instructions (DIV, DIVH, DIVU, DIVHU) * PREPARE, DISPOSE instructions (only when an interrupt occurs before stack pointer update) nextPC: The PC value at which processing is started following interrupt/exception processing. 2. The execution address of the illegal op code when an illegal op code exception occurs is calculated with (Restored PC - 4).
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19.2 Non-Maskable Interrupts
Non-maskable interrupt requests are acknowledged unconditionally, even when interrupts are disabled (DI state). Non-maskable interrupts (NMI) are not subject to priority control and take precedence over all other interrupt requests. The following three types of non-maskable interrupt requests are available in the V850ES/KF1, V850ES/KG1, and V850ES/KJ1. * NMI pin input (NMI) * Non-maskable interrupt request due to overflow of watchdog timer 1 (INTWDT1) * Non-maskable interrupt request due to overflow of watchdog timer 2 (INTWDT2) There are four choices for the valid edge of an NMI pin, namely: rising edge, falling edge, both edges, and no edge detection. The non-maskable interrupt due to overflow of watchdog timer 1 (INTWDT1) functions by setting the WDTN14 and WDTM13 bits of watchdog timer mode register 1 (WDTM1) to 10. The non-maskable interrupt due to overflow of watchdog timer 2 (INTWDT2) functions by setting the WDTN21 and WDTM20 bits of watchdog timer mode register 1 (WDTM1) to 01. When two or more non-maskable interrupts occur simultaneously, they are processed in a sequence determined by the following priority order (the interrupt requests with low priority level are ignored). INTWDT2 > INTWDT1 > NMI If during NMI processing, an NMI, INTWDT1, or INTWDT2 request newly occurs, processing is performed as follows. (1) If an NMI request newly occurs during NMI processing The new NMI request is held pending regardless of the value of the NP bit of the program status word (PSW) of the CPU. The NMI request held pending is acknowledged upon completion of processing of the NMI currently being executed (following RETI instruction execution). (2) If an INTWDT1 request newly occurs during NMI processing If the NP bit of PSW remains set (to 1) during NMI processing, the new INTWDT1 request is held pending. The INTWDT1 request held pending is acknowledged upon completion of processing of the NMI currently being executed (following RETI instruction execution). If the NP bit of PSW is cleared (to 0) during NMI processing, a newly generated INTWDT1 request is executed (NMI processing is interrupted). (3) If an INTWDT2 request newly occurs during NMI processing A newly generated INTWDT2 request is executed regardless of the value of the NP bit of PSW (NMI processing is interrupted). Caution When a non-maskable interrupt request is generated, the PC and PSW values are saved to the NMI occurrence status save registers (FEPC, FEPSW), but only NMIs can be restored via the RETI instruction at this time. In the case of INTWDT1 and INTWDT2, restoration through the RETI instruction is not possible, so perform system reset following completion of interrupt servicing.
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Figure 19-1. Acknowledging Non-Maskable Interrupt Requests (1/2)
(a) If two or more NMI requests are simultaneously generated
* NMI and INTWDT1 requests simultaneously generated
* NMI and INTWDT2 requests simultaneously generated
Main routine INTWDT1 processing NMI, INTWDT1 request (simultaneously generated)
Main routine INTWDT2 processing NMI, INTWDT2 request (simultaneously generated)
System reset
System reset
* INTWDT1 and INTWDT2 requests simultaneously generated
* NMI, INTWDT1, and INTWDT2 requests simultaneously generated
Main routine INTWDT2 processing INTWDT1, INTWDT2 request (simultaneously generated)
Main routine INTWDT2 processing NMI, INTWDT1, INTWDT2 requests (simultaneously generated)
System reset
System reset
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Figure 19-1. Acknowledging Non-Maskable Interrupt Requests (2/2)
(b) If a new NMI request is generated during a non-maskable interrupt servicing
Non-maskable interrupt currently being serviced NMI Non-maskable interrupt request newly generated during non-maskable interrupt servicing NMI * Generation of NMI request during NMI processing INTWDT1 INTWDT2
* Generation of INTWDT request during NMI processing * Generation of INTWDT2 request during NMI processing (NP = 1 state prior to INTWDT request is maintained)
Main routine NMI processing NMI request(Hold pending) (Held pending) NMI processing NMI request INTWDT request(Hold pending) INTWDT processing NMI request INTWDT2 request Main routine NMI processing NMI request Main routine NMI processing INTWDT2 processing
System reset
System reset
* Generation of INTWDT request during NMI processing (Set NP = 0 before INTWDT request)
Main routine NP = 0 NMI request INTWDT request
NMI processing
INTWDT processing
System reset
* Generation of INTWDT request during NMI processing (Set NP = 0 after INTWDT request)
Main routine
NMI processing INTWDT(Hold pending) request NP = 0
INTWDT processing
NMI request
System reset
INTWDT1 * Generation of NMI request during INTWDT processing * Generation of INTWDT request during INTWDT processing * Generation of INTWDT2 request during INTWDT1 processing
Main routine INTWDT processing INTWDT request NMI request(Invalid) System reset
Main routine INTWDT processing INTWDT request INTWDT(Invalid) request System reset INTWDT1 request System reset Main routine INTWDT1 processing INTWDT2 processing
INTWDT2 * Generation of NMI request during INTWDT2 processing
* Generation of INTWDT1 request during INTWDT2 processing * Generation of INTWDT2 request during INTWDT2 processing
Main routine INTWDT2 processing INTWDT2 request NMI request(Invalid) System reset
Main routine INTWDT2 processing INTWDT1(Invalid) request System reset
Main routine INTWDT2 processing INTWDT2(Invalid) request System reset
INTWDT2 request
INTWDT2 request
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19.2.1 Operation Upon generation of a non-maskable interrupt request, the CPU performs the following processing and transfers control to a handler routine. <1> Saves the restored PC to FEPC. <2> Saves the current PSW to FEPSW. <3> Writes the exception code 0010H to the higher halfword (FECC) of ECR. <4> Sets the NP and ID bits of the PSW and clears the EP bit. <5> Loads the handler address of the non-maskable interrupt to the PC and transfers control. Figure 19-2. Non-Maskable Interrupt Servicing
NMI input
INTC acknowledged Non-maskable interrupt request
CPU processing PSW. NP 0 1
FEPC FEPSW ECR. FECC PSW. NP PSW. EP PSW. ID PC
Restored PC PSW Exception code 1 0 1 Handler address
Interrupt request held pending
Interrupt servicing
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19.2.2 Restore Execution is restored from non-maskable interrupt servicing by the RETI instruction. (1) In case of NMI Restore from NMI processing is done with the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC. (i) Loads the values of the restored PC and PSW from FEPC and FEPSW, respectively, because the EP bit and NP bit of the PSW are 0 and 1, respectively. (ii) Transfers control back to the loaded address of the restored PC and PSW. Figure 19-3 shows the processing flow of the RETI instruction. Figure 19-3. RETI Instruction Processing
RETI instruction
1
PSW.EP 0 PSW.NP 0 1
PC PSW
EIPC EIPSW
PC PSW
FEPC FEPSW
Original processing restored
Caution When the PSW.EP bit and PSW.NP bit are changed by the LDSR instruction during nonmaskable interrupt servicing, in order to restore the PC and PSW correctly during restoring by the RETI instruction, it is necessary to set PSW.EP back to 0 and PSW.NP back to 1 using the LDSR instruction immediately before the RETI instruction. Remark The solid line shows the CPU processing flow.
(2) In case of INTWDT1, INTWDT2 Restoring with the RETI instruction is not performed. Perform system reset following the completion of interrupt servicing.
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19.2.3 NP flag The NP flag is a status flag that indicates that non-maskable interrupt servicing is in progress. This flag is set when a non-maskable interrupt request has been acknowledged, and masks all non-maskable requests to prevent multiple interrupts.
After reset : 00000020H
PSW
0
NP
EP
ID SAT CY OV
S
Z
NP 0 1
NMI servicing status No non-maskable interrupt servicing Non-maskable interrupt serving in progress
19.2.4 Noise elimination for NMI pin NMI pin noise is eliminated by a on-chip noise eliminator that uses analog delay. Therefore, a signal input to the NMI pin is not detected as an edge unless it maintains its input level for a certain period. The edge is detected only after a certain period has elapsed. The NMI pin is used for releasing the STOP mode. In the STOP mode, noise elimination using the system clock is not performed because the internal system clock is stopped.
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19.2.5 Edge detection function for NMI pin The NMI valid edge can be selected from the following four types: falling edge, rising edge, both edges, and no edge detection. Rising edge specification register 0 (INTR0) and falling edge specification register 0 (INTF0) specify the valid edge of non-maskable interrupts (NMI). These two registers can be read/written in 8-bit or 1-bit units. After reset, the edge detection for the NMI pin is set to "no edge detection". Therefore, the NMI pin functions as a normal port and interrupt requests cannot be acknowledged unless a valid edge is specified by the INTF0 and INTR0 registers. When using P02 as an output port, set the NMI pin valid edge to "no edge detection". (1) External interrupt rising edge specification register 0 (INTR0) This is an 8-bit register that specifies the rising edge of the NMI pin. This register can be read/written in 8-bit or 1-bit units. Caution When switching to the port function from the external interrupt function (alternate function), edge detection may be performed. Therefore, set the port mode after setting INTF0n = INTR0n = 0.
After reset : 00H
R/W
Address : FFFFFC20H
INTR0
0
INTR06
INTR05
INTR04
INTR03
INTR02
0
0
Remark
For specification of the valid edge, refer to Table 19-4.
(2) External interrupt falling edge specification register 0 (INTF0) This is an 8-bit register that specifies the falling edge of the NMI pin. This register can be read/written in 8-bit or 1-bit units. Caution When switching to the port function from the external interrupt function (alternate function), edge detection may be performed. Therefore, set the port mode after setting INTF0n = INTR0n = 0.
After reset : 00H
R/W
Address : FFFFFC00H
INTF0
0
INTF06
INTF05
INTF04
INTF03
INTF02
0
0
Remark
For specification of the valid edge, refer to Table 19-4.
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Table 19-4. NMI Valid Edge Specification
INTF02 0 0 1 1 INTR02 0 1 0 1 NMI Valid Edge Specification No edge detection Rising edge Falling edge Both edges
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19.3 Maskable Interrupts
Maskable interrupt requests can be masked by interrupt control registers. The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 have 33 to 45 maskable interrupt sources (refer to 19.1.1 Features). If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority. In addition to the default priority, eight levels of interrupt priorities can be specified by using the interrupt control registers, allowing programmable priority control. When an interrupt request has been acknowledged, the interrupt disabled (DI) status is set and the acknowledgement of other maskable interrupts is disabled. When the EI instruction is executed in an interrupt servicing routine, the interrupt enabled (EI) status is set, which enables acknowledgement of interrupts having a priority higher than that of the interrupt request currently in progress. Note that only interrupts with a higher priority have this capability; interrupts with the same priority level cannot be nested. To use multiple interrupts, it is necessary to save EIPC and EIPSW to memory or a register before executing the EI instruction, and restore EIPC and EIPSW to the original values by executing the DI instruction before the RETI instruction. When the WDTM14 bit of watchdog timer mode register 1 (WDTM1) is set to 0, the watchdog timer overflow interrupt functions as a maskable interrupt (INTWDTM1). 19.3.1 Operation If a maskable interrupt request is generated, the CPU performs the following processing and transfers control to a handler routine. <1> Saves the restored PC to EIPC. <2> Saves the current PSW to EIPSW. <3> Writes an exception code to the lower halfword of ECR (EICC). <4> Sets the ID bit of the PSW and clears the EP bit. <5> Loads the corresponding handler address to the PC and transfers control. The maskable interrupt request masked by INTC and the maskable interrupt request that occurs while another interrupt is being serviced (when PSW.NP = 1 or PSW.ID = 1) are held pending internally. When the interrupts are unmasked, or when PSW.NP = 0 and PSW.ID = 0 by using the RETI and LDSR instructions, a new maskable interrupt servicing is started in accordance with the priority of the pending maskable interrupt request. Figure 19-4 shows the servicing flow for maskable interrupts.
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Figure 19-4. Maskable Interrupt Servicing
INT input
Interrupt mask released? Yes INTC acknowledged Priority higher than that of interrupt currently being serviced? Yes Priority higher than that of other interrupt requests? Yes Highest default priority of interrupt requests with the same priority? Yes Maskable interrupt request
No
No
No
No
Interrupt request pending
1 PSW. NP 0 1 PSW. ID CPU processing EIPC EIPSW ECR. EICC PSW. EP PSW. ID PC 0 Restored PC PSW Exception code 0 1 Handler address Interrupt request pending
Interrupt servicing
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19.3.2 Restore Execution is restored from maskable interrupt servicing by the RETI instruction. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC. (1) Loads the values of the restored PC and PSW from EIPC and EIPSW because the EP bit and NP bit of the PSW are both 0. (2) Transfers control to the loaded address of the restored PC and PSW. Figure 19-5 shows the processing flow of the RETI instruction. Figure 19-5. RETI Instruction Processing
RETI instruction
1 PSW. EP 0 1
PSW. NP 0
PC PSW
EIPC EIPSW
PC PSW
FEPC FEPSW
Original processing restored
Caution When the PSW.EP bit and PSW.NP bit are changed by the LDSR instruction during maskable interrupt servicing, in order to restore the PC and PSW correctly during restoring by the RETI instruction, it is necessary to set PSW.EP back to 0 and PSW.NP back to 0 using the LDSR instruction immediately before the RETI instruction. Remark The solid line shows the CPU processing flow.
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19.3.3 Priorities of maskable interrupts The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 provide a multiple interrupt servicing in which an interrupt can be acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels specified by the interrupt priority level specification bit (xxPRn). When two or more interrupts having the same priority level specified by xxPRn are generated at the same time, interrupts are serviced in order depending on the priority level allocated to each interrupt request (default priority level) beforehand. For more information, refer to Tables 19-1, 19-2, and 19-3 Interrupt Sources. Programmable priority control divides interrupt requests into eight levels by setting the priority level specification flag. Note that when an interrupt request is acknowledged, the ID flag of the PSW is automatically set (1). Therefore, when multiple interrupts are to be used, clear (0) the ID flag beforehand (for example, by placing the EI instruction into the interrupt service program) to enable interrupts.
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Figure 19-6. Example of Interrupt Nesting (1/2)
Main routine Servicing of a EI Interrupt request a (level 3) EI Interrupt request b (level 2) Interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. Servicing of b
Servicing of c
Interrupt request c (level 3)
Interrupt request d (level 2) Although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled.
Servicing of d
Servicing of e EI Interrupt request e (level 2) Interrupt request f (level 3) Interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. Servicing of f
Servicing of g EI Interrupt request g (level 1) Interrupt request h (level 1) Servicing of h
Interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g.
Caution The values of EIPC and EIPSW must be saved before executing multiple interrupts. Remarks 1. a to u in the figure are the names of interrupt requests shown for the sake of explanation. 2. The default priority in the figure indicates the relative priority between two interrupt requests.
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Figure 19-6. Example of Interrupt Nesting (2/2)
Main routine Servicing of i EI Interrupt request i (level 2) Interrupt request j (level 3) Interrupt request k (level 1) EI Servicing of k
Interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority.
Servicing of j
Servicing of l Interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status.
Interrupt request l (level 2)
Interrupt request m (level 3) Interrupt request n (level 1) Servicing of n
Pending interrupt requests are acknowledged after servicing of interrupt request l. At this time, interrupt requests n is acknowledged first even though m has occurred first because the priority of n is higher than that of m.
Servicing of m
Interrupt request o (level 3)
Servicing of o Servicing of p EI Servicing of q EI Servicing of r EI Interrupt request p Interrupt request q EI (level 2) Interrupt request r (level 1) (level 0)
If levels 3 to 0 are acknowledged Servicing of s Pending interrupt requests t and u are acknowledged after processing of s. Because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. Servicing of u
Interrupt request s (level 1)
Interrupt request t (level 2)Note 1 Interrupt request u (level 2)Note 2
Servicing of t
Notes 1. Lower default priority 2. Higher default priority
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Figure 19-7. Example of Servicing Simultaneously Generated Interrupt Requests
Main routine EI Interrupt request a (level 2) Interrupt request b (level 1)Note 1 Interrupt request c (level 1)Note 2 Servicing of interrupt request b *Interrupt requests b and c are acknowledged first according to their priorities. *Because the priorities of b and c are the same, b is acknowledged first because it has the higher default priority.
Servicing of interrupt request c
Servicing of interrupt request a
Notes 1. Higher default priority 2. Lower default priority
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19.3.4 Interrupt control register (xxlCn) An interrupt control register is assigned to each maskable interrupt and sets the control conditions for each maskable interrupt request. The interrupt control registers can be read/written in 8-bit or 1-bit units. Caution Be sure to read the xxIFn bit of the xxICn register while interrupts are disabled (DI). If the xxIFn bit is read while interrupts are enabled (EI), an incorrect value may be read if there is a conflict between acknowledgement of the interrupt and reading of the bit.
After reset: 47H <> xxICn xxIFn
R/W <> xxMKn
Address: FFFFF110H to FFFFF168H
0
0
0
xxPRn2
xxPRn1
xxPRn0
xxIFn 0 1
Interrupt request flagNote Interrupt request not generated Interrupt request generated
xxMKn 0 1 Enables interrupt servicing
Interrupt mask flag
Disables interrupt servicing (pending)
xxPRn2 0 0 0 0 1 1 1 1
xxPRn1 0 0 1 1 0 0 1 1
xxPRn0 0 1 0 1 0 1 0 1
Interrupt priority specification bit Specifies level 0 (highest) Specifies level 1 Specifies level 2 Specifies level 3 Specifies level 4 Specifies level 5 Specifies level 6 Specifies level 7 (lowest)
Note Automatically reset by hardware when interrupt request is acknowledged. Remark xx: Identifying name of each peripheral unit (CSI0, TM5, TM0, P, WDT, BRG, WT, WTI, KR, AD, IIC, CSIA, TMH, ST, SR, SRE) n: Peripheral unit number (See Tables 19-5 to 19-7.)
Following tables list the addresses and bits of the interrupt control registers.
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Table 19-5. Interrupt Control Registers (xxlCn) (V850ES/KF1)
Address Register <7> FFFFF110H FFFFF112H FFFFF114H FFFFF116H FFFFF118H FFFFF11AH FFFFF11CH FFFFF11EH FFFFF120H FFFFF122H FFFFF124H FFFFF126H FFFFF128H FFFFF12AH FFFFF12CH FFFFF12EH FFFFF130H FFFFF132H FFFFF134H FFFFF136H FFFFF138H FFFFF13AH FFFFF13CH FFFFF13EH FFFFF140H FFFFF142H FFFFF144H FFFFF146H FFFFF148H FFFFF14AH FFFFF14CH WDT1IC PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 TM0IC00 TM0IC01 TM0IC10 TM0IC11 TM5IC0 TM5IC1 CSI0IC0 CSI0IC1 SREIC0 SRIC0 STIC0 SREIC1 SRIC1 STIC1 TMHIC0 TMHIC1 CSIAIC0 IICIC0 ADIC KRIC WTIIC WTIC BRGIC
Note
Bits <6> WDT1MK PMK0 PMK1 PMK2 PMK3 PMK4 PMK5 PMK6 TM0MK00 TM0MK01 TM0MK10 TM0MK11 TM5MK0 TM5MK1 CSI0MK0 CSI0MK1 SREMK0 SRMK0 STMK0 SREMK1 SRMK1 STMK1 TMHMK0 TMHMK1 CSIAMK0 IICMK0 ADMK KRMK WTIIMK WTMK BRGMK 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0
WDT1IF PIF0 PIF1 PIF2 PIF3 PIF4 PIF5 PIF6 TM0IF00 TM0IF01 TM0IF10 TM0IF11 TM5IF0 TM5IF1 CSI0IF0 CSI0IF1 SREIF0 SRIF0 STIF0 SREIF1 SRIF1 STIF1 TMHIF0 TMHIF1 CSIAIF0 IICIF0 ADIF KRIF WTIIF WTIF BRGIF
WDT1PR2 WDT1PR1 WDT1PR0 PPR02 PPR12 PPR22 PPR32 PPR42 PPR52 PPR62 PPR01 PPR11 PPR21 PPR31 PPR41 PPR51 PPR61 PPR00 PPR10 PPR20 PPR30 PPR40 PPR50 PPR60
TM0PR002 TM0PR001 TM0PR000 TM0PR012 TM0PR011 TM0PR010 TM0PR102 TM0PR101 TM0PR100 TM0PR112 TM0PR111 TM0PR110 TM5PR02 TM5PR12 TM5PR01 TM5PR11 TM5PR00 TM5PR10
CSI0PR02 CSI0PR01 CSI0PR00 CSI0PR12 CSI0PR11 CSI0PR10 SREPR02 SRPR02 STPR02 SREPR12 SRPR12 STPR12 SREPR01 SRPR01 STPR01 SREPR11 SRPR11 STPR11 SREPR00 SRPR00 STPR00 SREPR10 SRPR10 STPR10
TMHPR02 TMHPR01 TMHPR00 TMHPR12 TMHPR11 TMHPR10 CSIAPR02 CSIAPR01 CSIAPR00 IICPR02 ADPR2 KRPR2 WTIPR2 WTPR2 BRGPR2 IICPR01 ADPR1 KRPR1 WTIPR1 WTPR1 BRGPR1 IICPR00 ADPR0 KRPR0 WTIPR0 WTPR0 BRGPR0
Note Only for the PD703208Y, 703209Y, 703210Y, and 70F3210Y
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Table 19-6. Interrupt Control Registers (xxlCn) (V850ES/KG1)
Address Register <7> FFFFF110H FFFFF112H FFFFF114H FFFFF116H FFFFF118H FFFFF11AH FFFFF11CH FFFFF11EH FFFFF120H FFFFF122H FFFFF124H FFFFF126H FFFFF128H FFFFF12AH FFFFF12CH FFFFF12EH FFFFF130H FFFFF132H FFFFF134H FFFFF136H FFFFF138H FFFFF13AH FFFFF13CH FFFFF13EH FFFFF140H FFFFF142H FFFFF144H FFFFF146H FFFFF148H FFFFF14AH FFFFF14CH FFFFF14EH FFFFF150H FFFFF152H FFFFF154H FFFFF156H WDT1IC PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 TM0IC00 TM0IC01 TM0IC10 TM0IC11 TM5IC0 TM5IC1 CSI0IC0 CSI0IC1 SREIC0 SRIC0 STIC0 SREIC1 SRIC1 STIC1 TMHIC0 TMHIC1 CSIAIC0 IICIC0 ADIC KRIC WTIIC WTIC BRGIC TM0IC20 TM0IC21 TM0IC30 TM0IC31 CSIAIC1
Note
Bits <6> WDT1MK PMK0 PMK1 PMK2 PMK3 PMK4 PMK5 PMK6 TM0MK00 TM0MK01 TM0MK10 TM0MK11 TM5MK0 TM5MK1 CSI0MK0 CSI0MK1 SREMK0 SRMK0 STMK0 SREMK1 SRMK1 STMK1 TMHMK0 TMHMK1 CSIAMK0 IICMK0 ADMK KRMK WTIIMK WTMK BRGMK TM0MK20 TM0MK21 TM0MK30 TM0MK31 CSIAMK1 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0
WDT1IF PIF0 PIF1 PIF2 PIF3 PIF4 PIF5 PIF6 TM0IF00 TM0IF01 TM0IF10 TM0IF11 TM5IF0 TM5IF1 CSI0IF0 CSI0IF1 SREIF0 SRIF0 STIF0 SREIF1 SRIF1 STIF1 TMHIF0 TMHIF1 CSIAIF0 IICIF0 ADIF KRIF WTIIF WTF BRGIF TM0IF20 TM0IF21 TM0IF30 TM0IF31 CSIAIF1
WDT1PR2 WDT1PR1 WDT1PR0 PPR02 PPR12 PPR22 PPR32 PPR42 PPR52 PPR62 PPR01 PPR11 PPR21 PPR31 PPR41 PPR51 PPR61 PPR00 PPR10 PPR20 PPR30 PPR40 PPR50 PPR60
TM0PR002 TM0PR001 TM0PR000 TM0PR012 TM0PR011 TM0PR010 TM0PR102 TM0PR101 TM0PR100 TM0PR112 TM0PR111 TM0PR110 TM5PR02 TM5PR12 TM5PR01 TM5PR11 TM5PR00 TM5PR10
CSI0PR02 CSI0PR01 CSI0PR00 CSI0PR12 CSI0PR11 CSI0PR10 SREPR02 SRPR02 STPR02 SREPR12 SRPR12 STPR12 SREPR01 SRPR01 STPR01 SREPR11 SRPR11 STPR11 SREPR00 SRPR00 STPR00 SREPR10 SRPR10 STPR10
TMHPR02 TMHPR01 TMHPR00 TMHPR12 TMHPR11 TMHPR10 CSIAPR02 CSIAPR01 CSIAPR00 IICPR02 ADPR2 KRPR2 WTIPR2 WTPR2 BRGPR2 IICPR01 ADPR1 KRPR1 WTIPR1 WTPR1 BRGPR1 IICPR00 ADPR0 KRPR0 WTIPR0 WTPR0 BRGPR0
TM0PR202 TM0PR201 TM0PR200 TM0PR212 TM0PR211 TM0PR210 TM0PR302 TM0PR301 TM0PR300 TM0PR312 TM0PR311 TM0PR310 CSIAPR12 CSIAPR11 CSIAPR10
Note Only for the PD703212Y, 703213Y, 703214Y, and 70F3214Y
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Table 19-7. Interrupt Control Registers (xxlCn) (V850ES/KJ1) (1/2)
Address Register <7> FFFFF110H FFFFF112H FFFFF114H FFFFF116H FFFFF118H FFFFF11AH FFFFF11CH FFFFF11EH FFFFF120H FFFFF122H FFFFF124H FFFFF126H FFFFF128H FFFFF12AH FFFFF12CH FFFFF12EH FFFFF130H FFFFF132H FFFFF134H FFFFF136H FFFFF138H FFFFF13AH FFFFF13CH FFFFF13EH FFFFF140H FFFFF142H FFFFF144H FFFFF146H FFFFF148H FFFFF14AH FFFFF14CH FFFFF14EH FFFFF150H FFFFF152H FFFFF154H FFFFF156H FFFFF158H FFFFF15AH FFFFF15CH FFFFF15EH FFFFF160H WDT1IC PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 TM0IC00 TM0IC01 TM0IC10 TM0IC11 TM5IC0 TM5IC1 CSI0IC0 CSI0IC1 SREIC0 SRIC0 STIC0 SREIC1 SRIC1 STIC1 TMHIC0 TMHIC1 CSIAIC0 IICIC0Note ADIC KRIC WTIIC WTIC BRGIC TM0IC20 TM0IC21 TM0IC30 TM0IC31 CSIAIC1 TM0IC40 TM0IC41 TM0IC50 TM0IC51 CSI0IC2 WDT1IF PIF0 PIF1 PIF2 PIF3 PIF4 PIF5 PIF6 TM0IF00 TM0IF01 TM0IF10 TM0IF11 TM5IF0 TM5IF1 CSI0IF0 CSI0IF1 SREIF0 SRIF0 STIF0 SREIF1 SRIF1 STIF1 TMHIF0 TMHIF1 CSIAIF0 IICIF0 ADIF KRIF WTIIF WTIF BRGIF TM0IF20 TM0IF21 TM0IF30 TM0IF31 CSIAIF1 TM0IF40 TM0IF41 TM0IF50 TM0IF51 CSI0IF2 <6> WDT1MK PMK0 PMK1 PMK2 PMK3 PMK4 PMK5 PMK6 TM0MK00 TM0MK01 TM0MK10 TM0MK11 TM5MK0 TM5MK1 CSI0MK0 CSI0MK1 SREMK0 SRMK0 STMK0 SREMK1 SRMK1 STMK1 TMHMK0 TMHMK1 CSIAMK0 IICMK0 ADMK KRMK WTIIMK WTMK BRGMK TM0MK20 TM0MK21 TM0MK30 TM0MK31 CSIAMK1 TM0MK40 TM0MK41 TM0MK50 TM0MK51 CSI0MK2 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0
WDT1PR2 WDT1PR1 WDT1PR0 PPR02 PPR12 PPR22 PPR32 PPR42 PPR52 PPR62 PPR01 PPR11 PPR21 PPR31 PPR41 PPR51 PPR61 PPR00 PPR10 PPR20 PPR30 PPR40 PPR50 PPR60
TM0PR002 TM0PR001 TM0PR000 TM0PR012 TM0PR011 TM0PR010 TM0PR102 TM0PR101 TM0PR100 TM0PR112 TM0PR111 TM0PR110 TM5PR02 TM5PR12 TM5PR01 TM5PR11 TM5PR00 TM5PR10
CSI0PR02 CSI0PR01 CSI0PR00 CSI0PR12 CSI0PR11 CSI0PR10 SREPR02 SRPR02 STPR02 SREPR12 SRPR12 STPR12 SREPR01 SRPR01 STPR01 SREPR11 SRPR11 STPR11 SREPR00 SRPR00 STPR00 SREPR10 SRPR10 STPR10
TMHPR02 TMHPR01 TMHPR00 TMHPR12 TMHPR11 TMHPR10 CSIAPR02 CSIAPR01 CSIAPR00 IICPR02 ADPR2 KRPR2 WTIPR2 WTPR2 BRGPR2 IICPR01 ADPR1 KRPR1 WTIPR1 WTPR1 BRGPR1 IICPR00 ADPR0 KRPR0 WTIPR0 WTPR0 BRGPR0
TM0PR202 TM0PR201 TM0PR200 TM0PR212 TM0PR211 TM0PR210 TM0PR302 TM0PR301 TM0PR300 TM0PR312 TM0PR311 TM0PR310 CSIAPR12 CSIAPR11 CSIAPR10 TM0PR402 TM0PR401 TM0PR400 TM0PR412 TM0PR411 TM0PR410 TM0PR502 TM0PR501 TM0PR500 TM0PR512 TM0PR511 TM0PR510 CSI0PR22 CSI0PR21 CSI0PR20
Note Only for the PD703216Y, 703217Y, and 70F3217Y
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Table 19-7. Interrupt Control Registers (xxlCn) (V850ES/KJ1) (2/2)
Address Register <7> FFFFF162H FFFFF164H FFFFF166H FFFFF168H SREIC2 SRIC2 STIC2 IICIC1Note SREIF2 SRIF2 STIF2 IICIF1 <6> SREMK2 SRMK2 STMK2 IICMK1 5 0 0 0 0 4 0 0 0 0 Bits 3 0 0 0 0 2 SREPR22 SRPR22 STPR22 IICPR12 1 SREPR21 SRPR21 STPR21 IICPR11 0 SREPR20 SRPR20 STPR20 IICPR10
Note Only for the PD703216Y, 703217Y, and 70F3217Y
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19.3.5 Interrupt mask registers 0 to 2 (IMR0 to IMR2) These registers set the interrupt mask status for maskable interrupts. Bits xxMKn of the IMR0 to IMR2 register and bits xxMKn of the xxlCn register are respectively linked. The IMRm register can be read/written in 16-bit units (m = 0 to 2). When the higher 8 bits of the IMRm register are treated as the IMRmH register and the lower 8 bits of the IMRm register as the IMRmL register, they can be read/written in 8-bit or 1-bit units (m = 0 to 2). Caution In the device file, the xxMKn bit of the xxICn register is defined as a reserved word. Therefore, if bit manipulation is performed using the name xxMKn, the xxICn register, not the IMRm register, is rewritten (as a result, the IMRm register is also rewritten).
(i) V850ES/KF1
After reset: FFFFH
15
R/W
14
Address: FFFFF100H (IMR0, IMR0L), FFFFF101H (IMR0H)
13 12 11 10 9 8
IMR0 (IMR0H
Note
) CSI0MK1 CSI0MK0 TM5MK1 TM5MK0 TM0MK11 TM0MK10 TM0MK01 TM0MK00
7 6 5 4 3 2 1 0
(IMR0L)
PMK6
PMK5
PMK4
PMK3
PMK2
PMK1
PMK0
WDT1MK
After reset: FFFFH
15
R/W
14
Address: FFFFF102H (IMR1, IMR1L), FFFFF103H (IMR1H)
13 12 11 10 9 8
IMR1 (IMR1H
Note
)
1
7
BRGMK
6
WTMK
5
WTIMK
4
KRMK
3
ADMK
2
IICMK0 CSIAMK0
1 0
(IMR1L) TMHMK1 TMHMK0
STMK1
SRMK1
SREMK1
STMK0
SRMK0
SREMK0
xxMKn 0 1
Interrupt mask flag setting Enables interrupt servicing Disables interrupt servicing
Note When reading from or writing to bits 8 to 15 of the IMR0 and IMR1 registers in 8-bit or 1bit units, specify these bits as bits 0 to 7 of the IMR0H and IMR1H registers. Caution Bit 15 of the IMR1 register is fixed to 1. The operation is not generated if the value is changed. Remark xx: Identifying name of each peripheral unit (CSI0, TM5, TM0, P, WDT, BRG, WT, WTI, KR, AD, IIC, CSIA, TMH, ST, SR, SRE) n: Peripheral unit number (See Tables 19-5 to 19-7.)
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(ii) V850ES/KG1
After reset: FFFFH
15
R/W
14
Address: FFFFF100H (IMR0, IMR0L), FFFFF101H (IMR0H)
13 12 11 10 9 8
IMR0 (IMR0H
Note
) CSI0MK1 CSI0MK0 TM5MK1 TM5MK0 TM0MK11 TM0MK10 TM0MK01 TM0MK00
7 6 5 4 3 2 1 0
(IMR0L)
PMK6
PMK5
PMK4
PMK3
PMK2
PMK1
PMK0
WDT1MK
After reset: FFFFH
15
R/W
14
Address: FFFFF102H (IMR1, IMR1L), FFFFF103H (IMR1H)
13 12 11 10 9 8
IMR1 (IMR1H
Note
) TM0MK20 BRGMK
7 6
WTMK
5
WTIMK
4
KRMK
3
ADMK
2
IICMK0 CSIAMK0
1 0
(IMR1L) TMHMK1 TMHMK0
STMK1
SRMK1
SREMK1
STMK0
SRMK0
SREMK0
After reset: FFFFH
15
R/W
14
Address: FFFFF104H (IMR2, IMR2L), FFFFF105H (IMR2H)
13 12 11 10 9 8
IMR2 (IMR2H
Note
)
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
(IMR2L)
1
1
1
1
CSIAMK1 TM0MK31 TM0MK30 TM0MK21
xxMKn 0 1
Interrupt mask flag setting Enables interrupt servicing Disables interrupt servicing
Note When reading from or writing to bits 8 to 15 of the IMR0 to IMR2 registers in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the IMR0H to IMR2H registers. Caution Bits 15 to 4 of the IMR2 register are fixed to 1. The operation is not guaranteed if their value is changed. Remark xx: Identifying name of each peripheral unit (CSI0, TM5, TM0, P, WDT, BRG, WT, WTI, KR, AD, IIC, CSIA, TMH, ST, SR, SRE) n: Peripheral unit number (See Tables 19-5 to 19-7.)
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(iii) V850ES/KJ1
After reset: FFFFH
15
R/W
14
Address: FFFFF100H (IMR0, IMR0L), FFFFF101H (IMR0H)
13 12 11 10 9 8
IMR0 (IMR0H
Note
) CSI0MK1 CSI0MK0 TM5MK1 TM5MK0 TM0MK11 TM0MK10 TM0MK01 TM0MK00
7 6 5 4 3 2 1 0
(IMR0L)
PMK6
PMK5
PMK4
PMK3
PMK2
PMK1
PMK0
WDT1MK
After reset: FFFFH
15
R/W
14
Address: FFFFF102H (IMR1, IMR1L), FFFFF103H (IMR1H)
13 12 11 10 9 8
IMR1 (IMR1H
Note
) TM0MK20 BRGMK
7 6
WTMK
5
WTIMK
4
KRMK
3
ADMK
2
IICMK0 CSIAMK0
1 0
(IMR1L) TMHMK1 TMHMK0
STMK1
SRMK1
SREMK1
STMK0
SRMK0
SREMK0
After reset: FFFFH
15
R/W
14
Address: FFFFF104H (IMR2, IMR2L), FFFFF105H (IMR2H)
13 12 11 10 9 8
IMR2 (IMR2H
Note
)
1
7
1
6
1
5
IICMK1
4
STMK2
3
SRMK2
2
SREMK2 CSI0MK2
1 0
(IMR2L) TM0MK51 TM0MK50 TM0MK41 TM0MK40 CSIAMK1 TM0MK31 TM0MK30 TM0MK21
xxMKn 0 1
Interrupt mask flag setting Enables interrupt servicing Disables interrupt servicing
Note When reading from or writing to bits 8 to 15 of the IMR0 to IMR2 registers in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the IMR0H to IMR2H registers. Caution Bits 15 to 13 of the IMR2 register are fixed to 1. The operation is not guaranteed if their value is changed. Remark xx: Identifying name of each peripheral unit (CSI0, TM5, TM0, P, WDT, BRG, WT, WTI, KR, AD, IIC, CSIA, TMH, ST, SR, SRE) n: Peripheral unit number (See Tables 19-5 to 19-7.)
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19.3.6 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently being acknowledged. When the interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt is set (1) and remains set while the interrupt is being serviced. When the RETI instruction is executed, the bit among those that are set (1) in the ISPR register that corresponds to the interrupt request having the highest priority is automatically reset (0) by hardware. However, it is not reset (0) when execution is returned from non-maskable interrupt servicing or exception processing. This register can only be read, in 8-bit or 1-bit units. Caution If an interrupt is acknowledged while the ISPR register is being read in the interrupt enabled (EI) status, the value of the ISPR register after the bits of the register have been set to 1 by acknowledging the interrupt may be read. To accurately read the value of the ISPR register before an interrupt is acknowledged, read the register while interrupts are disabled (DI status).
After reset: 00H <> ISPR ISPR7
R
Address: FFFFF1FAH <> <> ISPR5 <> ISPR4 <> ISPR3 <> ISPR2 <> ISPR1 <> ISPR0
ISPR6
ISPRn 0 1
Priority of interrupt currently being acknowledged Interrupt request with priority n is not acknowledged Interrupt request with priority n is being acknowledged
Remark
n = 0 to 7 (priority level)
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19.3.7 Maskable interrupt status flag The interrupt disable flag (ID) is allocated to the PSW and controls the maskable interrupt's operating state, and stores control information regarding enabling/disabling reception of interrupt requests.
After reset: 00000020H
PSW
0
NP
EP
ID SAT CY OV
S
Z
ID 0 1
Maskable interrupt servicing specificationNote Maskable interrupt acknowledgement enabled Maskable interrupt acknowledgement disabled
Note Interrupt disable flag (ID) function ID is set (1) by the DI instruction and reset (0) by the EI instruction. Its value is also modified by the RETI instruction or LDSR instruction when referencing the PSW. Non-maskable interrupts and exceptions are acknowledged regardless of this flag. When a maskable interrupt is acknowledged, the ID flag is automatically set (1) by hardware. An interrupt request generated during the acknowledgement disabled period (ID = 1) can be acknowledged when the xxIFn bit of xxICn is set (1), and the ID flag is reset (0).
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19.3.8 Watchdog timer mode register 1 (WDTM1) This register is a special register that can be written to only in a special sequence. To generate a maskable interrupt (INTWDT1), set the WDTM14 bit to 0. This register can be read/written in 8-bit or 1-bit units (for details, refer to CHAPTER 12 WATCHDOG TIMER FUNCTIONS).
After reset: 00H <> WDTM1 RUN1
R/W
Address: FFFFF6C2H
0
0
WDTM14 WDTM13
0
0
0
RUN1 0 1
Watchdog timer operation mode selectionNote 1 Stop count operation Clear counter and start count operation
WDTM14 WDTM13 0 0 1 0 1 0
Watchdog timer operation mode selectionNote 2 Interval timer mode (Generate maskable interrupt INTWDTM1 when overflow occurs) Watchdog timer mode 1Note 3 (Generate non-maskable interrupt INTWDT1 when overflow occurs)
1
1
Watchdog timer mode 2 (Start WDTRES2 reset operation when overflow occurs)
Notes 1. Once the RUN1 bit has been set (1), it cannot be cleared (0) by software. Therefore, once counting starts, it cannot be stopped except through RESET input. 2. Once the WDTM14 and WDTM13 bits have been set (1), they cannot be cleared (0) by software. RESET input is the only way to clear these bits. 3. Restoring using the RETI instruction following a non-maskable interrupt servicing due to non-maskable interrupt request (INTWDT1) is not possible. Therefore, following completion of interrupt servicing, perform system reset.
19.3.9 Elimination of noise from INTP0 to INTP6 (1) Elimination of noise from INTP0 to INTP6 pins INTP0 to INTP6 pins incorporate a noise eliminator that uses analog delay to eliminate noise. Therefore, only when a signal having a constant level is input for a specified time or longer, it is detected as a valid edge. Edge detection occurs only after the specified length of time has elapsed.
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19.3.10 INTP0 to INTP6 edge detection function The valid edges of the INTP0 to INTP6 pins can be selected from the following four types. * Rising edge * Falling edge * Both edges * No edge detection (1) External interrupt rising edge specification register 0 (INTR0) This is an 8-bit register that specifies detection of the rising edge of the INTP0 to INTP3 pins. This register can be read/written in 8-bit or 1-bit units. Caution When switching to the port function from the external interrupt function (alternate function), edge detection may be performed. Therefore, set the port mode after setting INTF0n = INTR0n = 0.
After reset: 00H
R/W
Address: FFFFFC20H
INTR0
0
INTR06
INTR05
INTR04
INTR03
INTR02
0
0
Remark
For specification of the valid edge, refer to Table 19-8.
(2) External interrupt falling edge specification register 0 (INTF0) This is an 8-bit register that specifies detection of the falling edge of the INTP0 to INTP3 pins. This register can be read/written in 8-bit or 1-bit units. Caution When switching to the port function from the external interrupt function (alternate function), edge detection may be performed. Therefore, set the port mode after setting INTF0n = INTR0n = 0.
After reset: 00H
R/W
Address: FFFFFC00H
INTF0
0
INTF06
INTF05
INTF04
INTF03
INTF02
0
0
Remark
For specification of the valid edge, refer to Table 19-8.
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Table 19-8. INTP0 to INTP3 Pins Valid Edge Specification
INTF0n 0 0 1 1 INTR0n 0 1 0 1 Valid edge specification (n = 3 to 6) No edge detection Rising edge Falling edge Both edges
Remark n = 3 to 6: Control of INTP0 to INTP3 pins (3) External interrupt rising edge specification register 9H (INTR9H) This is an 8-bit register that specifies detection of the rising edge of the INTP4 to INTP6 pins. This register can be read/written in 8-bit or 1-bit units. Caution When switching to the port function from the external interrupt function (alternate function), edge detection may be performed. Therefore, set the port mode after setting INTF9n = INTR9n = 0.
After reset: 00H
R/W
Address: FFFFFC33H
INTR9H
INTR915 INTR914 INTR913
0
0
0
0
0
Remark
For specification of the valid edge, refer to Table 19-9.
(4) External interrupt falling edge specification register 9H (INTF9H) This is an 8-bit register that specifies detection of the falling edge of the INTP4 to INTP6 pins. This register can be read/written in 8-bit or 1-bit units. Caution When switching to the port function from the external interrupt function (alternate function), edge detection may be performed. Therefore, set the port mode after setting INTF9n = INTR9n = 0.
After reset: 00H
R/W
Address: FFFFFC13H
INTF9H
INTF915 INTF914 INTF913
0
0
0
0
0
Remark
For specification of the valid edge, refer to Table 19-9.
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Table 19-9. INTP4 to INTP6 Pins Valid Edge Specification
INTF9n 0 0 1 1 INTR9n 0 1 0 1 Valid edge specification (n = 13 to 15) No edge detection Rising edge Falling edge Both edges
Remark n = 13 to 15: Control of INTP4 to INTP6 pins
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19.4 Software Exceptions
A software exception is generated when the CPU executes the TRAP instruction. Software exceptions can always be acknowledged. 19.4.1 Operation If a software exception occurs, the CPU performs the following processing and transfers control to a handler routine. <1> Saves the restored PC to EIPC. <2> Saves the current PSW to EIPSW. <3> Writes an exception code to the lower 16 bits (EICC) of ECR (interrupt source). <4> Sets the EP and ID bits of the PSW. <5> Loads the handler address (00000040H or 00000050H) for the software exception routine to the PC and transfers control. Figure 19-8 shows the software exception processing flow. Figure 19-8. Software Exception Processing
TRAP instructionNote
CPU processing
EIPC EIPSW ECR.EICC PSW.EP PSW.ID PC
Restored PC PSW Exception code 1 1 Handler address
Exception processing
Note TRAP instruction format: TRAP vector (However, vector = 0 to 1FH)
The handler address is determined by the operand (vector) of the TRAP instruction. If the vector is 0 to 0FH, the handler address is 00000040H, and if the vector is 10 to 1FH, the handler address is 00000050H.
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19.4.2 Restore Execution is restored from software exception processing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC. <1> Loads the restored PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 1. <2> Transfers control to the address of the restored PC and PSW. Figure 19-9 shows the processing flow of the RETI instruction. Figure 19-9. RETI Instruction Processing
RETI instruction
1
PSW.EP 0 PSW.NP 0 1
PC PSW
EIPC EIPSW
PC PSW
FEPC FEPSW
Original processing restored
Caution When the PSW.EP bit and PSW.NP bit are changed by the LDSR instruction during software exception processing, in order to restore the PC and PSW correctly during restoring by the RETI instruction, it is necessary to set PSW.EP back to 1 using the LDSR instruction immediately before the RETI instruction. Remark The solid line shows the CPU processing flow.
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19.4.3 Exception status flag (EP) The EP flag, which is bit 6 of the PSW, is a status flag that indicates that exception processing is in progress. It is set when an exception occurs.
After reset: 00000020H
PSW
0
NP
EP
ID SAT CY OV
S
Z
EP 0 1
Exception processing status Exception processing not in progress Exception processing in progress
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19.5 Exception Trap
The exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the V850ES/KF1, V850ES/KG1, and V850ES/KJ1, an illegal op code trap (ILGOP: illegal OP code trap) is considered as an exception trap. 19.5.1 Illegal op code An illegal op code is defined as an instruction with instruction op code (bits 10 to 5) = 111111B, sub-op code (bits 26 to 23) = 0111B to 1111B, and sub-op code (bit 16) = 0B. When such an instruction is executed, an exception trap is generated.
15
11 10
54
0 31
27 26
23 22
16
0111 XXXXX111111XXXXXXXXXX 1111 XXXXXX0
X: Don't care
Caution It is recommended not to use illegal op code because instructions may newly be assigned in the future. (1) Operation Upon generation of an exception trap, the CPU performs the following processing and transfers control to a handler routine. <1> Saves the restored PC to DBPC. <2> Saves the current PSW to DBPSW. <3> Sets the NP, EP, and ID bits of the PSW. <4> Loads the handler address (00000060H) for the exception trap routine to the PC and transfers control. Figure 19-10 shows the exception trap processing flow.
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Figure 19-10. Exception Trap Processing
Exception trap (ILGOP) occurs
CPU processing
DBPC DBPSW PSW.NP PSW.EP PSW.ID PC
Restored PC PSW 1 1 1 00000060H
Exception processing
(2) Restore Execution is restored from exception trap processing by the DBRET instruction. When the DBRET instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC. <1> Loads the restored PC and PSW from DBPC and DBPSW. <2> Transfers control to the loaded address of the restored PC and PSW. Figure 19-11 shows the processing flow for restore from exception trap processing. Figure 19-11. Processing Flow for Restore from Exception Trap
DBRET instruction
PC PSW
DBPC DBPSW
Jump to restored PC address
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19.5.2 Debug trap A debug trap is an exception that occurs upon execution of the DBTRAP instruction and that can be acknowledged at all times. When a debug trap occurs, the CPU performs the following processing. (1) Operation <1> Saves the restored PC to DBPC. <2> Saves the current PSW to DBPSW. <3> Sets the NP, EP, and ID bits of the PSW. <4> Sets the handler address (00000060H) for the debug trap routine to the PC and transfers control. Figure 19-12 shows the debug trap processing flow. Figure 19-12. Debug Trap Processing
DBTRAP instruction
CPU processing
DBPC DBPSW PSW.NP PSW.EP PSW.ID PC
Restored PC PSW 1 1 1 00000060H
Exception processing
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(2) Restore Execution is restored from debug trap processing by the DBRET instruction. When the DBRET instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC. <1> Loads the restored PC and PSW from DBPC and DBPSW. <2> Transfers control to the loaded address of the restored PC and PSW. Figure 19-13 shows the processing flow for restore from debug trap processing. Figure 19-13. Processing Flow for Restore from Debug Trap
DBRET instruction
PC PSW
DBPC DBPSW
Jump to restored PC address
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19.6 Multiple Interrupt Servicing Control
Multiple interrupt servicing control is a function that stops an interrupt service routine currently in progress if a higher priority interrupt request is generated, and processes the acknowledgement operation of the higher priority interrupt. If an interrupt with a lower or equal priority is generated and a service routine is currently in progress, the later interrupt will be held pending. Multiple interrupt servicing control is performed when interrupts are enabled (ID = 0). Even in an interrupt servicing routine, multiple interrupt control must be performed while interrupts are enabled (ID = 0). If a maskable interrupt or software exception is generated in a maskable interrupt or software exception service program, EIPC and EIPSW must be saved. The following example illustrates the procedure. (1) To acknowledge maskable interrupt requests in service program Service program for maskable interrupt or exception ... ... * EIPC saved to memory or register * EIPSW saved to memory or register * EI instruction (enables interrupt acknowledgement) ... ... ... ... * DI instruction (disables interrupt acknowledgement) * Saved value restored to EIPSW * Saved value restored to EIPC * RETI instruction
Acknowledges maskable interrupt
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(2) To generate exception in service program Service program for maskable interrupt or exception ... ... * EIPC saved to memory or register * EIPSW saved to memory or register ... * TRAP instruction ... * Saved value restored to EIPSW * Saved value restored to EIPC * RETI instruction Priorities 0 to 7 (0 is the highest) can be set for each maskable interrupt request in multiple interrupt servicing control by software. To set a priority level, write values to the xxPRn0 to xxPRn2 bits of the interrupt request control register (xxICn) corresponding to each maskable interrupt request. After reset, interrupt requests are masked by the xxMKn bit, and the priority is set to level 7 by the xxPRn0 to xxPRn2 bits. Priorities of maskable interrupts are as follows. (High) Level 0 > Level 1 > Level 2 > Level 3 > Level 4 > Level 5 > Level 6 > Level 7 (Low) Interrupt servicing that has been suspended as a result of multiple interrupt servicing control is resumed after the interrupt servicing of the higher priority has been completed and the RETI instruction has been executed. A pending interrupt request is acknowledged after the current interrupt servicing has been completed and the RETI instruction has been executed. Caution In a non-maskable interrupt servicing routine (in the time until the RETI instruction is executed), maskable interrupts are not acknowledged and held pending. Acknowledges exceptions such as TRAP instruction.
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19.7 Interrupt Response Time
Except in the following cases, the CPU interrupt response time is a minimum of 4 clocks. If inputting consecutive interrupt requests, at least 4 clocks must be placed between each interrupt. * STOP mode * External bus access * Interrupt request non-sample instruction (Refer to 19.8 Periods in Which Interrupts Are Not Acknowledged by CPU.) * Interrupt control register access Figure 19-14. Pipeline Operation During Interrupt Request Acknowledgment (Outline) (1) Minimum interrupt response time
4 system clocks Internal clock
Interrupt request Instruction 1 Instruction 2 Interrupt acknowledgement operation Instruction (first instruction of interrupt servicing routine) IF ID EX MEM WB
IFX IDX INT1 INT2 INT3 INT4 IF ID EX
(2) Maximum interrupt response time
6 system clocks Internal clock
Interrupt request Instruction 1 Instruction 2 Interrupt acknowledgement operation Instruction (first instruction of interrupt servicing routine) IF ID EX MEM MEM MEM WB
IFX IDX INT1 INT2 INT3 INT3 INT3 INT4 IF ID EX
INT1 to INT4: Interrupt acknowledgement processing IFX: Invalid instruction fetch IDX: Invalid instruction decode
Interrupt response time (internal system clock) Internal interrupt Min. Max. 4 6 External interrupt 4 + analog delay 6 + analog delay The following cases are excluded. * IDLE/STOP mode * External bus access * Consecutive interrupt request non-sample instruction * Access to interrupt control register * Access to peripheral I/O register Condition
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19.8 Periods in Which Interrupts Are Not Acknowledged by CPU
Interrupts are acknowledged by the CPU while an instruction is being executed. However, no interrupt is acknowledged between an interrupt request non-sample instruction and the next instruction. The following instructions are interrupt request non-sample instructions. * EI instruction * DI instruction * LDSR reg2, 0x5 instructions (vs. PSW) * Store instruction for the following registers * Command register (PRCMD) * Interrupt-related registers: Interrupt control register (xxlCn), interrupt mask registers 0 to 2 (IMR0 to IMR2), in-service priority register (ISPR)
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CHAPTER 20 KEY INTERRUPT FUNCTION
20.1 Function
A key interrupt (INTKR) can be generated by inputting a falling edge to the eight key input pins (KR0 to KR7) by setting the key return mode register (KRM). Table 20-1. Assignment of Key Return Detection Pins
Flag KRM0 KRM1 KRM2 KRM3 KRM4 KRM5 KRM6 KRM7 Pin Description Controls KR0 signal in 1-bit units Controls KR1 signal in 1-bit units Controls KR2 signal in 1-bit units Controls KR3 signal in 1-bit units Controls KR4 signal in 1-bit units Controls KR5 signal in 1-bit units Controls KR6 signal in 1-bit units Controls KR7 signal in 1-bit units
Figure 20-1. Key Return Block Diagram
KR7 KR6 KR5 KR4 INTKR KR3 KR2 KR1 KR0
KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 Key return mode register (KRM)
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20.2 Key Interrupt Control Register
(1) Key return mode register (KRM) The KRM register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals. This register can be read/written in 8-bit or 1-bit units. RESET input clears KRM to 00H.
After reset: 00H
R/W
Address: FFFFF300H
KRM
KRM7
KRM6
KRM5
KRM4
KRM3
KRM2
KRM1
KRM0
KRMn 0 1
Key return mode control Does not detect key return signal Detects key return signal
Caution If the key return mode register (KRM) is changed, an interrupt request flag may be set. To prevent this, change the KRM register after disabling interrupts, and then enable interrupts after clearing the interrupt request flag.
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CHAPTER 21 STANDBY FUNCTION
21.1 Overview
The power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. The available standby modes are listed in Table 21-1. Table 21-1. Standby Modes
Mode HALT mode IDLE mode STOP mode Subclock operation mode Sub-IDLE mode Functional Outline Mode to stop only the operating clock of the CPU Mode to stop all the internal operations of the chip except the oscillatorNote Mode to stop all the internal operations of the chip except the subclock oscillatorNote Mode to use the subclock as the internal system clock Mode to stop all the internal operations of the chip, except the oscillator, in the subclock operation mode
Note The PLL does not stop. Stop the PLL to reduce the current consumption before setting each standby mode.
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Figure 21-1. Status Transition (1/2)
Normal operation mode (operation with main clock) End of oscillation stabilization time count End of oscillation stabilization time count Interrupt requestNote 3 End of oscillation stabilization time count Interrupt request
Note 2
Setting of HALT mode
Wait for stabilization of oscillation
Setting of IDLE mode
Wait for stabilization of oscillation
Setting of STOP mode
RESET inputNote 1
Wait for stabilization of oscillation Interrupt requestNote 4 RESET inputNote 1
RESET inputNote 1
HALT mode
IDLE mode
STOP mode
Notes 1. Reset input by RESET input or watchdog timer 2 overflow. 2. Non-maskable interrupt request or unmasked maskable interrupt request. 3. Non-maskable interrupt request (NMI pin input), unmasked external interrupt request (INTP0 to INTP6 pin input), or unmasked internal interrupt request from peripheral functions operable in IDLE mode. 4. Non-maskable interrupt request (NMI pin input), unmasked external interrupt request (INTP0 to INTP6 pin input), or unmasked internal interrupt request from peripheral functions operable in STOP mode.
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Figure 21-1. Status Transition (2/2)
Normal operation mode (operation with main clock) End of oscillation stabilization time count End of oscillation stabilization time count
Setting of subclock operation mode
Wait for stabilization of oscillation Setting of normal operation mode
Wait for stabilization of oscillation
RESET inputNote 1
RESET inputNote 1
Interrupt requestNote 2 Subclock operation mode (operation with subclock) Setting of IDLE mode Sub-IDLE mode
Notes 1. Reset input by RESET input or watchdog timer 2 overflow. 2. Non-maskable interrupt request (NMI pin input), unmasked external interrupt request (INTP0 to INTP6 pin input), or unmasked internal interrupt request from peripheral functions operable in subIDLE mode.
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21.2 HALT Mode
21.2.1 Setting and operation status The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode. In the HALT mode, the clock oscillator continues operating. Only clock supply to the CPU is stopped; clock supply to the other on-chip peripheral functions continues. As a result, program execution is stopped, and the internal RAM retains the contents before the HALT mode was set. The on-chip peripheral functions that are independent of instruction processing by the CPU continue operating. Table 21-3 shows the operation status in the HALT mode. The average power consumption of the system can be reduced by using the HALT mode in combination with the normal operation mode for intermittent operation. Caution Insert five or more NOP instructions after the HALT instruction. 21.2.2 Releasing HALT mode The HALT mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request, and RESET pin input. After the HALT mode has been released, the normal operation mode is restored. (1) Releasing HALT mode by non-maskable interrupt request or unmasked maskable interrupt request The HALT mode is released by a non-maskable interrupt request or an unmasked maskable interrupt request, regardless of the priority of the interrupt request. If the HALT mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. (a) If an interrupt request with a priority lower than that of the interrupt request currently being serviced is issued, only the HALT mode is released, and that interrupt request is not acknowledged. The interrupt request itself is retained. (b) If an interrupt request with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request), the HALT mode is released and that interrupt request is acknowledged. Table 21-2. Operation After Releasing HALT Mode by Interrupt Request
Release Source Non-maskable interrupt request Maskable interrupt request Interrupt Enabled (EI) Status Execution branches to the handler address Execution branches to the handler address or the next instruction is executed The next instruction is executed Interrupt Disabled (DI) Status
(2) Releasing HALT mode by RESET pin input The same operation as the normal reset operation is performed.
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Table 21-3. Operation Status in HALT Mode
Setting of HALT Mode Item CPU ROM correction Main clock oscillator Subclock oscillator Interrupt controller 16-bit timers (TM00 to TM05) 8-bit timers (TM50, TM51) Timer H (TMH0, TMH1) Watch timer Watchdog timer 1 Watchdog timer 2 Serial interface CSI00 to CSI02 CSIA0 to CSIA1 I C0
2 Note
When CPU Is Operating with Main Clock When Subclock Is Not Used Stops operation Stops operation Oscillation enabled - Operable Operable Operable Operable Operable when main clock output is selected as count clock Operable Operable when main clock is selected as count clock Operable Operable Operable Operable Operable Operable Operable Operable Retains status before HALT mode was set. Refer to CHAPTER 5 BUS CONTROL FUNCTION. The CPU registers, statuses, data, and all other internal data such as the contents of the internal RAM are retained as they were before the HALT mode was set. Operable Operable Oscillation enabled When Subclock Is Used
, I C1
2
Note
UART0 to UART2 Key interrupt function A/D converter D/A converter Real-time output Port function External bus interface Internal data
2
Note Only products with I C
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21.3 IDLE Mode
21.3.1 Setting and operation status The IDLE mode is set by clearing the PSM bit of the power save mode register (PSMR) to 0 and setting the STP bit of the power save control register (PSC) to 1 in the normal operation mode. In the IDLE mode, the clock oscillator continues operation but clock supply to the CPU and other on-chip peripheral functions stops. As a result, program execution stops and the contents of the internal RAM before the IDLE mode was set are retained. The CPU and other on-chip peripheral functions stop operating. However, the on-chip peripheral functions that can operate with the subclock or an external clock continue operating. Table 21-5 shows the operation status in the IDLE mode. The IDLE mode can reduce the current consumption more than the HALT mode because it stops the operation of the on-chip peripheral functions. The main clock oscillator does not stop, so the normal operation mode can be restored without waiting for the oscillation stabilization time after the IDLE mode has been released, in the same manner as when the HALT mode is released. Caution Insert five or more NOP instructions after the instruction that stores data in the PSC register to set the IDLE mode. 21.3.2 Releasing IDLE mode The IDLE mode is released by a non-maskable interrupt request (NMI pin input), unmasked external interrupt request (INTP0 to INTP6 pin input), unmasked internal interrupt request from the peripheral functions operable in the IDLE mode, or RESET input. After the IDLE mode has been released, the normal operation mode is restored. (1) Releasing IDLE mode by non-maskable interrupt request or unmasked maskable interrupt request The IDLE mode is released by a non-maskable interrupt request or an unmasked maskable interrupt request, regardless of the priority of the interrupt request. If the IDLE mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is processed as follows. (a) If an interrupt request with a priority lower than that of the interrupt request currently being serviced is issued, only the IDLE mode is released, and that interrupt request is not acknowledged. The interrupt request itself is retained. (b) If an interrupt request with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request), the IDLE mode is released and that interrupt request is acknowledged. Table 21-4. Operation After Releasing IDLE Mode by Interrupt Request
Release Source Non-maskable interrupt request Maskable interrupt request Interrupt Enabled (EI) Status Execution branches to the handler address Execution branches to the handler address or the next instruction is executed The next instruction is executed Interrupt Disabled (DI) Status
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(2) Releasing IDLE mode by RESET pin input The same operation as the normal reset operation is performed. Table 21-5. Operation Status in IDLE Mode
Setting of IDLE Mode Item CPU ROM correction Main clock oscillator Subclock oscillator Interrupt controller 16-bit timers (TM00 to TM05) 8-bit timers (TM50, TM51) Timer H (TMH0) Timer H (TMH1) Watch timer Stops operation Stops operation Operable when TI5m is selected as count clock Stops operation Stops operation Operable when fXT is selected as count clock Operable When CPU Is Operating with Main Clock When Subclock Is Not Used Stops operation Stops operation Oscillation enabled - Oscillation enabled When Subclock Is Used
Operable when main clock output is selected as count clock Stops operation Stops operation CSI00 to CSI02 CSIA0, CSIA1 I2C0Note, I2C1Note UART0 UART0, UART2
Watchdog timer 1 Watchdog timer 2 Serial interface
Operable when fXT is selected as count clock
Operable when SCK0n input clock is selected as operation clock Stops operation Stops operation Operable when ASCK0 is selected as count clock Stops operation Operable Stops operation Stops operation Stops operation Retains status before IDLE mode was set. Refer to CHAPTER 5 BUS CONTROL FUNCTION. The CPU registers, statuses, data, and all other internal data such as the contents of the internal RAM are retained as they were before the IDLE mode was set.
Key interrupt function A/D converter D/A converter Real-time output Port function External bus interface Internal data
2
Note Only products with I C Remark m = 0 or 1 n = 0 to 2
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21.4 STOP Mode
21.4.1 Setting and operation status The STOP mode is set when the PSM bit of the power save mode register (PSMR) is set to 1 and the STP bit of the power save control register (PSC) is set to 1 in the normal operation mode. In the STOP mode, the subclock oscillator continues operating but the main clock oscillator stops. Clock supply to the CPU and the on-chip peripheral functions is stopped. As a result, program execution is stopped, and the contents of the internal RAM before the STOP mode was set are retained. The on-chip peripheral functions that operate with the clock oscillated by the subclock oscillator or an external clock continue operating. Table 21-7 shows the operation status in the STOP mode. Because the STOP stops operation of the main clock oscillator, it reduces the current consumption to a level lower than the IDLE mode. If the subclock oscillator and external clock are not used, the power consumption can be minimized with only leakage current flowing. Caution Insert five or more NOP instructions after the instruction that stores data in the PSC register to set the STOP mode. 21.4.2 Releasing STOP mode The STOP mode is released by a non-maskable interrupt request (NMI pin input), unmasked external interrupt request (INTP0 to INTP6 pin input), unmasked internal interrupt request from the peripheral functions operable in the STOP mode, or RESET pin input. After the STOP mode has been released, the normal operation mode is restored after the oscillation stabilization time has been secured. (1) Releasing STOP mode by non-maskable interrupt request or unmasked maskable interrupt request The STOP mode is released by a non-maskable interrupt request or an unmasked maskable interrupt request, regardless of the priority of the interrupt request. If the software STOP mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. (a) If an interrupt request with a priority lower than that of the interrupt request currently being serviced is issued, only the STOP mode is released, and that interrupt request is not acknowledged. The interrupt request itself is retained. (b) If an interrupt request with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request), the STOP mode is released and that interrupt request is acknowledged. Table 21-6. Operation After Releasing STOP Mode by Interrupt Request
Release Source Non-maskable interrupt request Maskable interrupt request Interrupt Enabled (EI) Status Execution branches to the handler address The next instruction is executed Execution branches to the handler address or the next instruction is executed Interrupt Disabled (DI) Status
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(2) Releasing STOP mode by RESET pin input The same operation as the normal reset operation is performed. Table 21-7. Operation Status in STOP Mode
Setting of STOP Item CPU ROM correction Main clock oscillator Subclock oscillator Interrupt controller 16-bit timers (TM00 to TM05) 8-bit timers (TM50, TM51) Timer H (TMH0) Timer H (TMH1) Watch timer Stops operation Stops operation Operable when TI5m is selected as count clock Stops operation Stops operation Stops operation Operable when fXT is selected as count clock Operable when fXT is selected as count clock Mode When CPU Is Operating with Main Clock When Subclock Is Not Used Stops operation Stops operation Oscillation stops - Oscillation enabled When Subclock Is Used
Watchdog timer 1 Watchdog timer 2 Serial interface CSI00 to CSI02 CSIA0, CSIA1 I2C0Note, I2C1Note UART0 UART1, UART2 Key interrupt function A/D converter D/A converter Real-time output Port function External bus interface Internal data
2
Stops operation Stops operation Operable when fXT is selected as count clock
Operable when SCK0n input clock is selected as operation clock Stops operation Stops operation Operable when ASCK0 is selected as count clock Stops operation Operable Stops operation Stops operation Stops operation Retains status before STOP mode was set. Refer to CHAPTER 5 BUS CONTROL FUNCTION. The CPU registers, statuses, data, and all other internal data such as the contents of the internal RAM are retained as they were before the STOP mode was set.
Note Only products with I C Remark m = 0 or 1 n = 0 to 2
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21.5 Securing Oscillation Stabilization Time
When the STOP mode is released, only the oscillation stabilization time set by the oscillation stabilization time selection register (OSTS) elapses. If the software STOP mode has been released by RESET pin input, however, the reset value of the OSTS register, 2 /fX (8.192 ms at fX = 4 kHz) elapses. The timer for counting the oscillation stabilization time is shared with watchdog timer 1, so the oscillation stabilization time equal to the overflow time of the watchdog timer elapses. Figure 21-2 shows the operation performed when the STOP mode is released by an interrupt request. Figure 21-2. Oscillation Stabilization Time
15
Oscillated waveform Main clock
STOP mode status
Interrupt request Main clock oscillator stops Oscillation stabilization time count
Caution For details of the OSTS register, refer to 21.1.3 (1) Oscillation stabilization time selection register (OSTS).
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21.6 Subclock Operation Mode
21.6.1 Setting and operation status The subclock operation mode is set when the CK3 bit of the processor clock control register (PCC) is set to 1 in the normal operation mode. When the subclock operation mode is set, the internal system clock is changed from the main clock to the subclock. When the MCK bit of the PCC register is set to 1, the operation of the main clock oscillator is stopped. As a result, the system operates only with the subclock. However, watchdog timer 1 stops counting when subclock operation is started (CLS bit of PCC register = 1). (Watchdog timer 1 retains the value before the subclock operation mode was set.) Table 21-8 shows the operation status in subclock operation mode. In the subclock operation mode, the current consumption can be reduced to a level lower than in the normal operation mode because the subclock is used as the internal system clock. In addition, the current consumption can be further reduced to the level of the STOP mode by stopping the operation of the main system clock oscillator. Caution When manipulating the CK3 bit of the PCC register, do not change the set values of the CK2 to CK0 bits (using a bit manipulation instruction to manipulate the bit is recommended). For details, refer to 6.3 (1) Processor clock control register (PCC). 21.6.2 Releasing subclock operation mode The subclock operation mode is released by RESET pin input when the CK3 bit of the PCC register is cleared to 0. If the main clock is stopped (MCK bit of PCC register = 1), set the MCK bit of the PCC register to 1, secure the oscillation stabilization time of the main clock by software, and clear the CK3 bit of the PCC register to 0. The normal operation mode is restored when the subclock operation mode is released. Caution When manipulating the CK3 bit of the PCC register, do not change the set values of the CK2 to CK0 bits (using a bit manipulation instruction to manipulate the bit is recommended). For details, refer to 6.3 (1) Processor clock control register (PCC).
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Table 21-8. Operation Status in Subclock Operation Mode
Setting of Subclock Operation Mode Item CPU ROM correction Subclock oscillator Interrupt controller 16-bit timers (TM00 to TM05) 8-bit timers (TM50, TM51) Timer H (TMH0) Timer H (TMH1) Watch timer Watchdog timer 1 Watchdog timer 2 Serial interface CSI00 to CSI02 CSIA0, CSIA1 I C0
2 Note
Operation Status When Main Clock Is Oscillating Operable Operable Oscillation enabled Operable Operable Operable Operable Operable Operable Operable Operable Operable Operable Operable Operable Operable Operable Operable Operable Operable Settable Operable Settable Stops operation Stops operation Stops operation Stops operation Operable when TI5m is selected as count clock Stops operation Operable when fXT is selected as count clock Operable when fXT is selected as count clock Stops operation Operable when fXT is selected as count clock Operable when SCK0n input clock is selected as operation clock Stops operation Stops operation Operable when ASCK0 is selected as count clock Stops operation When Main Clock Is Stopped
, I C1
2
Note
UART0 UART1, UART2 Key interrupt function A/D converter D/A converter Real-time output Port function External bus interface Internal data
Note Only products with I C Remark m = 0 or 1 n = 0 to 2
2
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21.7 Sub-IDLE Mode
21.7.1 Setting and operation status The sub-IDLE mode is set when the PSM bit of the power save mode register (PSMR) is cleared to 0 and the STP bit of the power save control register (PSC) is set to 1 in the subclock operation mode. In this mode, the clock oscillator continues operation but clock supply to the CPU and the other on-chip peripheral functions is stopped. As a result, program execution is stopped and the contents of the internal RAM before the sub-IDLE mode was set are retained. The CPU and the other on-chip peripheral functions are stopped. However, the on-chip peripheral functions that can operate with the subclock or an external clock continue operating. Table 21-10 shows the operation status in the sub-IDLE mode. Because the sub-IDLE mode stops operation of the CPU and other on-chip peripheral functions, it can reduce the current consumption more than the subclock operation mode. If the sub-IDLE mode is set after the main clock has been stopped, the current consumption can be reduced to a level as low as that in the STOP mode. 21.7.2 Releasing sub-IDLE mode The sub-IDLE mode is released by a non-maskable interrupt request (NMI pin input), unmasked external interrupt request (INTP0 to INTP6 pin input), unmasked internal interrupt request from the peripheral functions operable in the sub-IDLE mode, or RESET pin input. When the sub-IDLE mode is released by an interrupt request, the subclock operation mode is set. If it is released by RESET pin input, the normal operation mode is restored. (1) Releasing sub-IDLE mode by non-maskable interrupt request or unmasked maskable interrupt request The sub-IDLE mode is released by a non-maskable interrupt request or an unmasked maskable interrupt request, regardless of the priority of the interrupt request. If the sub-IDLE mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. (a) If an interrupt request with a priority lower than that of the interrupt request currently being serviced is issued, only the sub-IDLE mode is released, and that interrupt request is not acknowledged. The interrupt request itself is retained. (b) If an interrupt request with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request), the sub-IDLE mode is released and that interrupt request is acknowledged. Table 21-9. Operation After Releasing Sub-IDLE Mode by Interrupt Request
Release Source Non-maskable interrupt request Maskable interrupt request Interrupt Enabled (EI) Status Execution branches to the handler address Execution branches to the handler address or the next instruction is executed The next instruction is executed Interrupt Disabled (DI) Status
(2) Releasing sub-IDLE mode by RESET pin input The same operation as the normal reset operation is performed.
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Table 21-10. Operation Status in Sub-IDLE Mode
Setting of Sub-IDLE Mode Item CPU ROM correction Subclock oscillator Interrupt controller 16-bit timers (TM00 to TM05) 8-bit timers (TM50, TM51) Timer H (TMH0) Timer H (TMH1) Watch timer Watchdog timer 1 Watchdog timer 2 Serial interface CSI00 to CSI02 CSIA0, CSIA1 I C0
2 Note
Operation Status When Main Clock Is Oscillating Stops operation Stops operation Oscillation enabled Stops operation Stops operation Operable when TI5m is selected as count clock Stops operation Operable when fXT is selected as count clock Stops operation Operable Operable when fXT is selected as count clock Stops operation Stops operation Stops operation Operable when ASCK0 is selected as count clock Stops operation Operable Stops operation Stops operation Stops operation Retains status before sub-IDLE mode was set. Refer to CHAPTER 5 BUS CONTROL FUNCTION. The CPU registers, statuses, data, and all other internal data such as the contents of the internal RAM are retained as they were before the sub-IDLE mode was set. Operable when SCK0n input clock is selected as operation clock Operable when fXT is selected as count clock Stops operation When Main Clock Is Stopped
, I C1
2
Note
UART0 UART1, UART2 Key interrupt function A/D converter D/A converter Real-time output Port function External bus interface Internal data
2
Note Only products with I C Remark m = 0 or 1 n = 0 to 2
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21.8 Control Registers
(1) Power save control register (PSC) This is an 8-bit register that controls the standby function. The STP bit of this register is used to specify the STOP mode. The PSC register is a special register (refer to 3.4.7 Special registers). Data can be written to this register only in a specific sequence so that its contents are not rewritten by mistake due to a program hang-up. This register can be read or written in 8-bit or 1-bit units.
After reset: 00H <> PSC NMI2M
R/W
Address: FFFFF1FEH <> <> INTM 0 0 <> STP 0
0
NMI0M
NMI2M 0 1
Controls non-maskable interrupt request (INTWDT2) from watchdog timer 2Note 1 INTWDT2 request enabled INTWDT2 request disabled Controls non-maskable interrupt request from NMI pinNote 1 NMI request enabled NMI request disabled
NMI0M 0 1
INTM 0 1
Controls all non-maskable interrupt requests (INTxxNote 2)Note 1 INTxxx request enabled INTxxx request disabled
STP 0 1 Normal mode Standby modeNote 3
Sets standby mode
Notes 1. Setting these bits is valid only in the STOP mode. 2. For details, refer to Tables 19-1 to 19-3 Interrupt Sources. 3. Set the STOP or IDLE mode using the PSM bit of the PSMR register. Caution If the NMI2M, NMI0M, and INTM bits, and the STP bit are set to 1 at the same time, the setting of NMI2M, NMI0M, and INTM bits becomes invalid. If there is an unmasked interrupt request being held pending when the STOP mode is set, set the bit corresponding to the interrupt (NMI2M, NMI0M, or INTM) to 1, and then set the STP bit to 1.
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CHAPTER 22 RESET FUNCTION
22.1 Overview
The following reset functions are available. * Reset function by RESET pin input * Reset function by overflow of watchdog timer 1 (WDTRES1) * Reset function by overflow of watchdog timer 2 (WDTRES2) If the RESET pin goes high, the reset status is released, and the CPU starts executing the program. Initialize the contents of each register in the program as necessary. The RESET pin has a noise eliminator that operates by analog delay to prevent malfunction caused by noise.
22.2 Configuration
Figure 22-1. Reset Block Diagram
RESET
Analog delay circuit Reset signal to CPU WDTRES1 issued due to overflow Reset controller Reset signal to CG Reset signal to other peripheral macros
Count clock
Watchdog timer 1
Count clock
Watchdog timer 2 WDTRES2 issued due to overflow
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22.3 Operation
The system is reset, initializing each hardware unit, when a low level is input to the RESET pin or if watchdog timer 1 or watchdog timer 2 overflows (WDTRES1 or WDTRES2). While a low level is being input to the RESET pin, the main clock oscillator stops. Therefore, the overall power consumption of the system can be reduced. If the RESET pin goes high or if WDTRES1 or WDTRES2 is received, the reset status is released. If the reset status is released by RESET pin input or WDTRES2, the oscillation stabilization time elapses (reset value of OSTS register: 2 /fxx) and then the CPU starts program execution. If the reset status is released by WDTRES1, the oscillation stabilization time is not inserted because the main system clock oscillator does not stop.
15
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Table 22-1. Hardware Status on RESET Pin Input or Occurrence of WDTRES2
Item Main clock oscillator (fX) Subclock oscillator (fXT) Peripheral clock (fXX to fXX/1024), internal system clock (fCLK), CPU clock (fCPU) Watchdog timer 1 clock (fXW) Internal RAM During Reset Oscillation stops (fX = 0 level). After Reset Oscillation starts
Oscillation can continue without effect from resetNote. Operation stops Operation starts. However, operation stops during oscillation stabilization time count. Operation starts
Operation stops
Undefined if power-on reset occurs or writing data to RAM and reset conflict (data loss); otherwise, retains values immediately before reset input. High impedance Initialized to specified status Operation stops Operation can be started
I/O lines (ports) On-chip peripheral I/O registers Other on-chip peripheral functions
Note The on-chip feedback resistor is "connected" by default (refer to 6.3 (1) Processor clock control register (PCC)). Table 22-2. Hardware Status on Occurrence of WDTRES1
Item Main clock oscillator (fX) Subclock oscillator (fXT) Peripheral clock (fXX to fXX/1024), internal system clock (fCLK), CPU clock (fCPU) Watchdog timer 1 clock (fXW) Internal RAM I/O lines (ports) On-chip peripheral I/O registers Other on-chip peripheral functions During Reset Oscillation continues
Note
After Reset
Oscillation can continue without effect from resetNote. Operation stops Operation continues Undefined if writing data to RAM and reset conflict (data loss); otherwise, retains values immediately before reset input. High impedance Initialized to specified status Operation stops Operation can be started Operation starts
Note The on-chip feedback resistor is "connected" by default (refer to 6.3 (1) Processor clock control register (PCC)).
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Figure 22-2. Hardware Status on RESET Input
fX
fCLK Initialized to fXX/8 operation
RESET
Analog delay (eliminated as noise) Internal system reset signal
Analog Analog delay Analog delay (eliminated as noise) delay
Oscillation stabilization time count
Overflow of timer for oscillation stabilization
Figure 22-3. Operation on Power Application
VDD
fX
fCLK Initialized to fXX/8 operation
RESET Analog delay Internal system reset signal Oscillation stabilization time count
Overflow of timer for oscillation stabilization
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CHAPTER 23 REGULATOR
23.1 Overview
The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 include a regulator to reduce the power consumption and noise. This regulator supplies a stepped-down VDD power supply voltage to the oscillator block and internal logic circuits (except the A/D converter, D/A converter, and output buffer). The regulator output voltage is set to 3.6 V (TYP.). Figure 23-1. Regulator
AVREF0
A/D converter 2.7 to 5.5 V D/A converter 2.7 to 5.5 V
BVDD I/O buffer (external access port) 2.7 to 5.5 V BVDD Bidirectional level shifter
AVREF1 VPP VDD REGC
Regulator
Flash memory
Main/sub oscillator
Internal digital circuits 3.6 V (TYP.)
EVDD
EVDD I/O buffer (normal port) 2.7 to 5.5 V
23.2 Operation
The regulator stops operating in the following modes (but only when REGC = VDD). * During RESET input * In STOP mode * In sub-IDLE mode Be sure to connect a capacitor (10 F) to the REGC pin to stabilize the regulator output. A diagram of the regulator pin connections is shown below.
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Figure 23-2. REGC Pin Connection
(a) When REGC = VDD
VDD Input voltage = 2.7 to 5.5 V REG
REGC
Voltage supply to oscillator/internal logic = 2.7 to 5.5 V
(b) When connecting REGC pin to VSS via a capacitor
VDD Input voltage = 4.0 to 5.5 V REG
REGC
Voltage supply to oscillator/internal logic = 3.6 V
10 F (recommended)
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CHAPTER 24 ROM CORRECTION FUNCTION
24.1 Overview
The ROM correction function is used to replace part of the program in the mask ROM with the program of an external RAM or the internal RAM. By using this function, instruction bugs found in the mask ROM can be corrected at up to four places. Figure 24-1. Block Diagram of ROM Correction
Instruction address bus
Correction address register n (CORADn)
Comparator
DBTRAP instruction generation block
ROM
Correction control register (CORENn bit)
Block replacing bug with DBTRAP instruction
Data bus
Remark n = 0 to 3
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24.2 Control Registers
24.2.1 Correction address registers 0 to 3 (CORAD0 to CORAD3) These registers are used to set the first address (correction address) of the instruction to be corrected in the ROM. The program can be corrected at up to four places because four correction address register n (CORADn) are provided (n = 0 to 3). The CORADn register can only be read or written in 32-bit units. If the higher 16 bits of the CORADn register are used as the CORADnH register, and the lower 16 bits as the CORADnL register, these registers can be read or written in 16-bit units. Because the ROM capacity differs depending on the product, set correction addresses in the following ranges.
PD703208, 703208Y, 7030212, 703212Y (64 KB): PD703209, 703209Y, 703213, 703213Y, 703216, 703216Y (96 KB):
0000000H to 000FFFEH 0000000H to 0017FFEH
PD703210, 703210Y, 703214, 703214Y, 703217, 703217Y (128 KB): 0000000H to 001FFFEH
Fix bits 0 and 18 to 31 to 0.
After reset: 00000000H
R/W
Address: CORAD0: FFFFF840H CORAD1: FFFFF844H
17 16
CORAD2: FFFFF848H CORAD3: FFFFF84CH
CORADn Fixed to 0 (n = 0-3) Correction address 0
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24.2.2 Correction control register (CORCN) This register disables or enables the correction operation of correction address register n (CORADn) (n = 0 to 3). Each channel can be enabled or disabled by this register. This register is set by using an 8-bit or 1-bit memory manipulation instruction.
After reset: 00H
R/W
Address: FFFFF880H
CORCN
0
0
0
0
COREN3 COREN2 COREN1 COREN0
CORENn 0 1 Disabled Enabled
Enables/disables correction operation
Remark n = 0 to 3
Table 24-1. Correspondence Between CORCN Register Bits and CORADn Registers
CORCN Register Bit COREN3 COREN2 COREN1 COREN0 Corresponding CORADn Register CORAD3 CORAD2 CORAD1 CORAD0
24.3 ROM Correction Operation and Program Flow
<1> If the address to be corrected and the fetch address of the internal ROM match, the fetch code is replaced by the DBTRAP instruction. <2> When the DBTRAP instruction is executed, execution branches to address 00000060H. <3> Software processing after branching causes the result of ROM correction to be judged (the fetch address and ROM correction operation are confirmed) and execution to branch to the correction software. <4> After the correction software has been executed, the return address is set, and return processing is started by the DBRET instruction. Cautions 1. The software that performs <3> and <4> must be executed in the internal ROM/RAM. 2. Develop the program so that the ROM correction function is not used until data has been completely written to the CORCN register that controls ROM correction. 3. When setting an address to be corrected to the CORADn register, clear the higher bits to 0 in accordance with the capacity of the internal ROM. 4. The ROM correction function cannot be used to correct the data of the internal ROM. It can only be used to correct instruction codes. If ROM correction is used to correct data, that data is replaced with the DBTRAP instruction code.
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Figure 24-2. ROM Correction Operation and Program Flow
Reset & start
Initialize microcontroller
Read data for setting ROM correction from external memory Set CORADn register
Set CORCN register
Fetch address = CORADn Yes Change fetch code to DBTRAP instruction
No
Execute fetch code
No
DBTRAP instruction executed? Yes Jump to address 60H
Jump to ROM correction judgment address
CORADn = DBPC-2? Yes CORENn = 1 Yes Jump to address of replacement program Execute correction code Write return address to DBPC. Write value of PSW to DBPSW as necessary. Execute DBRET instruction
No
No
Error processing
: Processing by user program : ROM correction judgment
Remark n = 0 to 3
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CHAPTER 25 FLASH MEMORY
The following products are the on-chip flash memory versions of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1. (1) V850ES/KF1
PD70F3210, 70F3210Y: Products with 128 KB flash memory
(2) V850ES/KG1
PD70F3214, 70F3214Y: Products with 128 KB flash memory
(3) V850ES/KJ1
PD70F3217, 70F3217Y: Products with 128 KB flash memory
When an instruction is fetched from this flash memory, 4 bytes can be accessed with 1 clock, in the same manner as the mask ROM versions. Data can be written to the flash memory with the flash memory mounted on the target system (on-board). Connect a dedicated flash programmer to the target system to write the flash memory. The following are the assumed environments and applications of flash memory. Changing software after soldering the V850ES/KF1, V850ES/KG1, or V850ES/KJ1 onto the target system Producing many variations of a product in small quantities by changing the software Adjusting data when mass production is started Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing and application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluation for the commercial samples (not engineering samples) of the mask ROM version.
25.1 Features
* 4 byte/1 clock access (during instruction fetch access) * Erasing all areas at once or in area units * Communication with dedicated flash programmer via serial interface * Erase/write voltage: VPP = 10.3 V * On-board programming
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25.2 Writing with Flash Programmer
Data can be written to the flash memory on-board or off-board, by using a dedicated flash programmer. (1) On-board programming The contents of the flash memory can be rewritten after the V850ES/KF1, V850ES/KG1, or V850ES/KJ1 has been mounted on the target system. The connectors that connect the dedicated flash programmer must be mounted on the target system. (2) Off-board programming Data can be written to the flash memory with a dedicated program adapter (FA series) before the V850ES/KF1, V850ES/KG1, or V850ES/KJ1 is mounted on the target system. Remark The FA series is a product of Naito Densei Machida Mfg. Co., Ltd. Table 25-1. Wiring Between PD70F3210 and 70F3210Y (V850ES/KF1), and PG-FP3
Pin Configuration of Flash Programmer (PG-FP3) Signal Name SI/RxD SO/TxD SCK CLK I/O Input Output Output Output Pin Function Receive signal Transmit signal Transfer clock Clock to V850ES/KF1 With CSI00-HS Pin Name P41/SO00 P40/SI00 Pin No. 20 19 With CSI00 Pin Name P41/SO00 P40/SI00 Pin No. 20 19 With UART0 Pin Name P30/TXD0 P31/RXD0 Pin No. 22 23
P42/SCK00 21 X1 X2
Note
P42/SCK00 21 X1 X2
Note
Not needed Not needed X1 X2
Note
12 13 14 8 48
12 13 14 8
12 13 14 8
/RESET VPP HS
Output Output Input
Reset signal Write voltage Handshake signal for CSI0 + HS communication
RESET VPP PCS1/CS1
RESET VPP
RESET VPP
Not needed Not needed Not needed Not needed
VDD
I/O
VDD voltage generation/voltage monitor
VDD EVDD AVREF0
9 31 1 11 2 30
VDD EVDD AVREF0 VSS AVSS EVSS
9 31 1 11 2 30
VDD EVDD AVREF0 VSS AVSS EVSS
9 31 1 11 2 30
GND
-
Ground
VSS AVSS EVSS
Note When using the clock out of the flash programmer, connect CLK of the programmer to X1, and connect its inverse signal to X2. Cautions 1. Be sure to connect the REGC pin in either of the following ways. * Connect to GND via a 10 F capacitor * Directly connect to VDD 2. When connecting the REGC pin to GND via a 10 F capacitor, the clock cannot be supplied from the CLK pin of the flash programmer. Supply the clock by creating an oscillator on the board.
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Figure 25-1. Wiring Example of V850ES/KF1 Flash Writing Adapter (FA-80GC-8BT, FA-80GK-9EU)
D VD D N G
D VD D N G
48
PD70F3210, PD70F3210Y
31 30
Connect to GND. Connect to VDD.
Note
21 1
G N D VD D
2
8
9
10
11
12
13
14
19
20
D N G D VD
SI
SO
SCK
X1
X2
/RESET
VPP RESERVE/HS
Note Be sure to connect the REGC pin in either of the following ways. * Connect to GND via a 10 F capacitor. * Directly connect to VDD. When connecting the REGC pin to GND via a 10 F capacitor, the clock cannot be supplied from the CLK pin of the flash programmer. Supply the clock by preparing an oscillator on the board. Remarks 1. Handle the pins not described above in accordance with the specified handling of unused pins (refer to 2.4 Pin I/O Circuits and Recommended Connection of Unused Pins). When connecting to VDD via a resistor, use of a resistor of 1 k to 10 k is recommended. 2. This adapter is for 80-pin plastic QFP and 80-pin plastic TQFP (fine pitch) packages. 3. This diagram shows the wiring when using a handshake-supporting CSI.
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Table 25-2. Wiring Between PD70F3214 and 70F3214Y (V850ES/KG1), and PG-FP3
Pin Configuration of Flash Programmer (PG-FP3) Signal Name SI/RXD SO/TXD SCK CLK I/O Input Output Output Output Pin Function Receive signal Transmit signal Transfer clock Clock to V850ES/KG1 With CSI00-HS Pin Name P41/SO00 P40/SI00 Pin No. 23 22 With CSI00 Pin Name P41/SO00 P40/SI00 Pin No. 23 22 With UART0 Pin Name P30/TXD0 P31/RXD0 Pin No. 25 26
P42/SCK00 24 X1 X2
Note
P42/SCK00 24 X1 X2
Note
Not needed Not needed X1 X2
Note
12 13 14 8 60
12 13 14 8
12 13 14 8
/RESET VPP HS
Output Output Input
Reset signal Write voltage Handshake signal for CSI0 + HS communication
RESET VPP PCS1/CS1
RESET VPP
RESET VPP
Not needed Not needed Not needed Not needed
VDD
I/O
VDD voltage generation/voltage monitor
VDD BVDD EVDD AVREF0 AVREF1
9 70 34 1 5 11 2 69 33
VDD BVDD EVDD AVREF0 AVREF1 VSS AVSS BVSS EVSS
9 70 34 1 5 11 2 69 33
VDD BVDD EVDD AVREF0 AVREF1 VSS AVSS BVSS EVSS
9 70 34 1 5 11 2 69 33
GND
-
Ground
VSS AVSS BVSS EVSS
Note When using the clock out of the flash programmer, connect CLK of the programmer to X1, and connect its inverse signal to X2. Cautions 1. Be sure to connect the REGC pin in either of the following ways. * Connect to GND via a 10 F capacitor * Directly connect to VDD 2. When connecting the REGC pin to GND via a 10 F capacitor, the clock cannot be supplied from the CLK pin of the flash programmer. Supply the clock by creating an oscillator on the board.
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Figure 25-2. Wiring Example of V850ES/KG1 Flash Writing Adapter (FA-100GC-8EU)
D VD D N G
D VD D N G
70
69
60
PD70F3214, PD70F3214Y
34 33
Connect to GND. Connect to VDD.
Note
1
D N G D VD
2
5
8
9
10
11
12
13
14
22
23
24
G N D VD D
SI
SO
SCK
X1
X2
/RESET
VPP RESERVE/HS
Note Be sure to connect the REGC pin in either of the following ways. * Connect to GND via a 10 F capacitor. * Directly connect to VDD. When connecting the REGC pin to GND via a 10 F capacitor, the clock cannot be supplied from the CLK pin of the flash programmer. Supply the clock by preparing an oscillator on the board. Remarks 1. Handle the pins not described above in accordance with the specified handling of unused pins (refer to 2.4 Pin I/O Circuits and Recommended Connection of Unused Pins). When connecting to VDD via a resistor, use of a resistor of 1 k to 10 k is recommended. 2. This adapter is for a 100-pin plastic LQFP (fine pitch) package. 3. This diagram shows the wiring when using a handshake-supporting CSI.
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Table 25-3. Wiring Between PD70F3217 and 70F3217Y (V850ES/KJ1), and PG-FP3
Pin Configuration of Flash Programmer (PG-FP3) Signal Name SI/RXD SO/TXD SCK CLK I/O Input Output Output Output Pin Function Receive signal Transmit signal Transfer clock Clock to V850ES/KJ1 With CIS00-HS Pin Name P41/SO00 P40/SI00 Pin No. 23 22 With CSI00 Pin Name P41/SO00 P40/SI00 Pin No. 23 22 With UART0 Pin Name P30/TXD0 P31/RXD0 Pin No. 25 26
P42/SCK00 24 X1 X2
Note
P42/SCK00 24 X1 X2
Note
Not needed Not needed X1 X2
Note
12 13 14 8 82
12 13 14 8
12 13 14 8
/RESET VPP HS
Output Output Input
Reset signal Write voltage Handshake signal for CSI0 + HS communication
RESET VPP PCS1/CS1
RESET VPP
RESET VPP
Not needed Not needed Not needed Not needed
VDD
I/O
VDD voltage generation/voltage monitor
VDD BVDD EVDD AVREF0 AVREF1
9 104 34 1 5 11 2 103 33
VDD BVDD EVDD AVREF0 AVREF1 VSS AVSS BVSS EVSS
9 70 34 1 5 11 2 69 33
VDD BVDD EVDD AVREF0 AVREF1 VSS AVSS BVSS EVSS
9 70 34 1 5 11 2 69 33
GND
-
Ground
VSS AVSS BVSS EVSS
Note When using the clock out of the flash programmer, connect CLK of the programmer to X1, and connect its inverse signal to X2. Cautions 1. Be sure to connect the REGC pin in either of the following ways. * Connect to GND via a 10 F capacitor * Directly connect to VDD 2. When connecting the REGC pin to GND via a 10 F capacitor, the clock cannot be supplied from the CLK pin of the flash programmer. Supply the clock by creating an oscillator on the board.
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Figure 25-3. Wiring Example of V850ES/KJ1 Flash Writing Adapter (FA-144GJ-UEN)
D VD D N G
D VD D N G
104103
82
PD70F3217, PD70F3217Y
Connect to GND. Connect to VDD.
Note
12
G N D VD D
5
8 9 10 11 12 13 14
22 23 24
33 34
G N D VD D
SI
SO
SCK
X1
X2
/RESET
VPP RESERVE/HS
Note Be sure to connect the REGC pin in either of the following ways. * Connect to GND via a 10 F capacitor. * Directly connect to VDD. When connecting the REGC pin to GND via a 10 F capacitor, the clock cannot be supplied from the CLK pin of the flash programmer. Supply the clock by preparing an oscillator on the board. Remarks 1. Handle the pins not described above in accordance with the specified handling of unused pins (refer to 2.4 Pin I/O Circuits and Recommended Connection of Unused Pins). When connecting to VDD via a resistor, use of a resistor of 1 k to 10 k is recommended. 2. This adapter is for a 144-pin plastic LQFP (fine pitch) package. 3. This diagram shows the wiring when using a handshake-supporting CSI.
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25.3 Programming Environment
The environment required for writing a program to the flash memory of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 is illustrated below. Figure 25-4. Environment for Writing Program to Flash Memory
VPP
XXXX YYYY
RS-232-C
Bxxxxx Cxxxxxx
XXXX
XXXXXX
Axxxx
VDD
PG-FP4 (Flash Pro4)
XXXXX
XXX YYY
STATVE
VSS RESET V850ES/KF1, V850ES/KG1, V850ES/KJ1
Dedicated flash programmer UART0/CSI00 Host machine
A host machine that controls the dedicated flash programmer is necessary. To interface between the flash programmer and the V850ES/KF1, V850ES/KG1, and V850ES/KJ1, UART0 or CSI00 is used for manipulation such as writing and erasing. To write the flash memory off-board, a dedicated program adapter (FA series) is necessary.
25.4 Communication Mode
Communication between the dedicated flash programmer and the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 is established by serial communication via UART0 or CSI00 of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1. (1) UART0 Transfer rate: 4800 to 76800 bps (LSB first) Figure 25-5. Communication with Dedicated Flash Programmer (UART0)
VPP VDD
XXXX YYYY
VPP VDD VSS RESET RXD0 TXD0 X1 X2 V850ES/KF1, V850ES/KG1, V850ES/KJ1
Bxxxxx Cxxxxxx
XXX YYY
PG-FP4 (Flash Pro4)
XXXXX
STATVE
XXXX
XXXXXX
Axxxx
GND RESET
Dedicated flash programmer
TXD RXD CLK CLK
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(2) CSI00 Transfer rate: 200 kHz to 1 MHz (MSB first) Figure 25-6. Communication with Dedicated Flash Programmer (CSI00)
VPP VDD
XXXX YYYY
VPP VDD VSS RESET SO00 SI00 SCK00 X1 X2 V850ES/KF1, V850ES/KG1, V850ES/KJ1
Bxxxxx Cxxxxxx
XXXX
XXXXXX
Axxxx
GND RESET SI
XXX YYY
PG-FP4 (Flash Pro4)
XXXXX
STATVE
Dedicated flash programmer
SO SCK CLK CLK
(3) CSI communication mode supporting handshake Transfer rate: 200 kHz to 1 MHz (MSB first) Figure 25-7. Communication with Flash Programmer (CSI00+HS)
VPP VDD
XXXX YYYY
VPP VDD VSS RESET SO00 SI00 SCK00 X1 X2 PCS1 V850ES/KF1, V850ES/KG1, V850ES/KJ1
Bxxxxx Cxxxxxx
XXXX
XXXXXX
Axxxx
GND
PG-FP4 (Flash Pro4)
XXXXX
XXX YYY
STATVE
RESET SI
Dedicated flash programmer
SO SCK CLK CLK
HS (VPP2)
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If the PG-FP3 is used as the flash programmer, the PG-PF3 generates the following signal for the V850ES/KF1, V850ES/KG1, and V850ES/KJ1. For details, refer to the PG-FP3 User's Manual (U13502E). Table 25-4. Signals Generated by Dedicated Flash Programmer (PG-FP3)
PG-FP3 V850ES/KF1, V850ES/KG1, V850ES/KJ1 Pin Function Write voltage VDD voltage generation/voltage monitor Ground Clock output to V850ES/KF1, V850ES/KG1, or V850ES/KJ1 Reset signal Receive signal Transmit signal Transfer clock Handshake signal of CSI00+HS communication Pin NameNote 1 VPP VDD VSS X1, X2Note 2 RESET SO00/TXD0 SI00/RXD0 SCK00 PCS1 x x Connection
Signal Name VPP VDD GND CLK RESET SI/RxD SO/TxD SCK HS (VPP2)
I/O Output I/O - Output Output Input Output Output Input
CSI00 UART0
Notes 1. When the flash memory programming mode is set, the pins not used for flash memory programming are in the same status as immediately after reset, i.e., port mode (input) and high impedance. If the external device connected to each port does not recognize the state immediately after reset, connect the pin to VDD or VSS via a resistor. 2. For off-board writing only: connect the clock output of the flash programmer to X1 and its inverse signal to X2. Remark : Be sure to connect the pin. : The pin does not have to be connected if the signal is generated on the target board. x: The pin does not have to be connected. : In handshake mode
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25.5 Pin Processing
To write the flash memory on-board, connectors that connect the flash programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board. When the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after reset. Therefore, because all the ports go into an output high-impedance state, if the external device does not recognize the output high-impedance state, the pins must be processed as described below. 25.5.1 VPP pin In the normal operation mode, 0 V is input to the VPP pin. In the flash memory programming mode, a write voltage of 10.3 V is supplied to the VPP pin. An example of connection of the VPP pin is illustrated below. Figure 25-8. Example of Connection of VPP Pin
V850ES/KF1, V850ES/KG1, V850ES/KJ1 Flash programmer connection pin VPP
Pull-down resistor (RVPP)
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25.5.2 Serial interface pins The pins used by each serial interface are listed below. Table 25-5. Pins Used by Each Serial Interface
Serial Interface CSI00 CSI00 + HS UART0 Pins Used SO00, SI00, SCK00 SO00, SI00, SCK00, PCS1 TXD0, RXD0
To connect the dedicated flash programmer to the pins of a serial interface that is connected to another device on the board, care must be exercised so that signals do not collide or that the other device does not malfunction. (1) Signal collision If the flash programmer (output) is connected to a pin (input) of a serial interface connected to another device (output), signal collision takes place. To avoid this collision, either isolate the connection with the other device, or make the other device go into an output high-impedance state. Figure 25-9. Signal Collision (Input Pin of Serial Interface)
V850ES/KF1, V850ES/KG1, V850ES/KJ1 Flash programmer connection pin Other device Output pin
Signal collision Input pin
In the flash memory programming mode, the signal output by the device collides with the signal sent from the flash programmer. Therefore, isolate the signal of the other device.
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(2) Malfunction of other device If the dedicated flash programmer (output or input) is connected to a pin (input or output) of a serial interface connected to another device (input), a signal may be output to the other device, causing the device to malfunction. To avoid this malfunction, either isolate the connection with the other device, or ignore the input signal to the other device. Figure 25-10. Malfunction of Other Device
V850ES/KF1, V850ES/KG1, V850ES/KJ1 Flash programmer connection pin Other device Input pin
Pin
If the signal output by the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 in the flash memory programming mode affects the other device, isolate the signal of the other device. V850ES/KF1, V850ES/KG1, V850ES/KJ1 Flash programmer connection pin Other device Input pin
Pin
If the signal output by the flash programmer in the flash memory programming mode affects the other device, isolate the signal of the other device.
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25.5.3 RESET pin If the reset signal of the flash programmer is connected to the RESET pin that is connected to the reset signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the reset signal generator. If the reset signal is input from the user system while the flash memory programming mode is set, the flash memory will not be correctly programmed. programmer. Figure 25-11. Signal Collision (RESET Pin) Do not input any signal other than the reset signal of the flash
V850ES/KF1, V850ES/KG1, V850ES/KJ1 Signal collision RESET Flash programmer connection signal Reset signal generator Output pin
In the flash memory programming mode, the signal output by the reset signal generator collides with the signal output by the flash programmer. Therefore, isolate the signal of the reset signal generator.
25.5.4 Port pins When the flash memory programming mode is set, all the port pins, except those used for communication with the flash programmer, go into an output high-impedance state. If this causes a problem in the external device connected to a port due to prohibition of the output high-impedance state (etc.), connect the port to VDD or VSS via a resistor. 25.5.5 Other signal pins Connect the X1, X2, XT1, XT2, and REGC pins in the same status as in the normal operation mode. To input the operating clock from the programmer, however, connect the clock out of the programmer to X1, and its inverse signal to X2. 25.5.6 Power supply Supply power as follows. VDD = EVDD Supply the same power as in the normal operation mode to the other power supply pins (AVREF0, AVREF1, AVSS, BVDD, and BVSS). Caution VDD of the flash programmer has a power monitor function. Be sure to connect VDD and VSS to VDD and GND of the flash programmer.
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25.6 Programming Method
25.6.1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory. Figure 25-12. Flash Memory Manipulation Procedure
Start
RESET pulse supply
Flash memory programming mode is set
Selecting communication mode
Manipulate flash memory
End? Yes End
No
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25.6.2 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash programmer, set the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 in the flash memory programming mode. To set the mode, set the VPP pin and clear the reset signal. Change the mode by using a jumper when writing the flash memory on-board. Figure 25-13. Flash Memory Programming Mode
Flash memory programming mode 10.3 V VPP VDD 0V RESET 1 2 *** n
VPP 0V 10.3 V Normal operation mode
Operation mode
Flash memory programming mode
25.6.3 Selecting communication mode In the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 a communication mode is selected by inputting pulses (up to 16 pulses) to the VPP pin after the flash memory programming mode is entered. These VPP pulses are generated by the flash programmer. The following table shows the relationship between the number of pulses and communication modes. Table 25-6. Communication Modes
VPP Pulse 0 3 8 Other Communication Mode CSI00 CSI00 + HS UART0 RFU Remark V850ES/KF1, V850ES/KG1, and V850ES/KJ1 operate as slave with MSB first. V850ES/KF1, V850ES/KG1, and V850ES/KJ1 operate as slave with MSB first. Communication rate: 9600 bps (after reset), LSB first Setting prohibited
Caution When UART0 is selected, the receive clock is calculated based on the reset command sent from the dedicated flash programmer after the VPP pulse has been received.
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25.6.4 Communication commands The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 communicate with the flash programmer by using commands. The commands sent from the flash programmer to the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 are called commands, and the commands sent from the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 to the flash programmer are called response commands. Figure 25-14. Communication Commands
Command
XXXX YYYY
Bxxxxx Cxxxxxx
XXX YYY
PG-FP4 (Flash Pro4)
XXXXX
STATVE
XXXX
XXXXXX
Axxxx
Response command V850ES/KF1, V850ES/KG1, V850ES/KJ1
Flash programmer
The flash memory control commands of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 are listed in the table below. All these commands are issued from the programmer and the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 perform processing corresponding to the respective commands. Table 25-7. Flash Memory Control Commands
Classification Verify Erase Blank check Data write Command Name Batch verify command Batch erase command Batch blank check command High-speed write command Function Compares the contents of the entire memory with the input data. Erases the contents of the entire memory. Checks the erasure status of the entire memory. Writes data by specifying the write address and number of bytes to be written, and executes a verify check. Writes data from the address following that of the high-speed write command executed immediately before, and executes a verify check. Obtains the operation status Sets the oscillation frequency Sets the erase time for batch erase Sets the write time for writing data Sets the baud rate when UART is used Reads the silicon signature information Escapes from each status
Successive write command
System setting, control
Status read command Oscillation frequency setting command Erase time setting command Write time setting command Baud rate setting command Silicon signature command Reset command
The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 return a response command for the command issued by the dedicated flash programmer. The response commands sent from the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 are listed below.
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Table 25-8. Response Commands
Command Name ACK (acknowledge) NAK (not acknowledge) Function Acknowledges command/data. Acknowledges illegal command/data.
25.6.5 Resources used The resources used in the flash memory programming mode are the areas other than addresses 03FFE800H to 03FFEFFFH (2 KB) of the internal RAM, and all the registers. The other areas of the internal RAM retain their data unless the power is turned off. The registers that are initialized by reset are initialized to the default value.
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Absolute Maximum Ratings (TA = 25C) (1/2)
Parameter Supply voltage Symbol VDD VPP BVDD EVDD AVREF0 AVREF1 Conditions VDD = EVDD = AVREF0 Flash memory version, Note 1 BVDD VDD VDD = EVDD = AVREF0 VDD= EVDD = AVREF0 AVREF1 VDD (D/A output mode) AVREF1 = AVREF0 = VDD (port mode) VSS AVSS BVSS EVSS Input voltage VI1 VI2 VI3 VI4 VI5 VI6 Analog input voltage VIAN VSS = EVSS = BVSS = AVSS VSS = EVSS = BVSS = AVSS VSS = EVSS = BVSS = AVSS VSS = EVSS = BVSS = AVSS P00 to P06, P30 to P35, P38, P39, P40 to P42, P50 to P55, P60 to P613, P80, P81, P90 to P915 PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDL0 to PDL15, PDH0 to PDH7 P10, P11 P36, P37, P614, P615 X1, X2, XT1, XT2 VPP P70 to P715 -0.3 to +0.3 -0.3 to +0.3 -0.3 to +0.3 -0.3 to +0.3 -0.3 to EVDD + 0.3
Note 2
Ratings -0.3 to +6.5 -0.3 to +10.5 -0.3 to VDD + 0.3 -0.3 to +6.5 -0.3 to +6.5 -0.3 to VDD + 0.3
Note 2 Note 2
Unit V V V V V V
V V V V V V V V V V
Note 2
-0.3 to BVDD + 0.3Note 2 -0.3 to AVREF1 + 0.3Note 2 -0.3 to +13
Note 3
-0.3 to VDD + 1.0Note 2 -0.3 to +10.5 -0.3 to AVREF0 + 0.3
V
Notes 1. Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash memory is written. * When supply voltage rises VPP must exceed VDD 15 s or more after VDD has reached the lower-limit value (2.7 V) of the operating voltage range (see a in the figure below). * When supply voltage drops VDD must be lowered 10 s or more after VPP falls below the lower-limit value (2.7 V) of the operating voltage range of VDD (see b in the figure below).
2.7 V 0V a b
VDD
VPP 2.7 V 0V
2. Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage. 3. When pull-up is not specified by a mask option. The same as VI1 when pull-up is specified.
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Absolute Maximum Ratings (TA = 25C) (2/2)
Parameter Output current, low Symbol IOL
Note
Conditions Per pin P00 to P06, P10, P11, P30 to P35, P40 to P42, P50 to P55, P60 to P613, P80, P81, P90 to P915, PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDL0 to PDL15, PDH0 to PDH7 P36 to P39, P614, P615 P00 to P06, P30 to P39, P40 to P42 P50 to P55, P60 to P615, P80, P81, P90 to P915 PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7 PDL0 to PDL15, PDH0 to PDH7 Total of all pins: 70 mA Total of all pins: 70 mA
Ratings 20
Unit mA
30 35 35 35 35 -10 Total of all pins: -60 mA Total of all pins: -60 mA Total of all pins: -70 mA Per pin -30 -30 -30
mA mA
mA mA mA
Output current, high
IOH
Note
Per pin P00 to P06, P30 to P35, P40 to P42 P50 to P55, P60 to P613, P80, P81, P90 to P915 PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7 PDL0 to PDL15, PDH0 to PDH7
mA
mA
-30
mA
P10, P11 Operating ambient temperature Storage temperature TA
-10 -40 to +85 C
Tstg
Mask ROM version Flash memory version
-65 to +150 -40 to +125
C C
Note In the V850ES/KF1, the specifications of the total of all pins for IOL and IOH are as follows since BVDD system pins do not exist.
IOL Total of pins: 70 mA P00 to P06, P30 to P35, P38, P39, P40 to P42 P50 to P55, P90, P91, P96 to P99, P913 to P915, PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, PDL0 to PDL15 IOH Total of pins: -60 mA P00 to P06, P30 to P35, P40 to P42 P50 to P55, P90, P91, P96 to P99, P913 to P915, PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6, PDL0 to PDL15 35
mA
35 mA
-30 -30
mA
mA
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Cautions 1. Do not directly connect the output (or I/O) pins of IC products to each other, or to VDD, VCC, and GND. Open-drain pins or open-collector pins, however, can be directly connected to each other. Direct connection of the output pins between an IC product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. 3. The following pins are not provided in the V850ES/KF1. P10, P11, P36, P37, P60 to P615, P78 to P715, P80, P81, P92 to P95, P910 to P912, PCD0 to PCD3, PCM4, PCM5, PCS2 to PCS7, PCT2, PCT3, PCT5, PCT7, PDH0 to PDH7, AVREF1, BVDD, BVSS In the V850ES/KF1, the specification of VI2 is the same as that of the VI1 since the BVDD pin does not exist. The following pins are not provided in the V850ES/KG1. P60 to P615, P78 to P715, P80, P81, PCD0 to PCD3, PCM4, PCM5, PCS2 to PCS7, PCT2, PCT3, PCT5, PCT7, PDH6, PDH7 Capacitance (TA = 25C, VDD = EVDD = AVREF0 = BVDD = AVREF1 = VSS = EVSS = BVSS = AVSS = 0 V)
Parameter Input capacitance I/O capacitance Symbol CI CIO Conditions fX = 1 MHz Unmeasured pins returned to 0 V P70 to P715 Note P36 to P39, P614, P615 MIN. TYP. MAX. 15 15 20 Unit pF pF pF
Note P00 to P06, P10, P11, P30 to P35, P40 to P42, P50 to P55, P60 to P613, P80, P81, P90 to P915, PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDL0 to PDL15, PDH0 to PDH7 Caution The following pins are not provided in the V850ES/KF1. P10, P11, P36, P37, P60 to P615, P78 to P715, P80, P81, P92 to P95, P910 to P912, PCD0 to PCD3, PCM4, PCM5, PCS2 to PCS7, PCT2, PCT3, PCT5, PCT7, PDH0 to PDH7, AVREF1, BVDD, BVSS The following pins are not provided in the V850ES/KG1. P60 to P615, P78 to P715, P80, P81, PCD0 to PCD3, PCM4, PCM5, PCS2 to PCS7, PCT2, PCT3, PCT5, PCT7, PDH6, PDH7
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Operating Conditions (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF)
Parameter Internal system clock frequency Symbol fCLK Conditions REGC = VDD = 5 V 10% In PLL mode (OSC = 2 to 5 MHz) REGC = Capacity, VDD = 4.0 to 5.5 V In PLL mode (OSC = 2 to 4 MHz) REGC = VDD = 2.7 to 5.5 V REGC = VDD = 2.7 to 5.5 V, operating with subclock 2 32.768 10 MHz kHz 8 16 MHz MIN. 8 TYP. MAX. 20 Unit MHz
Internal System Clock Frequency vs. Supply Voltage
100
Internal system clock frequency fCLK [MHz]
When REGC = Capacity
20.0 16.0 10.0
1.0
0.1 2.0 3.0 4.0 Supply voltage VDD [V] 5.0 6.0
PLL Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V, VSS = 0 V)
Parameter Input frequency Output frequency Lock time Symbol fx fxx tPLL After VDD reaches MIN.:2.7 V Conditions MIN. 2 8 TYP. MAX. 5 20 200 Unit MHz MHz
s
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Main Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V, VSS = 0 V)
Resonator Ceramic resonator Recommended Circuit
X1 X2
Parameter Oscillation frequency (fX)Note 1 Oscillation stabilization timeNote 2
Conditions
MIN. 2
TYP.
MAX. 10
Unit MHz s s
After reset is released After STOP mode is released
215/fX Note 3
Crystal resonator
X1
X2
Oscillation frequency (fX)Note 1 Oscillation stabilization timeNote 2 After reset is released After STOP mode is released
2 215/fX
10
MHz s
Note 3
s
External clock
X1
X2
X1, X2 input frequency (fX)
REGC = VDD Duty = 50% 5%
2
10
MHz
External clock
Notes 1. Indicates only oscillator characteristics. 2. Time required to stabilize the crystal resonator after reset or STOP mode is released. 3. The value differs depending on the OSTS register settings. Cautions 1. When using the main clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main clock is stopped and the device is operating on the subclock, wait until the oscillation stabilization time has been secured by the program before switching back to the main clock.
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(i)
Murata Manufacturing Co., Ltd.: Ceramic resonator (TA = -40 to +85C)
Product Name Type Oscillation Frequency fXX (MHz) 2.000 3.000 4.000 Recommended Circuit Constant Recommended Voltage Range MIN. (V) 2.7 2.7 2.7 2.7 2.7 2.7 2.7 2.7 2.7 2.7 2.7 2.7 2.7 MAX. (V) 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5
Manufacturer
C1 (pF) 47 47 39 47
C2 (pF) 47 47 39 47 39 47 10 15 47 47 39 39 10
Rd (k) 0 0 0 0 0 0 0 0 0 0 0 0 0
Murata Mfg. Co., Ltd.
CSTCC2M00G56-R0 CSTCC3M00G56-R0 CSTCR4M00G55-R0 CSTLS4M00G56-B0 CSTCR5M00G55-R0 CSTLS5M00G56-B0 CSTCE10M0G52-R0 CSTLS10M0G53-B0 CSTCC2M00G56A-R0 CSTCC3M00G56A-R0 CSTCR4M00G55A-R0 CSTCR5M00G55A-R0 CSTCE10M0G52A-R0
SMD SMD SMD
SMD
5.000
39 47
SMD
10.000
10 15
SMD SMD SMD SMD SMD
2.000 3.000 4.000 5.000 10.000
47 47 39 39 10
Caution This oscillator constant is a reference value based on evaluation under a specific environment by the resonator manufacturer. If optimization of oscillator characteristics is necessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 so that the internal operating conditions are within the specifications of the DC and AC characteristics.
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Subclock Oscillator Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V, VSS = 0 V)
Resonator Crystal resonator Recommended Circuit
XT1 XT2
Parameter Oscillation frequency (fXT)Note 1
Conditions
MIN. 32
TYP. 32.768
MAX. 35
Unit kHz
Oscillation stabilization timeNote 2
10
s
External clock
XT1
XT2
XT1 input frequency (fXT)Note 1 Duty = 50% 5%
REGC = VDD
32
35
kHz
External clock
Notes 1. Indicates only oscillator characteristics. 2. Time required from when VDD reaches oscillation voltage range (MIN.: 2.7 V) to when the crystal resonator stabilizes. Cautions 1. When using the subclock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subclock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main clock oscillator. Particular care is therefore required with the wiring method when the subclock is used.
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DC Characteristics (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) (1/5)
Parameter Output current, high Symbol IOH1 Conditions Per pin for P00 to P06, P30 to P35, P40 to P42, P50 to P55, P60 to P613, P80, P81, P90 to P915 Total of P00 to P06, P30 to P35, P40 to P42 Total of P50 to P55, P60 to P613, P80, P81, P90 to P915 IOH2 EVDD = 4.0 to 5.5 V EVDD = 2.7 to 5.5 V EVDD = 4.0 to 5.5 V EVDD = 2.7 to 5.5 V MAX. -5.0 -30 -15 -30 -15 -5.0 -30 -15 -30 -15 10 15 8 10 5 30 30 10 30 30 Unit mA
mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
Per pin for PCD0 to PCD3, PCM0 to PCM3, PCS0 to PCS7, PCT0 to PCT7, PDH0 to PDH7, PDL0 to PDL15 Total of PCD0 to PCD3, PCM0 to PCM3, PCS0 to PCS7, PCT0 to PCT7 Total of PDL0 to PDL15, PDH0 to PDH7 EVDD = 4.0 to 5.5 V EVDD = 2.7 to 5.5 V EVDD = 4.0 to 5.5 V EVDD = 2.7 to 5.5 V
Output current, low
IOL1
Per pin for P00 to P06, P30 to P35, P40 to P42, P50 to P55, P60 to P613, P80, P81, P90 to P915 Per pin for P36 to P39 EVDD = 4.0 to 5.5 V EVDD = 2.7 to 5.5 V Per pin for P614, P615 EVDD = 4.0 to 5.5 V EVDD = 2.7 to 5.5 V Total of P00 to P06, P30 to P37, P40 to P42 Total of P38, P39, P50 to P55, P60 to P615, P80, P81, P90 to P915
IOL2
Per pin for PCD0 to PCD3, PCM0 to PCM3, PCS0 to PCS7, PCT0 to PCT7, PDH0 to PDH7, PDL0 to PDL15 Total of PCD0 to PCD3, PCM0 to PCM3, PCS0 to PCS7, PCT0 to PCT7 Total of PDL0 to PDL15, PDH0 to PDH7
Caution The following pins are not provided in the V850ES/KF1. P10, P11, P36, P37, P60 to P615, P78 to P715, P80, P81, P92 to P95, P910 to P912, PCD0 to PCD3, PCM4, PCM5, PCS2 to PCS7, PCT2, PCT3, PCT5, PCT7, PDH0 to PDH7, AVREF1, BVDD, BVSS The following pins are not provided in the V850ES/KG1. P60 to P615, P78 to P715, P80, P81, PCD0 to PCD3, PCM4, PCM5, PCS2 to PCS7, PCT2, PCT3, PCT5, PCT7, PDH6, PDH7
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DC Characteristics (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) (2/5)
Parameter Input voltage, high Symbol VIH1 VIH2 VIH3 VIH4 VIH5 VIH6 VIH7 Input voltage, low VIL1 VIL2 VIL3 VIL4 VIL5 VIL6 VIL7 Note 1 Note 2 Note 3 P70 to P715 P10, P11Note 4 P36, P37, P614, P615 X1, X2, XT1, XT2 Note 1 Note 2 Note 3 P70 to P715 P10, P11
Note 4
Conditions
MIN. 0.7EVDD 0.8EVDD 0.7BVDD 0.7AVREF0 0.7AVREF1 0.7EVDD EVDD - 0.5 EVSS EVSS BVSS AVSS AVSS EVSS EVSS
TYP.
MAX. EVDD EVDD BVDD AVREF0 AVREF1 12
Note 5
Unit V V V V V V V V V V V V V V
EVDD 0.3EVDD 0.2EVDD 0.3BVDD 0.3AVREF0 0.3AVREF1 0.3EVDD 0.4
P36, P37, P614, P615 X1, X2, XT1, XT2
Notes 1. P00, P01, P30, P41, P60 to P65, P67, P611, P98, P911 and their alternate-function pins. 2. RESET, P02 to P06, P31 to P35, P38, P39, P40, P42, P50 to P55, P66, P68 to P610, P612, P613, P80, P81, P90 to P97, P99, P910, P912 to P915 and their alternate-function pins. 3. PCD0 to PCD3, PCM0 to PCM3, PCS0 to PCS7, PCT0 to PCT7, PDL0 to PDL15, PDH0 to PDH7 and their alternate-function pins. 4. When used as port pins, set AVREF1 = AVREF0 = VDD. 5. When pull-up is not specified by a mask option. EVDD when pull-up is specified. Caution The following pins are not provided in the V850ES/KF1. P10, P11, P36, P37, P60 to P615, P78 to P715, P80, P81, P92 to P95, P910 to P912, PCD0 to PCD3, PCM4, PCM5, PCS2 to PCS7, PCT2, PCT3, PCT5, PCT7, PDH0 to PDH7, AVREF1, BVDD, BVSS The following pins are not provided in the V850ES/KG1. P60 to P615, P78 to P715, P80, P81, PCD0 to PCD3, PCM4, PCM5, PCS2 to PCS7, PCT2, PCT3, PCT5, PCT7, PDH6, PDH7
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DC Characteristics (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) (3/5)
Parameter Output voltage, high Symbol VOH1 Note 1 Conditions IOH = -2.0 mA, EVDD = 4.0 to 5.5 V IOH = -0.1 mA, EVDD = 2.7 to 5.5 V IOH = -2.0 mA, EVDD = 4.0 to 5.5 V IOH = -0.1 mA, EVDD = 2.7 to 5.5 V IOH = -0.2 mA IOH = -0.1 mA Output voltage, low VOL1 VOL2 VOL3 VOL4 Note 6 Note 8 P10, P11
Note 5
MIN. EVDD - 1.0 EVDD - 0.5 BVDD - 1.0 BVDD - 0.5 AREF1 - 1.0 AREF1 - 0.5 0 0 0 0 0 0 0
TYP.
MAX. EVDD
Unit V
Note 2 VOH2 Note 3 Note 4 VOH3 P10, P11Note 5
EVDD BVDD BVDD AVREF1 AVREF1 0.8 0.8 0.8 2.0 1.0 1.0 2.0
V V V V V V V V V V V V
IOL = 2.0 mA IOL = 2.0 mA IOL = 2 mA
Note 7
Note 7
P36 to P39
IOL = 15 mA, EVDD = 4.0 to 5.5 V IOL = 8 mA, EVDD = 3.0 to 5.5 V IOL = 5 mA, EVDD = 2.7 to 5.5 V
VOL5
P614, P615
IOL = 10 mA, EVDD = 4.0 to 5.5 V IOL = 5 mA, EVDD = 2.7 to 5.5 V
0
1.0
V
Notes 1. Total of P00 to P06, P30 to P35, P40 to P42 and their alternate-function pins: IOH = -30 mA, total of P50 to P55, P60 to P613, P80, P81, P90 to P915 and their alternate-function pins: IOH = -30 mA. 2. Total of P00 to P06, P30 to P35, P40 to P42 and their alternate-function pins: IOH = -15 mA, total of P50 to P55, P60 to P613, P80, P81, P90 to P915 and their alternate-function pins: IOH = -15 mA. 3. Total of PCD0 to PCD3, PCM0 to PCM3, PCS0 to PCS7, PCT0 to PCT7: IOH = -30 mA, total of PDH0 to PDH7, PDL0 to PDL15 and their alternate-function pins: IOH = -30 mA. 4. Total of PCD0 to PCD3, PCM0 to PCM3, PCS0 to PCS7, PCT0 to PCT7: IOH = -15 mA, total of PDH0 to PDH7, PDL0 to PDL15 and their alternate-function pins: IOH = -15 mA. 5. When used as port pins, set AVREF1 = AVREF0 = VDD. 6. Total of P00 to P06, P30 to P37, P40 to P42 and their alternate-function pins: IOL = 30 mA, total of P38 to P39, P50 to P55, P60 to P615, P80, P81, P90 to P915 and their alternate-function pins: IOL = 30 mA. 7. Refer to IOL1 for IOL of P36 to P39, P614, and P615. 8. Total of PCD0 to PCD3, PCM0 to PCM3, PCS0 to PCS7, PCT0 to PCT7 and their alternate-function pins:IOL = 30 mA, total of PDH0 to PDH7, PDL0 to PDL15 and their alternate-function pins: IOL = 30 mA. Caution The following pins are not provided in the V850ES/KF1. P10, P11, P36, P37, P60 to P615, P78 to P715, P80, P81, P92 to P95, P910 to P912, PCD0 to PCD3, PCM4, PCM5, PCS2 to PCS7, PCT2, PCT3, PCT5, PCT7, PDH0 to PDH7, AVREF1, BVDD, BVSS The following pins are not provided in the V850ES/KG1. P60 to P615, P78 to P715, P80, P81, PCD0 to PCD3, PCM4, PCM5, PCS2 to PCS7, PCT2, PCT3, PCT5, PCT7, PDH6, PDH7
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DC Characteristics (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) (4/5)
Parameter Input leakage current, high Input leakage current, low Output leakage current, high Output leakage current, low Supply currentNote (flash memory version) Symbol ILIH ILIL ILOH ILOL IDD1 VIN = VDD VIN = 0 V VO = VDD VO = 0 V Normal operation fXX = 20 MHz (OSC = 5 MHz) (in PLL mode) REGC = VDD = 5 V 10% fXX = 16 MHz (OSC = 4 MHz) (in PLL mode) REGC = Capacity VDD = 5 V 10% fXX = 10 MHz (OSC = 10 MHz) REGC = VDD = 3 V 10% IDD2 HALT mode fXX = 20 MHz (OSC = 5 MHz) (in PLL mode) REGC = VDD = 5 V 10% fXX = 16 MHz (OSC = 4 MHz) (in PLL mode) REGC = Capacity VDD = 5 V 10% fXX = 10 MHz (OSC = 10 MHz) REGC = VDD = 3 V 10% IDD3 IDLE mode OSC = 5 MHz (when PLL mode off) REGC = VDD = 5 V 10% OSC = 4 MHz (when PLL mode off) REGC = Capacity VDD = 5 V 10% OSC = 10 MHz (when PLL mode off) REGC = VDD = 3 V 10% IDD4 Subclock operating mode Subclock IDLE mode STOP mode VIN = 0 V 10 fXT = 32.768 kHz 43 Conditions MIN. TYP. MAX. 3.0 -3.0 3.0 -3.0 60 Unit
A A A A
mA
27
40
mA
14
29
mA
18
28
mA
11
20
mA
6 1200
11 2000
mA
A
900
1600
A
900
1600
A
190
320
A
IDD5
fXT = 32.768 kHz
15
60
A
IDD6 Pull-up resistor RL
0.1 30
30 100
A
k
Note Total current of VDD, EVDD, and BVDD (all ports stopped). AVREF0 is not included.
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DC Characteristics (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) (5/5)
Parameter Supply current (mask ROM version)
Note
Symbol IDD1 Normal operation
Conditions fXX = 20 MHz (OSC = 5 MHz) (in PLL mode) REGC = VDD = 5 V 10% fXX = 16 MHz (OSC = 4 MHz) (in PLL mode) REGC = Capacity VDD = 5 V 10% fXX = 10 MHz (OSC = 10 MHz) REGC = VDD = 3 V 10%
MIN.
TYP. 30
MAX. 45
Unit mA
18
30
mA
9 17
18 25
mA mA
IDD2
HALT mode
fXX = 20 MHz (OSC = 5 MHz) (in PLL mode) REGC = VDD = 5 V 10% fXX = 16 MHz (OSC = 4 MHz) (in PLL mode) REGC = Capacity VDD = 5 V 10% fXX = 10 MHz (OSC = 10 MHz) REGC = VDD = 3 V 10%
10
18
mA
5 900
10 1400
mA
IDD3
IDLE mode
OSC = 5 MHz (when PLL mode off) REGC = VDD = 5 V 10% OSC = 4 MHz (when PLL mode off) REGC = Capacity VDD = 5 V 10% OSC = 10 MHz (when PLL mode off) REGC = VDD = 3 V 10%
A
600
1000
A
600
1000
A
IDD4 IDD5 IDD6 Pull-up resistance RL
Subclock operating mode Subclock IDLEmode STOP mode VIN = 0 V
fXT = 32.768 kHz fXT = 32.768 kHz
70 15 0.1 10 30
160 60 30 100
A A A
k
Note Total current of VDD, EVDD, and BVDD (all ports stopped). AVREF0 is not included.
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Data Retention Characteristics STOP Mode (TA = -40 to +85C)
Parameter Data retention voltage STOP release signal input time Symbol VDDDR tDREL Conditions STOP mode MIN. 2.0 0 TYP. MAX. 5.5 Unit V
s
Caution Shifting to STOP mode and restoring from STOP mode must be performed within the rated operating range.
STOP mode setting Operating voltage lower limit VDD
STOP release signal input
VDDDR
tDREL
RESET (input)
STOP mode release interrupt (NMI, etc.) (Released by falling edge)
STOP mode release interrupt (NMI, etc.) (Released by rising edge)
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AC Characteristics
AC Test Input Measurement Points (VDD, AVDD, EVDD, BVDD)
VDD
VIH Measurement points VIL
VIH VIL
0V
AC Test Output Measurement Points
VOH Measurement points VOL
VOH VOL
Load Conditions
DUT (Device under measurement)
CL = 50 pF
Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means.
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CLKOUT Output Timing (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF)
Parameter Output cycle High-level width Symbol tCYK tWKH <1> <2> VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V Low-level width tWKL <3> VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V Rise time tKR <4> VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V Fall time tKF <5> VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V Conditions MIN. 50 ns tCYK/2 - 17 tCYK/2 - 26 tCYK/2 - 17 tCYK/2 - 26 17 26 17 26 MAX. 30.6 s ns ns ns ns ns ns ns ns Unit
Clock Timing
<1> <2> <3>
CLKOUT (output)
<4>
<5>
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Bus Timing (1) In multiplex bus mode (a) CLKOUT asynchronous: In multiplex bus mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 4.0 to 5.5 V, 4.0 V BVDD VDD, 4.0 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (1/2)
Parameter Address setup time (to ASTB) Address hold time (from ASTB) Delay time from RD to address float Data input setup time from address Data input setup time from RD Delay time from ASTB to RD, WRm Data input hold time (from RD) Address output time from RD Delay time from RD, WRm to ASTB Delay time from RD to ASTB RD, WRm low-level width ASTB high-level width Data output time from WRm Data output setup time (to WRm) Data output hold time (from WRm) WAIT setup time (to address) tSAST tHSTA tFRDA tSAID tSRID tDSTRDWR tHRDID tDRDA tDRDWRST tDRDST tWRDWRL tWSTH tDWROD tSODWR tHWROD tSAWT1 tSAWT2 WAIT hold time (from address) tHAWT1 tHAWT2 WAIT setup time (to ASTB) tSSTWT1 tSSTWT2 WAIT hold time (from ASTB) tHSTWT1 tHSTWT2 HLDRQ high-level width HLDAK low-level width Delay time from HLDAK to bus output Delay time from HLDRQ to HLDAK Delay time from HLDRQ to HLDAK tWHQH tWHAL tDHAC tDHQHA1 tDHQHA2 Symbol <11> <12> <13> <14> <15> <16> <17> <18> <19> <20> <21> <22> <23> <24> <25> <26> <27> <28> <29> <30> <31> <32> <33> <34> <35> <36> <37> <38> 0.5T n1 nT (1 + n)T T + 10 T - 15 -40 (2n + 7.5)T + 40 1.5T + 40 n1 n1 (0.5 + n)T (1.5 + n)T T - 32 (1 + n)T - 32 n1 (1 + n)T - 25 T - 15 1.5T - 45 (1.5 + n)T - 45 0.5T - 20 0 (1 + i)T - 16 0.5T - 10 (1.5 + i)T - 10 (1 + n)T - 10 T - 25 20 Conditions MIN. 0.5T - 23 0.5T - 15 16 (2 + n)T - 40 (1 + n)T - 25 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. T = 1/fCPU (fCPU: CPU operating clock frequency) 2. n: Number of wait clocks inserted in the bus cycle. The sampling timing changes when a programmable wait is inserted. 3. m = 0, 1 4. i: Number of idle states inserted after a read cycle (0 or 1). 5. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.
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(TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (2/2)
Parameter Address setup time (to ASTB) Address hold time (from ASTB) Delay time from RD to address float Data input setup time from address Data input setup time from RD Delay time from ASTB to RD, WRm Data input hold time (from RD) Address output time from RD Delay time from RD, WRm to ASTB Delay time from RD to ASTB RD, WRm low-level width ASTB high-level width Data output time from WRm Data output setup time (to WRm) Data output hold time (from WRm) WAIT setup time (to address) tSAST tHSTA tFRDA tSAID tSRID tDSTRDWR tHRDID tDRDA tDRDWRST tDRDST tWRDWRL tWSTH tDWROD tSODWR tHWROD tSAWT1 tSAWT2 WAIT hold time (from address) tHAWT1 tHAWT2 WAIT setup time (to ASTB) tSSTWT1 tSSTWT2 WAIT hold time (from ASTB) tHSTWT1 tHSTWT2 HLDRQ high-level width HLDAK low-level width Delay time from HLDAK to bus output Delay time from HLDRQ to HLDAK Delay time from HLDRQ to HLDAK tWHQH tWHAL tDHAC tDHQHA1 tDHQHA2 Symbol <11> <12> <13> <14> <15> <16> <17> <18> <19> <20> <21> <22> <23> <24> <25> <26> <27> <28> <29> <30> <31> <32> <33> <34> <35> <36> <37> <38> 0.5T n1 nT (1 + n)T T + 10 T - 15 -80 (2n + 7.5)T + 70 1.5T + 70 n1 n1 (0.5 + n)T (1.5 + n)T T - 60 (1 + n)T - 60 n1 (1 + n)T - 40 T - 30 1.5T - 80 (1.5 + n)T - 80 0.5T - 35 0 (1 + i)T - 32 0.5T - 20 (1.5 + i)T - 20 (1 + n)T - 20 T-50 35 Conditions MIN. 0.5T - 42 0.5T - 30 32 (2 + n)T - 72 (1 + n)T - 40 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Caution Set the following in accordance with the usage conditions of the CPU operation clock frequency (n = 0 to 3). * 70 ns < 1/fCPU < 84 ns Set an address setup wait (ASWn bit = 1). * 62.5 ns < 1/fCPU < 70 ns Set an address setup wait (ASWn bit = 1) and address hold wait (AHWn bit = 1). Remarks 1. T = 1/fCPU (fCPU: CPU operating clock frequency) 2. n: Number of wait clocks inserted in the bus cycle. The sampling timing changes when a programmable wait is inserted. 3. m = 0, 1 4. i: Number of idle states inserted after a read cycle (0 or 1). 5. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.
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(b) CLKOUT synchronous: In multiplex bus mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 4.0 to 5.5 V, 4.0 V BVDD VDD, 4.0 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (1/2)
Parameter Delay time from CLKOUT to address Delay time from CLKOUT to address float Delay time from CLKOUT to ASTB Delay time from CLKOUT to RD, WRm Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Data output delay time from CLKOUT WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) HLDRQ setup time (to CLKOUT) HLDRQ hold time (from CLKOUT) Delay time from CLKOUT to bus float Delay time from CLKOUT to HLDAK tDKA tFKA tDKST tDKRDWR tSIDK tHKID tDKOD tSWTK tHKWT tSHQK tHKHQ tDKF tDKHA Symbol <39> <40> <41> <42> <43> <44> <45> <46> <47> <48> <49> <50> <51> 15 0 15 0 20 20 Conditions MIN. 0 0 0 -22 15 0 19 MAX. 19 14 23 0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. m = 0, 1 2. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (2/2)
Parameter Delay time from CLKOUT to address Delay time from CLKOUT to address float Delay time from CLKOUT to ASTB Delay time from CLKOUT to RD, WRm Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Data output delay time from CLKOUT WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) HLDRQ setup time (to CLKOUT) HLDRQ hold time (from CLKOUT) Delay time from CLKOUT to bus float Delay time from CLKOUT to HLDAK tDKST tDKRDWR tSIDK tHKID tDKOD tSWTK tHKWT tSHQK tHKHQ tDKF tDKHA <41> <42> <43> <44> <45> <46> <47> <48> <49> <50> <51> 25 0 25 0 40 40 0 -22 30 0 19 55 0 ns ns ns ns ns ns ns ns ns ns ns tDKA tFKA Symbol <39> <40> Conditions MIN. 0 0 MAX. 19 18 Unit ns ns
Remarks 1. m = 0, 1 2. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.
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Read Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait): In Multiplex Bus Mode
T1
T2
TW
T3
CLKOUT (output) <39>
A16 to A23 (output) <14> <43> <40> Hi-Z <44>
AD0 to AD15 (I/O)
Address <41> <11> <12>
Data <41> <17>
ASTB (output) <22> <42> <16> <13> <42> <15> <18> <20> RD (output) <21> <46> <19>
<30> <46> <32> <31> <33>
<47>
<47>
WAIT (input) <26> <28> <27> <29>
Remark WR0 and WR1 are high level.
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Write Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait): In Multiplex Bus Mode
T1
T2
TW
T3
CLKOUT (output) <39>
A16 to A23 (output) <45> AD0 to AD15 (I/O) Address <41> <11> <12> Data <41>
ASTB (output) <22> <42> <16> WR0 (output), WR1 (output) <30> <46> <47> <32> <31> <33> <21> <46> <47> <23> <42> <24> <25> <19>
WAIT (input) <26> <28> <27> <29>
Remarks RD is high level.
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Bus Hold: In Multiplex Bus Mode
TH CLKOUT (output)
TH
TH
TI
<48> <49>
<48> <34>
HLDRQ (input)
<51> <37> <38>
<51>
HLDAK (output) <35> Hi-Z <36>
<50> A16 to A23 (output)
AD0 to AD15 (I/O)
Data
Hi-Z
ASTB (output)
Hi-Z
RD (output), WR0 (output), WR1 (output)
Hi-Z
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(2) In separate bus mode (a) Read cycle (CLKOUT asynchronous): In separate bus mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 4.0 to 5.5 V, 4.0 V BVDD VDD, 4.0 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (1/2)
Parameter Address setup time (to RD) Address hold time (from RD) RD low-level width Data setup time (to RD) Data hold time (from RD) Data setup time (to address) WAIT setup time (to RD) Symbol tSARD tHARD tWRDL tSISD tHISD tSAID tSRDWT1 tSRDWT2 WAIT hold time (from RD) tHRDWT1 tHRDWT2 WAIT setup time (to address) tSAWT1 tSAWT2 WAIT hold time (from address) tHAWT1 tHAWT2 <52> <53> <54> <55> <56> <57> <58> <59> <60> <61> <62> <63> <64> <65> T (1 + n)T 0.5T (0.5 + n)T T - 65 (1 + n)T - 65 Conditions MIN. 0.5T - 50 -13 ( 1.5 + n)T - 15 30 0 (2 + n)T - 65 0.5T - 32 ( 0.5 + n)T - 32 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Cautions 1. The separate bus mode is not supported in the V850ES/KF1. 2. Set the following in accordance with the usage conditions of the CPU operation clock frequency (n = 0 to 3). * 1/fCPU < 100 ns Set an address setup wait (ASWn bit = 1). Remarks 1. T = 1/fCPU (fCPU: CPU operating clock frequency) 2. n: Number of wait clocks inserted in the bus cycle. The sampling timing changes when a programmable wait is inserted. 3. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.
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(TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (2/2)
Parameter Address setup time (to RD) Address hold time (from RD) RD low-level width Data setup time (to RD) Data hold time (from RD) Data setup time (to address) WAIT setup time (to RD) Symbol tSARD tHARD tWRDL tSISD tHISD tSAID tSRDWT1 tSRDWT2 WAIT hold time (from RD) tHRDWT1 tHRDWT2 WAIT setup time (to address) tSAWT1 tSAWT2 WAIT hold time (from address) tHAWT1 tHAWT2 <52> <53> <54> <55> <56> <57> <58> <59> <60> <61> <62> <63> <64> <65> T (1 + n)T 0.5T (0.5 + n)T T - 130 (1 + n)T - 130 Conditions MIN. 0.5T - 100 -26 ( 1.5 + n)T - 30 60 0 (2 + n)T - 120 0.5T - 50 ( 0.5 + n)T - 50 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Cautions 1. The separate bus mode is not supported in the V850ES/KF1. 2. Set the following in accordance with the usage conditions of the CPU operation clock frequency (n = 0 to 3). * 1/fCPU < 200 ns Set an address setup wait (ASWn bit = 1). Remarks 1. T = 1/fCPU (fCPU: CPU operating clock frequency) 2. n: Number of wait clocks inserted in the bus cycle. The sampling timing changes when a programmable wait is inserted. 3. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.
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(b) Read cycle (CLKOUT synchronous): In separate bus mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 4.0 to 5.5 V, 4.0 V BVDD VDD, 4.0 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (1/2)
Parameter Delay time from CLKOUT to address, CS Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Delay time from CLKOUT to RD WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) Symbol tDKSA tSISDK tHKISD tDKSR tSWTK tHKWT <66> <67> <68> <69> <70> <71> Conditions MIN. 0 15 0 0 20 0 6 MAX. 35 Unit ns ns ns ns ns ns
Caution The separate bus mode is not supported in the V850ES/KF1. Remark The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (2/2)
Parameter Delay time from CLKOUT to address, CS Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Delay time from CLKOUT to RD WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) Symbol tDKSA tSISDK tHKISD tDKSR tSWTK tHKWT <66> <67> <68> <69> <70> <71> Conditions MIN. 0 30 0 0 40 0 10 MAX. 65 Unit ns ns ns ns ns ns
Caution The separate bus mode is not supported in the V850ES/KF1. Remark The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.
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(c) Write cycle (CLKOUT asynchronous): In separate bus mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 4.0 to 5.5 V, 4.0 V BVDD VDD, 4.0 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (1/2)
Parameter Address setup time (to WRm) Address hold time (from WRm) WRm low-level width tSAW tHAW tWWRL Symbol <72> <73> <74> Conditions MIN. T - 60 0.5T - 10 ( 0.5 + n)T - 10 -5 ( 0.5 + n)T - 20 0.5T - 20 T - 30 30 nT - 30 0 nT T - 45 (1 + n)T - 45 T (1 + n)T MAX. Unit ns ns ns
Data output time from WRm Data setup time (to WRm) Data hold time (from WRm) Data setup time (to address) WAIT setup time (to WRm)
tDOSDW tSOSDW tHOSDW tSAOD tSWRWT1 tSWRWT2
<75> <76> <77> <78> <79> <80> <81> <82> <83> <84> <85> <86>
ns ns ns ns ns ns ns ns ns ns ns ns
WAIT hold time (from WRm)
tHWRWT1 tHWRWT2
WAIT setup time (to address)
tSAWT1 tSAWT2
WAIT hold time (from address)
tHAWT1 tHAWT2
Cautions 1. The separate bus mode is not supported in the V850ES/KF1. 2. Set the following in accordance with the usage conditions of the CPU operation clock frequency (n = 0 to 3). * 1/fCPU < 60 ns Set an address setup wait (ASWn bit = 1). Remarks 1. m = 0, 1 2. T = 1/fCPU (fCPU: CPU operating clock frequency) 3. n: Number of wait clocks inserted in the bus cycle. The sampling timing changes when a programmable wait is inserted. 4. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.
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(TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (2/2)
Parameter Address setup time (to WRm) Address hold time (from WRm) WRm low-level width Data output time from WRm Data setup time (to WRm) tSAW tHAW tWWRL tDOSDW tSOSDW Symbol <72> <73> <74> <75> <76> Conditions MIN. T - 100 0.5T - 10 ( 0.5 + n)T - 10 -5 ( 0.5 + n)T - 35 0.5T - 35 T - 55 50 nT - 50 0 nT T - 100 (1 + n)T - 100 T (1 + n)T MAX. Unit ns ns ns ns ns
Data hold time (from WRm) Data setup time (to address) WAIT setup time (to WRm)
tHOSDW tSAOD tSWRWT1 tSWRWT2
<77> <78> <79> <80> <81> <82> <83> <84> <85> <86>
ns ns ns ns ns ns ns ns ns ns
WAIT hold time (from WRm)
tHWRWT1 tHWRWT2
WAIT setup time (to address)
tSAWT1 tSAWT2
WAIT hold time (from address)
tHAWT1 tHAWT2
Cautions 1. The separate bus mode is not supported in the V850ES/KF1. 2. Set the following in accordance with the usage conditions of the CPU operation clock frequency (n = 0 to 3). * 1/fCPU < 100 ns Set an address setup wait (ASWn bit = 1). Remarks 1. m = 0, 1 2. T = 1/fCPU (fCPU: CPU operating clock frequency) 3. n: Number of wait clocks inserted in the bus cycle. The sampling timing changes when a programmable wait is inserted. 4. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.
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(d) Write cycle (CLKOUT synchronous): In separate bus mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 4.0 to 5.5 V, 4.0 V BVDD VDD, 4.0 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (1/2)
Parameter Delay time from CLKOUT to address, CS Data output delay time from CLKOUT Delay time from CLKOUT to WRm WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) Symbol tDKSA tDKSD tDKSW tSWTK tHKWT <87> <88> <89> <90> <91> Conditions MIN. 0 0 0 20 0 MAX. 35 10 10 Unit ns ns ns ns ns
Caution The separate bus mode is not supported in the V850ES/KF1. Remarks 1. m = 0, 1 2. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (2/2)
Parameter Delay time from CLKOUT to address, CS Data output delay time from CLKOUT Delay time from CLKOUT to WRm WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) Symbol tDKSA <87> Conditions MIN. 0 MAX. 65 Unit ns
tDKSD tDKSW tSWTK tHKWT
<88> <89> <90> <91>
0 0 40 0
15 15
ns ns ns ns
Caution The separate bus mode is not supported in the V850ES/KF1. Remarks 1. m = 0, 1 2. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.
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Read Cycle (CLKOUT Asynchronous, 1 Wait): In Separate Bus Mode
T1
TW
T2
CLKOUT (output)
CS0 to CS3 (output) A0 to A23 (output) <53> <57> AD0 to AD15 (I/O) Hi-Z <56> <55> <54> RD (output) <61> <59> <60> <58> WAIT (input) <62> <64> <63> <65> Hi-Z
<52>
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Read Cycle (CLKOUT Synchronous, 1 Wait): In Separate Bus Mode
T1
TW
T2
CLKOUT (output) <66>
<66> CS0 to CS3 (output) A0 to A23 (output) <67> Hi-Z
<68> Hi-Z <69>
AD0 to AD15 (I/O)
<69>
RD (output) <70> <71> <70> <71>
WAIT (input)
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Write Cycle (CLKOUT Asynchronous, 1 Wait): In Separate Bus Mode
T1
TW
T2
CLKOUT (output)
CS0 to CS3 (output) A0 to A23 (output) <73> <78> AD0 to AD15 (I/O) Hi-Z <75> <72> <77> <76> <74> WR0, WR1 (output) <82> <80> <79> <81> WAIT (input) <83> <85> <84> <86> Hi-Z
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Write Cycle (CLKOUT Synchronous, 1 Wait): In Separate Bus Mode
T1
TW
T2
CLKOUT (output) <87> <87>
CS0 to CS3 (output) A0 to A23 (output) <88> Hi-Z <88> Hi-Z
AD0 to AD15 (I/O)
<89>
<89>
WR0, WR1 (output)
<90>
<91>
<90>
<91>
WAIT (input)
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Basic Operation (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF)
Parameter RESET low-level width Symbol tWRSL1 tWRSL2 <93> <94> Conditions Reset in power-on status Power-on-reset when REGC = VDD Power-on-reset when REGC = Capacity NMI high-level width NMI low-level width INTPn high-level width INTPn low-level width tWNIH tWNIL tWITH tWITL <95> <96> <97> <98> Analog noise elimination Analog noise elimination n = 0 to 6 (analog noise elimination) n = 0 to 6 (analog noise elimination) MIN. 2 2 10 1 1 1 1 MAX. Unit ns
s s s s s s
Remark T = 1/fXX Reset
VDD <94> RESET (input) <93>
Interrupt
<95>
<96>
NMI (input)
<97>
<98>
INTPn (input)
Remark n = 0 to 6
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Timer Timing (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF)
Parameter TI0n high-level width Symbol tTI0H Conditions REGC = VDD = 5 V 10% MIN. 2/fsam + 0.1
Note
MAX.
Unit ns ns
TI0n low-level width
tTI0L
REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V REGC = VDD = 5 V 10% REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V
2/fsam + 0.2
Note
ns ns
TI50 high-level width TI51 low-level width
tTI5H tTI5L
50 100
ns ns
Note fsam = Timer count clock However, fsam = fXX/4 when the TI0n valid edge is selected as the timer count clock. Remark V850ES/KF1: n = 00, 01, 10, 11 V850ES/KG1: n = 00, 01, 10, 11, 20, 21, 30, 31 V850ES/KJ1: n = 00, 01, 10, 11, 20, 21, 30, 31, 40, 41, 50, 51 UART Timing (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF)
Parameter Transmit rate ASCK0 cycle time REGC = VDD = 5 V 10% REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V 12 6 Symbol Conditions MIN. MAX. 31.25 Unit kbps MHz MHz
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CSI0 Timing
(1) Master mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF)
Parameter SCK0n cycle time tKCY1 Symbol <99> Conditions REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V SCK0n high-/low-level width SI0n setup time (to SCK0n) tKH1, tKL1 tSIK1 <100> <101> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V SI0n hold time (from SCK0n) tKSI1 <102> REGC = VDD = 5 V 10% REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V Delay time from SCK0n to SO0n output tKSO1 <103> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V MIN. 200 400 tKCY1/2 - 30 30 50 30 50 30 60 MAX. Unit ns ns ns ns ns ns ns ns ns
Remark n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) (2) Slave mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF)
Parameter SCK0n cycle time tKCY2 Symbol <99> Conditions REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V SCK0n high-/low-level width tKH2, tKL2 <100> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V SI0n setup time (to SCK0n) tSIK2 <101> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V SI0n hold time (from SCK0n) tKSI2 <102> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V Delay time from SCK0n to SO0n output tKSO2 <103> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V MIN. 200 400 45 90 30 60 30 60 50 100 MAX. Unit ns ns ns ns ns ns ns ns ns ns
Remark n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1)
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<99> <100> SCK0n (I/O) <100>
<101> <102> Hi-Z SI0n (input)
Input data
Hi-Z
<103>
SO0n (output)
Output data
Remark n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1)
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CSIA Timing
(1) Master mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF)
Parameter SCKAn cycle time Symbol tKCY3 <99> Conditions REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V SCKAn high-/low-level width SIAn setup time (to SCKAn) tKH3, tKL3 tSIK3 <100> <101> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V SIAn hold time (from SCKAn) tKSI3 <102> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V Delay time from SCKAn to SOAn output tKSO3 <103> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V MIN. 600 1000 tKCY3/2 - 30 30 60 30 60 MAX. Unit ns ns ns ns ns ns ns
30 60
ns ns
Remark n = 0 (V850ES/KF1), n = 0, 1 (V850ES/KG1, V850ES/KJ1) (2) Slave mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF)
Parameter SCKAn cycle time tKCY4 Symbol <99> Conditions REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V SCKAn high-/low-level width SIAn setup time (to SCKAn) tKH4, tKL4 tSIK4 <100> <101> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V SIAn hold time (from SCKAn) tKSI4 <102> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V Delay time from SCKAn to SOAn output tKSO4 <103> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V MIN. 840 1700 tKCY4/2 - 30 50 100 MAX. Unit ns ns ns ns ns
50 100 tCY x 2 + 30Note tCY x 2 + 60Note
ns ns ns ns
Note tCY: Internal clock output cycle fXX (CKSAn1 = 0, CKSAn0 = 0), fXX/2 (CKSAn1 = 0, CKSAn0 = 1) fXX/2 (CKSAn1 = 1, CKSAn0 = 0), fXX/2 (CKSAn1 = 1, CKSAn0 = 1) Remark n = 0 (V850ES/KF1), n = 0, 1 (V850ES/KG1, V850ES/KJ1)
2 3
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CHAPTER 26 ELECTRICAL SPECIFICATIONS
<99> <100> SCKAn (I/O) <100>
<101> <102> Hi-Z SIAn (input)
Input data
Hi-Z
<103>
SOAn (output)
Output data
Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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CHAPTER 26 ELECTRICAL SPECIFICATIONS
I C Bus Mode (Y Products (Products with On-Chip I C) Only) (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Normal Mode MIN. SCLn clock frequency Bus free time (Between start and stop conditions) Hold timeNote 1 SCLn clock low-level width SCLn clock high-level width Setup time for start/restart conditions Data hold time CBUS compatible master I2C mode Data setup time SDAn and SCLn signal rise time SDAn and SCLn signal fall time Stop condition setup time Pulse width of spike suppressed by input filter Capacitance load of each bus line tSU:DAT tR tF tSU:STO tSP Cb <110> <111> <112> <113> <114> tHD:STA tLOW tHIGH tSU:STA <105> <106> <107> <108> <109> 4.0 4.7 4.0 4.7 - - - - - - - 1000 300 - - 400 0.6 1.3 0.6 0.6 - 0Note 2 100
Note 4
2
2
High-Speed Mode MIN. 0 1.3 MAX. 400 - - - - - - 0.9Note 3 - 300 300 - 50 400
Unit
MAX. 100 -
fCLK tBUF <104>
0 4.7
kHz
s s s s s s s
ns ns ns
tHD:DAT
5.0 0Note 2 250 - - 4.0 - -
20 + 0.1CbNote 5 20 + 0.1CbNote 5 0.6 0 -
s
ns pF
Notes 1. At the start condition, the first clock pulse is generated after the hold time. 2. The system requires a minimum of 300 ns hold time internally for the SDAn signal (at VIHmin. of SCLn signal) in order to occupy the undefined area at the falling edge of SCLn. 3. If the system does not extend the SCLn signal low hold time (tLOW), only the maximum data hold time (tHD:DAT) needs to be satisfied. 4. The high-speed mode I C bus can be used in the normal-mode I C bus system. In this case, set the highspeed mode I C bus so that it meets the following conditions. * If the system does not extend the SCLn signal's low state hold time: tSU:DAT 250 ns * If the system extends the SCLn signal's low state hold time: Transmit the following data bit to the SDAn line prior to the SCLn line release (tRmax. + tSU:DAT = 1000 + 250 = 1250 ns: Normal mode I C bus specification). 5. Cb: Total capacitance of one bus line (unit: pF) Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
2 2 2 2
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CHAPTER 26 ELECTRICAL SPECIFICATIONS
I C Bus Mode (Y Products (Products with On-Chip I C) Only)
2
2
<106> <107> SCLn (I/O) <112> <111> <105> <109> <110> <108> <105> <114> <113>
SDAn (I/O) <104> Stop condition Start condition <111> <112> Restart condition Stop condition
Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)
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CHAPTER 26 ELECTRICAL SPECIFICATIONS
A/D Converter (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V)
Parameter Resolution Overall error
Note 1
Symbol
Conditions
MIN. 10
TYP. 10 0.2 0.3
MAX. 10 0.4 0.6 100 100 0.4 0.6 0.4 0.6 2.5 4.5 1.5 2.0
Unit bit %FSR %FSR
4.0 AVREF0 5.5 V 2.7 AVREF0 4.0 V
Conversion time
tCONV
4.0 AVREF0 5.5 V 2.7 AVREF0 4.0 V
14 17
s s
%FSR %FSR %FSR %FSR LSB LSB LSB LSB V mA
Zero-scale error
Note 1
4.0 AVREF0 5.5 V 2.7 AVREF0 4.0 V
Full-scale error
Note 1
4.0 AVREF0 5.5 V 2.7 AVREF0 4.0 V
Non-linearity error
Note 2
4.0 AVREF0 5.5 V 2.7 AVREF0 4.0 V
Differential linearity errorNote 2 Analog input voltage AVREF0 current VIAN IAREF0
4.0 AVREF0 5.5 V 2.7 AVREF0 4.0 V 0 When using A/D converter When not using A/D converter 1.0 1.0
AVREF0 2.0 10
A
Notes 1. Excluding quantization error (0.05%FSR). 2. Excluding quantization error (0.5LSB). Remark LSB: Least Significant Bit FSR: Full Scale Range D/A Converter (V850ES/KG1, V850ES/KJ1 only) (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V)
Parameter Resolution Overall error
Notes 1, 2
Symbol
Conditions
MIN.
TYP.
MAX. 8
Unit bit %FSR %FSR %FSR
Load condition = 2 M Load condition = 4 M Load condition = 10 M
1.2 0.8 0.6 10 15 8 1.5 1.0 3.0 10
Settling time
Notes 1, 2
C = 30 pF
VDD = 4.5 to 5.5 V VDD = 2.7 to 4.5 V
s s
k mA
Output resistance AVREF1 current
Note 4
Note 3
VO IAVREF1
Output data 55H During D/A conversion When D/A conversion stopped
A
Notes 1. Excluding quantization error (0.2%FSR). 2. R and C are the D/A converter output pin load resistance. 3. Value of 1 channel of D/A converter 4. Value of 2 channels of D/A converter
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CHAPTER 26 ELECTRICAL SPECIFICATIONS
Flash Memory Programming Characteristics (TA = +10 to +40C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) (1) Basic characteristics
Parameter Programming operation frequency VPP supply voltage VDD supply current VPP supply current Step erase time Overall erase time Writeback time Number of writebacks Number of erases/writebacks Step write time Overall write time per word VPP2 IDD IPP tER tERA tWB CWB CERWB tWR tWRW Note 5 When step write time = 50 s (1 word = 4 byte), Note 6 1 erase + 1 write after erase = 1 rewrite, Note 7 49 49 50 During flash memory programming When VPP = VPP2, fXX = 10 MHz, VDD = 5.5 V When VPP = VPP2 Note 1 When step erase time = 0.2 s, Note 2 Note 3 When writeback time = 1 ms, Note 4 4.9 5.0 0.196 0.2 Symbol Conditions MIN. 2 9.7 10.0 TYP. MAX. 10 10.3 60 100 0.204 20 5.1 100 16 51 510 Unit MHz V mA mA s s/area ms Times Times
s s/word
Count/area
Number of rewrites per area
CERWR
20
Notes 1. The recommended setting value of the step erase time is 0.2 s. 2. The prewrite time prior to erasure and the erase verify time (writeback time) are not included. 3. The recommended setting value of the writeback time is 5.0 ms. 4. Writeback is executed once by the issuance of the writeback command. Therefore, the retry count must be the maximum value minus the number of commands issued. 5. The recommended setting value of the step writing time is 50 s. 6. 100 s is added to the actual writing time per word. The internal verify time during and after the writing is not included. 7. When writing initially to shipped products, it is counted as one rewrite for both "erase to write" and "write only". Example (P: Write, E: Erase) Shipped product PEPEP: 3 rewrites Shipped product E PEPEP: 3 rewrites
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CHAPTER 26 ELECTRICAL SPECIFICATIONS
(2) Serial write operation characteristics
Parameter Setup time from VDD to VPP Setup time from VPP to RESET Count start time from RESET to VPPH Count complete time VPP counter high-/low-level width VPP pulse low-level input voltage VPP pulse high-level input voltage Symbol tDPRSR tPSRRF tRFOF tCOUNT tCH/tCL VPPL VPPH 8 0.8VDD 9.7 10.0 1.2VDD 10.3 Conditions MIN. 15 10 2 20 TYP. MAX. Unit
s s s
ms
s
V V
Flash Write Mode Setting Timing
VDD VDD 0V VPPH VPP VDD VPPL tPSRRF tCOUNT EVDD RESET (input) 0V tCL tDRPSR tRFCF tCH
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CHAPTER 27 PACKAGE DRAWINGS
80-PIN PLASTIC QFP (14x14)
A B
60 61
41 40
detail of lead end S C D R Q
80 1
21 20
F J G P H I
M
K S N S L M
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 17.200.20 14.000.20 14.000.20 17.200.20 0.825 0.825 0.320.06 0.13 0.65 (T.P.) 1.600.20 0.800.20 0.17 +0.03 -0.07 0.10 1.400.10 0.1250.075 +7 3 -3 1.70 MAX. P80GC-65-8BT-1
NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.
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CHAPTER 27 PACKAGE DRAWINGS
80-PIN PLASTIC TQFP (FINE PITCH) (12x12)
A B
60 61
41 40
detail of lead end S C D P T
80 1 F G H I
M
21 20 Q J
R
L U
K S N
NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition.
S
M
ITEM A B C D F G H I J K L M N P Q R S T U
MILLIMETERS 14.00.2 12.00.2 12.00.2 14.00.2 1.25 1.25 0.220.05 0.08 0.5 (T.P.) 1.00.2 0.5 0.1450.05 0.08 1.0 0.10.05 +4 3 -3 1.10.1 0.25 0.60.15 P80GK-50-9EU-1
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CHAPTER 27 PACKAGE DRAWINGS
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
A B
75 76
51 50
detail of lead end S CD Q R
100 1
26 25
F G P H I
M
J K S
N
S L M
NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 16.000.20 14.000.20 14.000.20 16.000.20 1.00 1.00 0.22 +0.05 -0.04 0.08 0.50 (T.P.) 1.000.20 0.500.20 0.17 +0.03 -0.07 0.08 1.400.05 0.100.05 3 +7 -3 1.60 MAX.
S100GC-50-8EU, 8EA-2
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CHAPTER 27 PACKAGE DRAWINGS
144-PIN PLASTIC LQFP (FINE PITCH) (20x20)
A B
108 109 73 72
detail of lead end
S C D R Q
144 1
37 36
F G H
I
M
J
P
K S L M
N
NOTE
S
Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 22.00.2 20.00.2 20.00.2 22.00.2 1.25 1.25 0.220.05 0.08 0.5 (T.P.) 1.00.2 0.50.2 0.17 +0.03 -0.07 0.08 1.4 0.100.05 3 +4 -3 1.50.1 S144GJ-50-UEN
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CHAPTER 28 RECOMMENDED SOLDERING CONDITIONS
The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 should be soldered and mounted under the following recommended conditions. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. Table 28-1. Surface Mounting Type Soldering Conditions (1/3) (1) PD703208GK-xxx-9EU: 80-pin plastic TQFP (fine pitch) (12 x 12)
PD703208YGK-xxx-9EU: 80-pin plastic TQFP (fine pitch) (12 x 12) PD703209GK-xxx-9EU: 80-pin plastic TQFP (fine pitch) (12 x 12) PD703209YGK-xxx-9EU: 80-pin plastic TQFP (fine pitch) (12 x 12) PD703210GK-xxx-9EU: 80-pin plastic TQFP (fine pitch) (12 x 12) PD703210YGK-xxx-9EU: 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic TQFP (fine pitch) (12 x 12) PD70F3210GK-9EU: PD70F3210YGK-9EU: PD703212GC-xxx-8EU:
80-pin plastic TQFP (fine pitch) (12 x 12) 100-pin plastic LQFP (fine pitch) (14 x 14)
PD703212YGC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) PD703213GC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) PD703213YGC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) PD703214GC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) PD703214YGC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) PD70F3214GC-8EU: PD70F3214YGC-8EU:
Soldering Method
100-pin plastic LQFP (fine pitch) (14 x 14)
Soldering Conditions Recommended Condition Symbol IR35-107-2
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 10 to 72 hours) Package peak temperature: 215C, Time: 25 to 40 seconds (at 200C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 10 to 72 hours) Pin temperature: 350C max., Time: 3 seconds max. (per pin row)
VPS
VP15-107-2
Partial heating
-
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating).
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CHAPTER 28 RECOMMENDED SOLDERING CONDITIONS
Table 28-1. Surface Mounting Type Soldering Conditions (2/3) (2) PD703208GC-xxx-8BT: 80-pin plastic QFP (14 x 14) PD703208YGC-xxx-8BT: 80-pin plastic QFP (14 x 14) PD703209GC-xxx-8BT: 80-pin plastic QFP (14 x 14)
PD703209YGC-xxx-8BT: 80-pin plastic QFP (14 x 14) PD703210GC-xxx-8BT: 80-pin plastic QFP (14 x 14) PD703210YGC-xxx-8BT: 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) PD70F3210GC-8BT: PD70F3210YGC-8BT:
Soldering Method
80-pin plastic QFP (14 x 14)
Soldering Conditions Recommended Condition Symbol IR35-107-2
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 10 to 72 hours) Package peak temperature: 215C, Time: 25 to 40 seconds (at 200C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 10 to 72 hours) Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120C max. (package surface temperature), Exposure limit: 7 daysNote (after that, prebake at 125C for 10 hours) Pin temperature: 350C max., Time: 3 seconds max. (per pin row)
VPS
VP15-107-2
Wave soldering
WS60-107-1
Partial heating
-
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating).
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Table 28-1. Surface Mounting Type Soldering Conditions (3/3) (3) PD703216GJ-xxx-UEN: 144-pin plastic LQFP (fine pitch) (20 x 20) PD703216YGJ-xxx-UEN: 144-pin plastic LQFP (fine pitch) (20 x 20) PD703217GJ-xxx-UEN: 144-pin plastic LQFP (fine pitch) (20 x 20)
PD703217YGJ-xxx-UEN: 144-pin plastic LQFP (fine pitch) (20 x 20)
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-103-2
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less, Exposure limit: 3 daysNote (after that, prebake at 125C for 10 to 72 hours) Package peak temperature: 215C, Time: 25 to 40 seconds (at 200C or higher), Count: Two times or less, Exposure limit: 3 daysNote (after that, prebake at 125C for 10 to 72 hours) Pin temperature: 350C max., Time: 3 seconds max. (per pin row)
VPS
VP15-103-2
Partial heating
-
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). (4) PD70F3217GJ- UEN: 144-pin plastic LQFP (fine pitch) (20 x 20)
PD70F3217YGJ-UEN: 144-pin plastic LQFP (fine pitch) (20 x 20)
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-363-2
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less, Exposure limit: 3 daysNote (after that, prebake at 125C for 36 hours) Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Two times or less, Exposure limit: 3 daysNote (after that, prebake at 125C for 36 hours) Pin temperature: 350C max., Time: 3 seconds max. (per pin row)
VPS
VP15-363-2
Partial heating
-
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating).
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APPENDIX A REGISTER INDEX
(1/7)
Symbol ADCR ADIC ADM ADS ADTC0 ADTC1 ADTI0 ADTI1 ADTP0 ADTP1 ASIF0 ASIF1 ASIF2 ASIM0 ASIM1 ASIM2 ASIS0 ASIS1 ASIS2 AWC BCC BRGC0 BRGC1 BRGC2 BRGCA0 BRGCA1 BRGIC BSC CKSR0 CKSR1 CKSR2 CMP00 CMP01 CMP10 CMP11 CORAD0 CORAD1 CORAD2 CORAD3 A/D conversion result register Interrupt control register A/D converter mode register Analog input channel specification register Automatic data transfer address count register 0 Automatic data transfer address count register 1 Automatic data transfer interval specification register 0 Automatic data transfer interval specification register 1 Automatic data transfer address point specification register 0 Automatic data transfer address point specification register 1 Asynchronous serial interface transmission status register 0 Asynchronous serial interface transmission status register 1 Asynchronous serial interface transmission status register 2 Asynchronous serial interface mode register 0 Asynchronous serial interface mode register 1 Asynchronous serial interface mode register 2 Asynchronous serial interface status register 0 Asynchronous serial interface status register 1 Asynchronous serial interface status register 2 Address wait control register Bus cycle control register Baud rate generator control register 0 Baud rate generator control register 1 Baud rate generator control register 2 Divisor selection register 0 Divisor selection register 1 Interrupt control register Bus size configuration register Clock selection register 0 Clock selection register 1 Clock selection register 2 8-bit timer H compare register 00 8-bit timer H compare register 01 8-bit timer H compare register 10 8-bit timer H compare register 11 Correction address register 0 Correction address register 1 Correction address register 2 Correction address register 3 Name Unit ADC INTC ADC ADC CSI CSI CSI CSI CSI CSI UART UART UART UART UART UART UART UART UART BCU BCU BRG BRG BRG UART UART BCU BCU UART UART UART Timer Timer Timer Timer ROMC ROMC ROMC ROMC Page 421 629 423 425 504 504 510, 527 510, 527 508, 525 508, 525 449 449 449 445 445 445 448 448 448 280 281 467 467 467 508, 516, 525 508, 516, 525 629 270 466 466 466 371 371 371 371 678 678 678 678
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APPENDIX A REGISTER INDEX
(2/7)
Symbol CORCN CR000 CR001 CR010 CR011 CR020 CR021 CR030 CR031 CR040 CR041 CR050 CR051 CR5 CR50 CR51 CRC00 CRC01 CRC02 CRC03 CRC04 CRC05 CSI0IC0 CSI0IC1 CSI0IC2 CSIA0Bn CSIA1Bn CSIAIC0 CSIAIC1 CSIC0 CSIC1 CSIC2 CSIM00 CSIM01 CSIM02 CSIMA0 CSIMA1 CSIS0 CSIS1 CSIT0 CSIT1 DACS0 DACS1 DAM Correction control register 16-bit timer capture/compare register 000 16-bit timer capture/compare register 001 16-bit timer capture/compare register 010 16-bit timer capture/compare register 011 16-bit timer capture/compare register 020 16-bit timer capture/compare register 021 16-bit timer capture/compare register 030 16-bit timer capture/compare register 031 16-bit timer capture/compare register 040 16-bit timer capture/compare register 041 16-bit timer capture/compare register 050 16-bit timer capture/compare register 051 16-bit timer compare register 5 8-bit timer compare register 50 8-bit timer compare register 51 Capture/compare control register 00 Capture/compare control register 01 Capture/compare control register 02 Capture/compare control register 03 Capture/compare control register 04 Capture/compare control register 05 Interrupt control register Interrupt control register Interrupt control register CSIA0 buffer RAMn (n = 0 to F) CSIA1 buffer RAMn (n = 0 to F) Interrupt control register Interrupt control register Clocked serial interface clock selection register 0 Clocked serial interface clock selection register 1 Clocked serial interface clock selection register 2 Clocked serial interface mode register 00 Clocked serial interface mode register 01 Clocked serial interface mode register 02 Serial operation mode specification register 0 Serial operation mode specification register 1 Serial status register 0 Serial status register 1 Serial trigger register 0 Serial trigger register 1 D/A conversion value setting register 0 D/A conversion value setting register 1 D/A converter mode register Name Unit ROMC Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer INTC INTC INTC CSI CSI INTC INTC CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI DAC DAC DAC Page 679 305 307 305 307 305 307 305 307 305 307 305 307 352 352 352 310 310 310 310 310 310 629 629 629 510 510 629 629 479 479 479 477 477 477 505, 514, 522 505, 514, 522 506, 515, 523 506, 515, 523 507, 524 507, 524 438 438 437
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Symbol DWC0 EXIMC IIC0 IIC1 IICC0 IICC1 IICCL0 IICCL1 IICF0 IICF1 IICIC0 IICIC1 IICS0 IICS1 IICX0 IICX1 IMR0 IMR1 IMR2 INTF0 INTF9H INTR0 INTR9H ISPR KRIC KRM OSTS P0 P1 P3 P4 P5 P6 P7 P8 P9 PCC PCD PCM PCS PCT PDH PDL PF3H Data wait control register 0 External bus interface mode control register IIC shift register 0 IIC shift register 1 IIC control register 0 IIC control register 1 IIC clock selection register 0 IIC clock selection register 1 IIC flag register 0 IIC flag register 1 Interrupt control register Interrupt control register IIC status register 0 IIC status register 1 IIC function expansion register 0 IIC function expansion register 1 Interrupt mask register 0 Interrupt mask register 1 Interrupt mask register 2 External interrupt falling edge specification register 0 External interrupt falling edge specification register 9H External interrupt rising edge specification register 0 External interrupt rising edge specification register 9H In-service priority register Interrupt control register Key return mode register Oscillation stabilization time selection register Port 0 register Port 1 register Port 3 register Port 4 register Port 5 register Port 6 register Port 7 register Port 8 register Port 9 register Processor clock control register Port CD register Port CM register Port CS register Port CT register Port DH register Port DL register Port 3 function register H Name Unit BCU BCU I2C IC I2C IC I2C IC IC I2C INTC INTC I2C I2C I2C IC INTC INTC INTC INTC INTC INTC INTC INTC INTC KR WDT Port Port Port Port Port Port Port Port Port CG Port Port Port Port Port Port Port
2 2 2 2 2
Page 277 269 562 562 550 550 560 560 558 558 629 629 555 555 561 561 634 634 634 145, 620 216, 641 146, 620 216, 641 637 629 655 298, 410 143 150 155 166 173 183 196 199 206 295 224 228 235 241 247 252 158
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Symbol PF4 PF5 PF6 PF8 PF9H PFC3 PFC5 PFC6H PFC8 PFC9 PFM PFT PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 PLLCTL PM0 PM1 PM3 PM4 PM5 PM6 PM8 PM9 PMC0 PMC3 PMC4 PMC5 PMC6 PMC8 PMC9 PMCCM PMCCS PMCCT PMCDH PMCDL PMCD PMCM PMCS PMCT Port 4 function register Port 5 function register Port 6 function register Port 8 function register Port 9 function register H Port 3 function control register Port 5 function control register Port 6 function control register H Port 8 function control register Port 9 function control register Power-fail comparison mode register Power-fail comparison threshold value register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register PLL control register Port 0 mode register Port 1 mode register Port 3 mode register Port 4 mode register Port 5 mode register Port 6 mode register Port 8 mode register Port 9 mode register Port 0 mode control register Port 3 mode control register Port 4 mode control register Port 5 mode control register Port 6 mode control register Port 8 mode control register Port 9 mode control register Port CM mode control register Port CS mode control register Port CT mode control register Port DH mode control register Port DL mode control register Port CD mode register Port CM mode register Port CS mode register Port CT mode register Name Unit Port Port Port Port Port Port Port Port Port Port ADC ADC INTC INTC INTC INTC INTC INTC INTC CG Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Page 167 175 186 200 211 158 176 186 201 211 426 421 629 629 629 629 629 629 629 300, 399 143 150 156 166 173 184 199 207 144 157 167 174 185 200 207 230 237 243 249 253 225 229 236 242
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Symbol PMDH PMDL PRCMD PRM00 PRM01 PRM02 PRM03 PRM04 PRM05 PRSCM PRSM PSC PSMR PU0 PU1 PU3 PU4 PU5 PU6 PU8 PU9 RTBH0 RTBH1 RTBL0 RTBL1 RTPC0 RTPC1 RTPM0 RTPM1 RXB0 RXB1 RXB2 SIOA0 SIOA1 SIRB0 SIRB0L SIRB1 SIRB1L SIRB2 SIRB2L SIRBE0 SIRBE0L SIRBE1 SIRBE1L Port DH mode register Port DL mode register Command register Prescaler mode register 00 Prescaler mode register 01 Prescaler mode register 02 Prescaler mode register 03 Prescaler mode register 04 Prescaler mode register 05 Prescaler compare register Prescaler mode register Power save control register Power save mode register Pull-up resistor option register 0 Pull-up resistor option register 1 Pull-up resistor option register 3 Pull-up resistor option register 4 Pull-up resistor option register 5 Pull-up resistor option register 6 Pull-up resistor option register 8 Pull-up resistor option register 9 Real-time output buffer register H0 Real-time output buffer register H1 Real-time output buffer register L0 Real-time output buffer register L1 Real-time output port control register 0 Real-time output port control register 1 Real-time output port mode register 0 Real-time output port mode register 1 Receive buffer register 0 Receive buffer register 1 Receive buffer register 2 Serial I/O shift register A0 Serial I/O shift register A1 Clocked serial interface receive buffer register 0 Clocked serial interface receive buffer register 0L Clocked serial interface receive buffer register 1 Clocked serial interface receive buffer register 1L Clocked serial interface receive buffer register 2 Clocked serial interface receive buffer register 2L Clocked serial interface read-only receive buffer register 0 Clocked serial interface read-only receive buffer register 0L Clocked serial interface read-only receive buffer register 1 Clocked serial interface read-only receive buffer register 1L Name Unit Port Port CPU Timer Timer Timer Timer Timer Timer Timer CG CG CG Port Port Port Port Port Port Port Port RTP RTP RTP RTP RTP RTP RTP RTP UART UART UART CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI Page 248 253 132 313 314 315 316 317 318 407 406 297 298 145 151 159 168 177 187 201 215 393 393 393 393 395 395 394 394 450 450 450 504 504 480 480 480 480 480 480 481 481 481 481
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Symbol SIRBE2 SIRBE2L SOTB0 SOTB0L SOTB1 SOTB1L SOTB2 SOTB2L SOTBF0 SOTBF0L SOTBF1 SOTBF1L SOTBF2 SOTBF2L SREIC0 SREIC1 SREIC2 SRIC0 SRIC1 SRIC2 STIC0 STIC1 STIC2 SVA1 SVA0 SYS TCL5 TCL50 TCL51 TM00 TM01 TM02 TM03 TM04 TM05 TM0IC00 TM0IC01 TM0IC10 TM0IC11 TM0IC20 TM0IC21 TM0IC30 TM0IC31 TM0IC40 Name Clocked serial interface read-only receive buffer register 2 Clocked serial interface read-only receive buffer register 2L Clocked serial interface transmit buffer register 0 Clocked serial interface transmit buffer register 0L Clocked serial interface transmit buffer register 1 Clocked serial interface transmit buffer register 1L Clocked serial interface transmit buffer register 2 Clocked serial interface transmit buffer register 2L Clocked serial interface first stage transmit buffer register 0 Clocked serial interface first stage transmit buffer register 0L Clocked serial interface first stage transmit buffer register 1 Clocked serial interface first stage transmit buffer register 1L Clocked serial interface first stage transmit buffer register 2 Clocked serial interface first stage transmit buffer register 2L Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Slave address register 1 Slave address register 0 System status register Timer clock selection register 5 Timer clock selection register 50 Timer clock selection register 51 16-bit timer counter 00 16-bit timer counter 01 16-bit timer counter 02 16-bit timer counter 03 16-bit timer counter 04 16-bit timer counter 05 Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Unit CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI INTC INTC INTC INTC INTC INTC INTC INTC INTC IC IC CPU Timer Timer Timer Timer Timer Timer Timer Timer Timer INTC INTC INTC INTC INTC INTC INTC INTC INTC
2 2
Page 481 481 482 482 482 482 482 482 483 483 483 483 483 483 629 629 629 629 629 629 629 629 629 562 562 132 351 353 353 304 304 304 304 304 304 629 629 629 629 629 629 629 629 629
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Symbol TM0IC41 TM0IC50 TM0IC51 TM5 TM50 TM51 TM5IC0 TM5IC1 TMC00 TMC01 TMC02 TMC03 TMC04 TMC05 TMC5 TMC50 TMC51 TMCYC0 TMCYC1 TMHIC0 TMHIC1 TMHMD0 TMHMD1 TOC00 TOC01 TOC02 TOC03 TOC04 TOC05 TXB0 TXB1 TXB2 VSWC WDCS WDT1IC WDTE WDTM1 WDTM2 WTIC WTIIC WTM Interrupt control register Interrupt control register Interrupt control register 16-bit timer counter 5 8-bit timer counter 50 8-bit timer counter 51 Interrupt control register Interrupt control register 16-bit timer mode control register 00 16-bit timer mode control register 01 16-bit timer mode control register 02 16-bit timer mode control register 03 16-bit timer mode control register 04 16-bit timer mode control register 05 16-bit timer mode control register 5 8-bit timer mode control register 50 8-bit timer mode control register 51 8-bit timer H carrier control register 0 8-bit timer H carrier control register 1 Interrupt control register Interrupt control register 8-bit timer H mode register 0 8-bit timer H mode register 1 16-bit timer output control register 00 16-bit timer output control register 01 16-bit timer output control register 02 16-bit timer output control register 03 16-bit timer output control register 04 16-bit timer output control register 05 Transmit buffer register 0 Transmit buffer register 1 Transmit buffer register 2 System wait control register Watchdog timer clock selection register Interrupt control register Watchdog timer enable register Watchdog timer mode register 1 Watchdog timer mode register 2 Interrupt control register Interrupt control register Watch timer operation mode register Name Unit INTC INTC INTC Timer Timer Timer INTC INTC Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer INTC INTC Timer Timer Timer Timer Timer Timer Timer Timer UART UART UART CPU WDT INTC WDT WDT WDT INTC INTC WT Page 629 629 629 351 352 352 629 629 308 308 308 308 308 308 351 354 354 375 375 629 629 372 372 310 310 310 310 310 310 451 451 451 134 411 629 418 412, 639 417, 639 629 629 402
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APPENDIX B REVISION HISTORY
The following table shows the revision history up to this edition. The "Applied to:" column indicates the chapters of each edition in which the revision was applied. (1/3)
Edition 2nd Major Revision from Previous Edition Change of description in Figure 12-1 Block Diagram of D/A Converter Applied to: CHAPTER 12 D/A CONVERTER CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION CHAPTER 21 ELECTRICAL SPECIFICATIONS (TARGET VALUES) CHAPTER 22 PACKAGE DRAWINGS APPENDIX A REGISTER INDEX Throughout
Addition of Caution in 14.3.4 Interrupt control register (xxICn) Addition of Caution in 14.3.6 In-service priority register (ISPR) Addition of CHAPTER 21 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
Addition of CHAPTER 22 PACKAGE DRAWINGS Addition of APPENDIX A REGISTER INDEX 3rd * Addition of the following special quality grade products. PD703208(A), 703208Y(A), 703209(A), 703209Y(A), 703210(A), 703210Y(A), 703212(A), 703212Y(A), 703213(A), 703213Y(A), 703214(A), 703214Y(A), 703216(A), 703216Y(A), 703217(A), 703217Y(A), 70F3210(A), 70F3210Y(A), 70F3214(A), 70F3214Y(A), 70F3217(A), 70F3217Y(A) Addition of Caution in 1.2.4 Pin configuration (top view) (V850ES/KF1) Addition of Caution in 1.3.4 Pin configuration (top view) (V850ES/KG1) Addition of Caution in 1.4.4 Pin configuration (top view) (V850ES/KJ1) Addition of description in CHAPTER 2 PIN FUNCTIONS and addition of Table 2-1 Pin I/O Buffer Power Supplies Modification of description on recommended connection of P70 to P77, P78 to P715, IC, VPP, and XT1 in 2.4 Pin I/O Circuits and Recommended Connection of Unused Pins Modification of description in 3.4.8 (2) Access to special on-chip peripheral I/O registers Modification of description in 5.11 Bus Timing Addition of 5.12 Cautions Addition of description on the main clock oscillator in 6.1 Overview Addition of description in 6.2 (1) Main clock oscillator Addition of Caution 3 in 6.3 (1) Processor clock control register (PCC) Addition of description in CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 Modification of description of Caution 4 in 7.2 (2) 16-bit timer capture/compare register 0n0 (CR0n0) Modification of description of Caution 4 in 7.2 (3) 16-bit timer capture/compare register 0n1 (CR0n1) Modification of description of Caution 1 in 7.3 (3) 16-bit timer output control register 0n (TOC0n) Addition of setting procedures and modification of description in 7.4.1 Operation as interval timer (16 bits)
CHAPTER 1 INTRODUCTION
CHAPTER 2 PIN FUNCTIONS
CHAPTER 3 CPU FUNCTIONS CHAPTER 5 BUS CONTROL FUNCTION CHAPTER 6 CLOCK GENERATION FUNCTION
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05
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Edition 3rd Major Revision from Previous Edition Addition of setting procedures in 7.4.2 PPG output operation Addition of Figure 7-6 Configuration of PPG Output Addition of Figure 7-7 PPG Output Operation Timing Addition of setting procedures in 7.4.3 Pulse width measurement Addition of setting procedures and addition of Caution 2 in 7.4.4 Operation as external event counter Addition of setting procedures and addition of Caution in 7.4.5 Square-wave output operation Addition of setting procedures in 7.4.6 One-shot pulse output operation Addition of Caution 2 in 7.4.6 (1) One-shot pulse output with software trigger (16-bit timer/event counters 00, 01, 04 and 05 only) Addition of Caution 2 in 7.4.6 (2) One-shot pulse output with external trigger (16-bit timer/event counters 04 and 05 only) Addition of Caution in 7.4.7 (10) (b) When setting CR0n0, CR0n1 to compare mode Addition of description in CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 CHAPTER 9 8-BIT TIMERS H0 AND H1 Applied to: CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05
Addition of description in CHAPTER 9 8-BIT TIMERS H0 AND H1 Addition of Caution 3 in 9.3 (1) (a) 8-bit timer H mode register 0 (TMHMD0) Addition of Caution 3 in 9.3 (1) (b) 8-bit timer H mode register 1 (TMHMD1) Addition of Caution 2 in Figure 9-7 Transfer Timing Addition of Caution 4 in 9.4.3 (4) Timing chart Addition of 13.4 Relationship Between Analog Input Voltage and A/D Conversion Result Addition of 13.6 (3) A/D converter sampling time and A/D conversion start delay time Addition of 13.7 How to Read A/D Converter Characteristics Table Addition of description in CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) Modification of description in Figure 15-6 Continuous Transmission Starting Procedure Addition of description in CHAPTER 16 CLOCKED SERIAL INTERFACE 0 (CSI0)
CHAPTER 13 A/D CONVERTER
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) CHAPTER 16 CLOCKED SERIAL INTERFACE 0 (CSI0) CHAPTER 17 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION CHAPTER 18 I2C BUS CHAPTER 25 FLASH MEMORY
Modification of description in CHAPTER 17 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION
Addition of description in CHAPTER 18 I2C BUS Addition to Cautions in Table 25-1 Wiring Between PD70F3210 and 70F3210Y (V850ES/KF1), and PG-FP3 Addition of Figure 25-1 Wiring Example of V850ES/KF1 Flash Writing Adapter (FA80GC-8BT, FA-80GK-9EU) Addition of Cautions in Table 25-2 Wiring Between PD70F3214 and 70F3214Y (V850ES/KG1), and PG-FP3
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APPENDIX B REVISION HISTORY
(3/3)
Edition 3rd Major Revision from Previous Edition Addition of Figure 25-2 Wiring Example of V850ES/KG1 Flash Writing Adapter (FA100GC-8EU) Addition of Cautions in Table 25-3 Wiring Between PD70F3217 and 70F3217Y (V850ES/KJ1), and PG-FP3 Addition of Figure 25-3 Wiring Example of V850ES/KJ1 Flash Writing Adapter (FA144GJ-UEN) Addition of Note 1 and description in Absolute Maximum Ratings in CHAPTER 26 ELECTRICAL SPECIFICATIONS Addition of description on storage temperature in Absolute Maximum Ratings in CHAPTER 26 ELECTRICAL SPECIFICATIONS Addition of (i) Murata Manufacturing Co., Ltd.: Ceramic resonator (TA = -40 to +85C) in CHAPTER 26 ELECTRICAL SPECIFICATIONS Change of values of supply current (flash memory version) in DC Characteristics in CHAPTER 26 ELECTRICAL SPECIFICATIONS Change of values of supply current (mask ROM version) in DC Characteristics in CHAPTER 26 ELECTRICAL SPECIFICATIONS Addition of Caution and a timing chart in Data Retention Characteristics in CHAPTER 26 ELECTRICAL SPECIFICATIONS Addition of Caution in Bus Timing (1) (a) CLKOUT asynchronous: In multiplex bus mode (2/2) in CHAPTER 26 ELECTRICAL SPECIFICATIONS Addition of Caution 2 in Bus Timing (2) (a) Read cycle (CLKOUT asynchronous): In separate bus mode (1/2) in CHAPTER 26 ELECTRICAL SPECIFICATIONS Addition of Cautions in Bus Timing (2) (a) Read cycle (CLKOUT asynchronous): In separate bus mode (2/2) in CHAPTER 26 ELECTRICAL SPECIFICATIONS Addition of Caution 2 in Bus Timing (2) (c) Write cycle (CLKOUT asynchronous): In separate bus mode (1/2) in CHAPTER 26 ELECTRICAL SPECIFICATIONS Addition of Cautions in Bus Timing (2) (c) Write cycle (CLKOUT asynchronous): In separate bus mode (2/2) in CHAPTER 26 ELECTRICAL SPECIFICATIONS Addition of description in Basic Operation in CHAPTER 26 ELECTRICAL SPECIFICATIONS Addition of description in Flash Memory Programming Characteristics in CHAPTER 26 ELECTRICAL SPECIFICATIONS Addition of CHAPTER 28 RECOMMENDED SOLDERING CONDITIONS CHAPTER 28 RECOMMENDED SOLDERING CONDITIONS APPENDIX B REVISION HISTORY CHAPTER 26 ELECTRICAL SPECIFICATIONS Applied to: CHAPTER 25 FLASH MEMORY
Addition of APPENDIX B REVISION HISTORY
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